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Differential D125240

[AArch64] Baseline test for D125307
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Authored by arichardson on May 9 2022, 8:42 AM.

Details

Reviewers
dmgreen
Commits
rGf8639133b58d: [AArch64] Baseline test for D125307

Diff Detail

Unit TestsFailed

TimeTest
60,130 msx64 debian > AddressSanitizer-x86_64-linux-dynamic.TestCases::scariness_score_test.cpp
60,150 msx64 debian > AddressSanitizer-x86_64-linux.TestCases::scariness_score_test.cpp
60,020 msx64 debian > libFuzzer.libFuzzer::fuzzer-leak.test
60,030 msx64 debian > libFuzzer.libFuzzer::minimize_crash.test
60,030 msx64 debian > libFuzzer.libFuzzer::out-of-process-fuzz.test
View Full Test Results (6 Failed)

Event Timeline

arichardson created this revision.May 9 2022, 8:42 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 9 2022, 8:42 AM
Herald added a subscriber: kristof.beyls. · View Herald Transcript
Harbormaster completed remote builds in B163498: Diff 428100.May 9 2022, 9:57 AM
arichardson updated this revision to Diff 428341.May 10 2022, 4:49 AM

rebase on top of D125307

arichardson added a parent revision: D125307: [update_llc_test_checks] Use FileCheck captures for MCInst/MCReg output.May 10 2022, 5:06 AM
arichardson added a child revision: D125308: [AArch64] Add missing HasNEON predicates to int->float patterns.
arichardson published this revision for review.May 10 2022, 5:08 AM
arichardson retitled this revision from [AArch64] Baseline test for DXXXXX to [AArch64] Baseline test for D125307.
Herald added a project: Restricted Project. · View Herald TranscriptMay 10 2022, 5:09 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B163674: Diff 428341.May 10 2022, 5:34 AM
dmgreen added a subscriber: dmgreen.May 12 2022, 2:06 AM

Do we need --asm-show-inst, or is it enough to just show the instructions? It seems quite verbose for the information it gives.

arichardson updated this revision to Diff 428889.May 12 2022, 2:35 AM

regen with D125405

Harbormaster completed remote builds in B164066: Diff 428889.May 12 2022, 2:36 AM
arichardson added a comment.May 12 2022, 3:04 AM
In D125240#3508421, @dmgreen wrote:

Do we need --asm-show-inst, or is it enough to just show the instructions? It seems quite verbose for the information it gives.

I initially thought we did, but it turns out the register operands are different so there are still separate CHECK lines for neon/non-neon. Will update to remove.

arichardson updated this revision to Diff 428896.May 12 2022, 3:05 AM

drop --asm-show-inst

Harbormaster completed remote builds in B164069: Diff 428896.May 12 2022, 3:06 AM
arichardson removed a parent revision: D125307: [update_llc_test_checks] Use FileCheck captures for MCInst/MCReg output.May 12 2022, 3:09 AM
dmgreen accepted this revision.May 12 2022, 3:15 AM

Thanks. LGTM

This revision is now accepted and ready to land.May 12 2022, 3:15 AM
This revision was landed with ongoing or failed builds.May 14 2022, 7:43 AM
Closed by commit rGf8639133b58d: [AArch64] Baseline test for D125307 (authored by arichardson). · Explain Why
This revision was automatically updated to reflect the committed changes.
arichardson added a commit: rGf8639133b58d: [AArch64] Baseline test for D125307.

Revision Contents

PathSize
llvm/
test/
CodeGen/
AArch64/
496 lines

Diff 428341

llvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;; These test functions previously triggered the following error when emitting machine code:
;; LLVM ERROR: Attempting to emit UCVTFv1i64 instruction but the Feature_HasNEON predicate(s) are not met
; RUN: llc -mtriple=aarch64 -mattr=+neon,+fullfp16 --asm-show-inst < %s | FileCheck %s --check-prefixes=CHECK,NEON-ENABLED
; RUN: llc -mtriple=aarch64 -mattr=-neon,+fullfp16 --asm-show-inst < %s | FileCheck %s --check-prefixes=CHECK,NEON-DISABLED
;; Emit an object file so that verifyPredicates is called (it is not used for ASM output).
; RUNTODO: llc -mtriple=aarch64 -mattr=-neon,+fullfp16 -o /dev/null %s --asm-show-inst -filetype=obj
define double @ui8_to_double(i8* %i, float* %f) {
; CHECK-LABEL: ui8_to_double:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr b0, [x0] // <MCInst #[[#]] LDRBui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: ucvtf d0, d0 // <MCInst #[[#]] UCVTFv1i64
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i8, i8* %i, align 1
%conv = uitofp i8 %ld to double
ret double %conv
}
define float @ui8_to_float(i8* %i, float* %f) {
; CHECK-LABEL: ui8_to_float:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr b0, [x0] // <MCInst #[[#]] LDRBui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: ucvtf s0, s0 // <MCInst #[[#]] UCVTFv1i32
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i8, i8* %i, align 1
%conv = uitofp i8 %ld to float
ret float %conv
}
define half @ui8_to_half(i8* %i, half* %f) {
; CHECK-LABEL: ui8_to_half:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrb w8, [x0] // <MCInst #[[#]] LDRBBui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: ucvtf h0, w8 // <MCInst #[[#]] UCVTFUWHri
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i8, i8* %i, align 1
%conv = uitofp i8 %ld to half
ret half %conv
}
define double @ui16_to_double(i16* %i, float* %f) {
; CHECK-LABEL: ui16_to_double:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr h0, [x0] // <MCInst #[[#]] LDRHui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: ucvtf d0, d0 // <MCInst #[[#]] UCVTFv1i64
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i16, i16* %i, align 1
%conv = uitofp i16 %ld to double
ret double %conv
}
define float @ui16_to_float(i16* %i, float* %f) {
; CHECK-LABEL: ui16_to_float:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr h0, [x0] // <MCInst #[[#]] LDRHui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: ucvtf s0, s0 // <MCInst #[[#]] UCVTFv1i32
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i16, i16* %i, align 1
%conv = uitofp i16 %ld to float
ret float %conv
}
define half @ui16_to_half(i16* %i, half* %f) {
; CHECK-LABEL: ui16_to_half:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrh w8, [x0] // <MCInst #[[#]] LDRHHui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: ucvtf h0, w8 // <MCInst #[[#]] UCVTFUWHri
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i16, i16* %i, align 1
%conv = uitofp i16 %ld to half
ret half %conv
}
define double @ui32_to_double(i32* %i, float* %f) {
; CHECK-LABEL: ui32_to_double:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr s0, [x0] // <MCInst #[[#]] LDRSui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: ucvtf d0, d0 // <MCInst #[[#]] UCVTFv1i64
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i32, i32* %i, align 1
%conv = uitofp i32 %ld to double
ret double %conv
}
define float @ui32_to_float(i32* %i, float* %f) {
; NEON-ENABLED-LABEL: ui32_to_float:
; NEON-ENABLED: // %bb.0: // %entry
; NEON-ENABLED-NEXT: ldr s0, [x0] // <MCInst #[[#]] LDRSui
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-ENABLED-NEXT: // <MCOperand Imm:0>>
; NEON-ENABLED-NEXT: ucvtf s0, s0 // <MCInst #[[#]] UCVTFv1i32
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>>
; NEON-ENABLED-NEXT: ret // <MCInst #[[#]] RET
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>>
;
; NEON-DISABLED-LABEL: ui32_to_float:
; NEON-DISABLED: // %bb.0: // %entry
; NEON-DISABLED-NEXT: ldr w8, [x0] // <MCInst #[[#]] LDRWui
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-DISABLED-NEXT: // <MCOperand Imm:0>>
; NEON-DISABLED-NEXT: ucvtf s0, w8 // <MCInst #[[#]] UCVTFUWSri
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>>
; NEON-DISABLED-NEXT: ret // <MCInst #[[#]] RET
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i32, i32* %i, align 1
%conv = uitofp i32 %ld to float
ret float %conv
}
define half @ui32_to_half(i32* %i, half* %f) {
; CHECK-LABEL: ui32_to_half:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr w8, [x0] // <MCInst #[[#]] LDRWui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: ucvtf h0, w8 // <MCInst #[[#]] UCVTFUWHri
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i32, i32* %i, align 1
%conv = uitofp i32 %ld to half
ret half %conv
}
define double @ui64_to_double(i64* %i, float* %f) {
; NEON-ENABLED-LABEL: ui64_to_double:
; NEON-ENABLED: // %bb.0: // %entry
; NEON-ENABLED-NEXT: ldr d0, [x0] // <MCInst #[[#]] LDRDui
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-ENABLED-NEXT: // <MCOperand Imm:0>>
; NEON-ENABLED-NEXT: ucvtf d0, d0 // <MCInst #[[#]] UCVTFv1i64
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>>
; NEON-ENABLED-NEXT: ret // <MCInst #[[#]] RET
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>>
;
; NEON-DISABLED-LABEL: ui64_to_double:
; NEON-DISABLED: // %bb.0: // %entry
; NEON-DISABLED-NEXT: ldr x8, [x0] // <MCInst #[[#]] LDRXui
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-DISABLED-NEXT: // <MCOperand Imm:0>>
; NEON-DISABLED-NEXT: ucvtf d0, x8 // <MCInst #[[#]] UCVTFUXDri
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>>
; NEON-DISABLED-NEXT: ret // <MCInst #[[#]] RET
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i64, i64* %i, align 1
%conv = uitofp i64 %ld to double
ret double %conv
}
define float @ui64_to_float(i64* %i, float* %f) {
; CHECK-LABEL: ui64_to_float:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr x8, [x0] // <MCInst #[[#]] LDRXui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: ucvtf s0, x8 // <MCInst #[[#]] UCVTFUXSri
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i64, i64* %i, align 1
%conv = uitofp i64 %ld to float
ret float %conv
}
define half @ui64_to_half(i64* %i, half* %f) {
; CHECK-LABEL: ui64_to_half:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr x8, [x0] // <MCInst #[[#]] LDRXui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: ucvtf h0, x8 // <MCInst #[[#]] UCVTFUXHri
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i64, i64* %i, align 1
%conv = uitofp i64 %ld to half
ret half %conv
}
define double @si8_to_double(i8* %i, float* %f) {
; CHECK-LABEL: si8_to_double:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrsb w8, [x0] // <MCInst #[[#]] LDRSBWui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: scvtf d0, w8 // <MCInst #[[#]] SCVTFUWDri
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i8, i8* %i, align 1
%conv = sitofp i8 %ld to double
ret double %conv
}
define float @si8_to_float(i8* %i, float* %f) {
; CHECK-LABEL: si8_to_float:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrsb w8, [x0] // <MCInst #[[#]] LDRSBWui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: scvtf s0, w8 // <MCInst #[[#]] SCVTFUWSri
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i8, i8* %i, align 1
%conv = sitofp i8 %ld to float
ret float %conv
}
define half @si8_to_half(i8* %i, half* %f) {
; CHECK-LABEL: si8_to_half:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrsb w8, [x0] // <MCInst #[[#]] LDRSBWui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: scvtf h0, w8 // <MCInst #[[#]] SCVTFUWHri
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i8, i8* %i, align 1
%conv = sitofp i8 %ld to half
ret half %conv
}
define double @si16_to_double(i16* %i, float* %f) {
; CHECK-LABEL: si16_to_double:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrsh w8, [x0] // <MCInst #[[#]] LDRSHWui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: scvtf d0, w8 // <MCInst #[[#]] SCVTFUWDri
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i16, i16* %i, align 1
%conv = sitofp i16 %ld to double
ret double %conv
}
define float @si16_to_float(i16* %i, float* %f) {
; CHECK-LABEL: si16_to_float:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr h0, [x0] // <MCInst #[[#]] LDRHui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: sshll v0.4s, v0.4h, #0 // <MCInst #[[#]] SSHLLv4i16_shift
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: scvtf s0, s0 // <MCInst #[[#]] SCVTFv1i32
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i16, i16* %i, align 1
%conv = sitofp i16 %ld to float
ret float %conv
}
define half @si16_to_half(i16* %i, half* %f) {
; CHECK-LABEL: si16_to_half:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrsh w8, [x0] // <MCInst #[[#]] LDRSHWui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: scvtf h0, w8 // <MCInst #[[#]] SCVTFUWHri
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i16, i16* %i, align 1
%conv = sitofp i16 %ld to half
ret half %conv
}
define double @si32_to_double(i32* %i, float* %f) {
; CHECK-LABEL: si32_to_double:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr s0, [x0] // <MCInst #[[#]] LDRSui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: sshll v0.2d, v0.2s, #0 // <MCInst #[[#]] SSHLLv2i32_shift
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: scvtf d0, d0 // <MCInst #[[#]] SCVTFv1i64
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i32, i32* %i, align 1
%conv = sitofp i32 %ld to double
ret double %conv
}
define float @si32_to_float(i32* %i, float* %f) {
; NEON-ENABLED-LABEL: si32_to_float:
; NEON-ENABLED: // %bb.0: // %entry
; NEON-ENABLED-NEXT: ldr s0, [x0] // <MCInst #[[#]] LDRSui
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-ENABLED-NEXT: // <MCOperand Imm:0>>
; NEON-ENABLED-NEXT: scvtf s0, s0 // <MCInst #[[#]] SCVTFv1i32
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>>
; NEON-ENABLED-NEXT: ret // <MCInst #[[#]] RET
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>>
;
; NEON-DISABLED-LABEL: si32_to_float:
; NEON-DISABLED: // %bb.0: // %entry
; NEON-DISABLED-NEXT: ldr w8, [x0] // <MCInst #[[#]] LDRWui
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-DISABLED-NEXT: // <MCOperand Imm:0>>
; NEON-DISABLED-NEXT: scvtf s0, w8 // <MCInst #[[#]] SCVTFUWSri
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>>
; NEON-DISABLED-NEXT: ret // <MCInst #[[#]] RET
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i32, i32* %i, align 1
%conv = sitofp i32 %ld to float
ret float %conv
}
define half @si32_to_half(i32* %i, half* %f) {
; CHECK-LABEL: si32_to_half:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr w8, [x0] // <MCInst #[[#]] LDRWui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: scvtf h0, w8 // <MCInst #[[#]] SCVTFUWHri
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i32, i32* %i, align 1
%conv = sitofp i32 %ld to half
ret half %conv
}
define double @si64_to_double(i64* %i, float* %f) {
; NEON-ENABLED-LABEL: si64_to_double:
; NEON-ENABLED: // %bb.0: // %entry
; NEON-ENABLED-NEXT: ldr d0, [x0] // <MCInst #[[#]] LDRDui
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-ENABLED-NEXT: // <MCOperand Imm:0>>
; NEON-ENABLED-NEXT: scvtf d0, d0 // <MCInst #[[#]] SCVTFv1i64
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>>
; NEON-ENABLED-NEXT: ret // <MCInst #[[#]] RET
; NEON-ENABLED-NEXT: // <MCOperand Reg:[[#]]>>
;
; NEON-DISABLED-LABEL: si64_to_double:
; NEON-DISABLED: // %bb.0: // %entry
; NEON-DISABLED-NEXT: ldr x8, [x0] // <MCInst #[[#]] LDRXui
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-DISABLED-NEXT: // <MCOperand Imm:0>>
; NEON-DISABLED-NEXT: scvtf d0, x8 // <MCInst #[[#]] SCVTFUXDri
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>>
; NEON-DISABLED-NEXT: ret // <MCInst #[[#]] RET
; NEON-DISABLED-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i64, i64* %i, align 1
%conv = sitofp i64 %ld to double
ret double %conv
}
define float @si64_to_float(i64* %i, float* %f) {
; CHECK-LABEL: si64_to_float:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr x8, [x0] // <MCInst #[[#]] LDRXui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: scvtf s0, x8 // <MCInst #[[#]] SCVTFUXSri
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i64, i64* %i, align 1
%conv = sitofp i64 %ld to float
ret float %conv
}
define half @si64_to_half(i64* %i, half* %f) {
; CHECK-LABEL: si64_to_half:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr x8, [x0] // <MCInst #[[#]] LDRXui
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Imm:0>>
; CHECK-NEXT: scvtf h0, x8 // <MCInst #[[#]] SCVTFUXHri
; CHECK-NEXT: // <MCOperand Reg:[[#]]>
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
; CHECK-NEXT: ret // <MCInst #[[#]] RET
; CHECK-NEXT: // <MCOperand Reg:[[#]]>>
entry:
%ld = load i64, i64* %i, align 1
%conv = sitofp i64 %ld to half
ret half %conv
}