[X86] Set MaxVectorAlign for non-Darwin targets as well.

[ab]

Summary

Follow-up to r246229: this isn't Darwin-specific, so let's enable it for all X86 targets.

Quoting r160209, which introduced it:

Currently, if no aligned attribute is specified the alignment of a vector is inferred from its size.  Thus, very large vectors will be over-aligned with no benefit.

I tried to cc people for the various OSes we support; if you object or can suggest other reviewers, please do!

[echristo]

This seems reasonable to me, I can't see why it wouldn't be ok.

Thanks!

-eric

[echristo]

(This ACK btw means "yes we should do this on all platforms", not that it's necessarily safe on any platform, see my mail on the original thread).

-eric

[Eugene.Zelenko]

Looks like patch was not committed.

lib/Basic/Targets.cpp

bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
   // then enable MMX.
   std::vector<std::string>::iterator it;
   it = std::find(Features.begin(), Features.end(), "-mmx");
   if (it != Features.end())
     Features.erase(it);
   else if (SSELevel > NoSSE)
     MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
 
-  SimdDefaultAlign =
+  // We now know the features we have: we can decide how to align vectors.
+  MaxVectorAlign = SimdDefaultAlign =
       hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
   return true;
 }
 
 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
 /// definitions for this particular subtarget.
 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
                                      MacroBuilder &Builder) const {
DarwinI386TargetInfo(const llvm::Triple &Triple)
     LongDoubleWidth = 128;
     LongDoubleAlign = 128;
     SuitableAlign = 128;
     SizeType = UnsignedLong;
     IntPtrType = SignedLong;
     DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
     HasAlignMac68kSupport = true;
   }
-
-  bool handleTargetFeatures(std::vector<std::string> &Features,
-                            DiagnosticsEngine &Diags) override {
-    if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
-                                                                  Diags))
-      return false;
-    // We now know the features we have: we can decide how to align vectors.
-    MaxVectorAlign =
-        hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
-    return true;
-  }
 };
 
 // x86-32 Windows target
 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
 public:
   WindowsX86_32TargetInfo(const llvm::Triple &Triple)
       : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
     WCharType = UnsignedShort;
DarwinX86_64TargetInfo(const llvm::Triple &Triple)
       : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
     Int64Type = SignedLongLong;
     // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
     llvm::Triple T = llvm::Triple(Triple);
     if (T.isiOS())
       UseSignedCharForObjCBool = false;
     DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
   }
-
-  bool handleTargetFeatures(std::vector<std::string> &Features,
-                            DiagnosticsEngine &Diags) override {
-    if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
-                                                                  Diags))
-      return false;
-    // We now know the features we have: we can decide how to align vectors.
-    MaxVectorAlign =
-        hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
-    return true;
-  }
 };
 
 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
 public:
   OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
       : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
     IntMaxType = SignedLongLong;
     Int64Type = SignedLongLong;

test/CodeGen/const-init.c

 }
 
 void g28() {
   typedef long long v1i64 __attribute((vector_size(8)));
   typedef short v12i16 __attribute((vector_size(24)));
   typedef long double v2f80 __attribute((vector_size(24)));
   // CHECK: @g28.a = internal global <1 x i64> <i64 10>
   // CHECK: @g28.b = internal global <12 x i16> <i16 0, i16 0, i16 0, i16 -32768, i16 16383, i16 0, i16 0, i16 0, i16 0, i16 -32768, i16 16384, i16 0>
-  // CHECK: @g28.c = internal global <2 x x86_fp80> <x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000>, align 32
+  // CHECK: @g28.c = internal global <2 x x86_fp80> <x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000>, align 16
   static v1i64 a = (v1i64)10LL;
   static v12i16 b = (v2f80){1,2};
   static v2f80 c = (v12i16){0,0,0,-32768,16383,0,0,0,0,-32768,16384,0};
 }
 
 // PR13643
 void g29() {
   typedef char DCC_PASSWD[2];

test/CodeGen/vector-alignment.c

-// RUN: %clang_cc1 -w -triple x86_64-apple-darwin10 \
-// RUN:  -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE
-// RUN: %clang_cc1 -w -triple   i386-apple-darwin10 \
-// RUN:  -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE
-// RUN: %clang_cc1 -w -triple x86_64-apple-darwin10 -target-feature +avx \
-// RUN:  -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX
-// RUN: %clang_cc1 -w -triple   i386-apple-darwin10 -target-feature +avx \
-// RUN:  -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX
-// RUN: %clang_cc1 -w -triple x86_64-apple-darwin10 -target-feature +avx512f \
-// RUN:  -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX512
-// RUN: %clang_cc1 -w -triple   i386-apple-darwin10 -target-feature +avx512f \
-// RUN:  -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX512
-// rdar://11759609
-
-// At or below target max alignment with no aligned attribute should align based
-// on the size of vector.
-double __attribute__((vector_size(16))) v1;
-// SSE: @v1 {{.*}}, align 16
-// AVX: @v1 {{.*}}, align 16
-// AVX512: @v1 {{.*}}, align 16
-double __attribute__((vector_size(32))) v2;
-// SSE: @v2 {{.*}}, align 16
-// AVX: @v2 {{.*}}, align 32
-// AVX512: @v2 {{.*}}, align 32
-
-// Alignment above target max alignment with no aligned attribute should align
-// based on the target max.
-double __attribute__((vector_size(64))) v3;
-// SSE: @v3 {{.*}}, align 16
-// AVX: @v3 {{.*}}, align 32
-// AVX512: @v3 {{.*}}, align 64
-double __attribute__((vector_size(1024))) v4;
-// SSE: @v4 {{.*}}, align 16
-// AVX: @v4 {{.*}}, align 32
-// AVX512: @v4 {{.*}}, align 64
-
-// Aliged attribute should always override.
-double __attribute__((vector_size(16), aligned(16))) v5;
-// ALL: @v5 {{.*}}, align 16
-double __attribute__((vector_size(16), aligned(64))) v6;
-// ALL: @v6 {{.*}}, align 64
-double __attribute__((vector_size(32), aligned(16))) v7;
-// ALL: @v7 {{.*}}, align 16
-double __attribute__((vector_size(32), aligned(64))) v8;
-// ALL: @v8 {{.*}}, align 64
-
-// Check non-power of 2 widths.
-double __attribute__((vector_size(24))) v9;
-// SSE: @v9 {{.*}}, align 16
-// AVX: @v9 {{.*}}, align 32
-// AVX512: @v9 {{.*}}, align 32
-double __attribute__((vector_size(40))) v10;
-// SSE: @v10 {{.*}}, align 16
-// AVX: @v10 {{.*}}, align 32
-// AVX512: @v10 {{.*}}, align 64
-
-// Check non-power of 2 widths with aligned attribute.
-double __attribute__((vector_size(24), aligned(64))) v11;
-// ALL: @v11 {{.*}}, align 64
-double __attribute__((vector_size(80), aligned(16))) v12;
-// ALL: @v12 {{.*}}, align 16

test/CodeGen/x86-vector-alignment.c

-// RUN: %clang_cc1 -w -triple x86_64-apple-darwin10 \
+// RUN: %clang_cc1 -w -triple x86_64-unknown-unknown \
 // RUN:  -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE
-// RUN: %clang_cc1 -w -triple   i386-apple-darwin10 \
+// RUN: %clang_cc1 -w -triple   i386-unknown-unknown \
 // RUN:  -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE
-// RUN: %clang_cc1 -w -triple x86_64-apple-darwin10 -target-feature +avx \
+// RUN: %clang_cc1 -w -triple x86_64-unknown-unknown -target-feature +avx \
 // RUN:  -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX
-// RUN: %clang_cc1 -w -triple   i386-apple-darwin10 -target-feature +avx \
+// RUN: %clang_cc1 -w -triple   i386-unknown-unknown -target-feature +avx \
 // RUN:  -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX
-// RUN: %clang_cc1 -w -triple x86_64-apple-darwin10 -target-feature +avx512f \
+// RUN: %clang_cc1 -w -triple x86_64-unknown-unknown -target-feature +avx512f \
 // RUN:  -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX512
-// RUN: %clang_cc1 -w -triple   i386-apple-darwin10 -target-feature +avx512f \
+// RUN: %clang_cc1 -w -triple   i386-unknown-unknown -target-feature +avx512f \
 // RUN:  -emit-llvm -o - %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX512
-// rdar://11759609
 
 // At or below target max alignment with no aligned attribute should align based
 // on the size of vector.
 double __attribute__((vector_size(16))) v1;
 // SSE: @v1 {{.*}}, align 16
 // AVX: @v1 {{.*}}, align 16
 // AVX512: @v1 {{.*}}, align 16
 double __attribute__((vector_size(32))) v2;

test/CodeGen/x86_64-arguments.c

 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | \
 // RUN:   FileCheck %s -check-prefix=CHECK -check-prefix=SSE -check-prefix=NO-AVX512
 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-feature +avx | \
-// RUN:   FileCheck %s -check-prefix=CHECK -check-prefix=AVX -check-prefix=NO-AVX512
+// RUN:   FileCheck %s -check-prefix=CHECK -check-prefix=AVX -check-prefix=AVXUP -check-prefix=NO-AVX512
 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-feature +avx512f | \
-// RUN:   FileCheck %s -check-prefix=CHECK -check-prefix=AVX -check-prefix=AVX512
+// RUN:   FileCheck %s -check-prefix=CHECK -check-prefix=AVXUP -check-prefix=AVX512
 #include <stdarg.h>
 
 // CHECK-LABEL: define signext i8 @f0()
 char f0(void) {
   return 0;
 }
 
 // CHECK-LABEL: define signext i16 @f1()

 // and return them in the appropriate vector registers if possible.
 
 typedef float v8f32 __attribute__((__vector_size__(32)));
 struct v8f32wrapper {
   v8f32 v;
 };
 
 struct v8f32wrapper f27a(struct v8f32wrapper X) {
-  // AVX-LABEL: define <8 x float> @f27a(<8 x float> %X.coerce)
+  // AVXUP-LABEL: define <8 x float> @f27a(<8 x float> %X.coerce)
   return X;
 }
 
 struct v8f32wrapper_wrapper {
   v8f32 v[1];
 };
 
 struct v8f32wrapper_wrapper f27b(struct v8f32wrapper_wrapper X) {
-  // AVX-LABEL: define <8 x float> @f27b(<8 x float> %X.coerce)
+  // AVXUP-LABEL: define <8 x float> @f27b(<8 x float> %X.coerce)
   return X;
 }
 
 // rdar://5711709
 struct f28c {
   double x;
   int y;
 };

 {
   func(ss);
 }
 
 // CHECK-LABEL: define double @f36(double %arg.coerce)
 typedef unsigned v2i32 __attribute((__vector_size__(8)));
 v2i32 f36(v2i32 arg) { return arg; }
 
-// AVX: declare void @f38(<8 x float>)
-// AVX: declare void @f37(<8 x float>)
-// SSE: declare void @f38(%struct.s256* byval align 32)
-// SSE: declare void @f37(<8 x float>* byval align 32)
+// AVXUP: declare void @f38(<8 x float>)
+// AVXUP: declare void @f37(<8 x float>)
+// SSE: declare void @f38(%struct.s256* byval align 16)
+// SSE: declare void @f37(<8 x float>* byval align 16)
 typedef float __m256 __attribute__ ((__vector_size__ (32)));
 typedef struct {
   __m256 m;
 } s256;
 
 s256 x38;
 __m256 x37;
 

 
 extern void func42(SA s);
 void func43(SA s) {
   func42(s);
 }
 
 // CHECK-LABEL: define i32 @f44
 // CHECK: ptrtoint
-// CHECK-NEXT: and {{.*}}, -32
+// SSE-NEXT: and {{.*}}, -16
+// AVXUP-NEXT: and {{.*}}, -32
 // CHECK-NEXT: inttoptr
 typedef int T44 __attribute((vector_size(32)));
 struct s44 { T44 x; int y; };
 int f44(int i, ...) {
   __builtin_va_list ap;
   __builtin_va_start(ap, i);
   struct s44 s = __builtin_va_arg(ap, struct s44);
   __builtin_va_end(ap);
   return s.y;
 }
 
 // Text that vec3 returns the correct LLVM IR type.
-// AVX-LABEL: define i32 @foo(<3 x i64> %X)
+// AVXUP-LABEL: define i32 @foo(<3 x i64> %X)
 typedef long long3 __attribute((ext_vector_type(3)));
 int foo(long3 X)
 {
   return 0;
 }
 
 // Make sure we don't use a varargs convention for a function without a
 // prototype where AVX types are involved.
-// AVX: @test45
-// AVX: call i32 bitcast (i32 (...)* @f45 to i32 (<8 x float>)*)
+// AVXUP: @test45
+// AVXUP: call i32 bitcast (i32 (...)* @f45 to i32 (<8 x float>)*)
 int f45();
 __m256 x45;
 void test45() { f45(x45); }
 
 // Make sure we use byval to pass 64-bit vectors in memory; the LLVM call
 // lowering can't handle this case correctly because it runs after legalization.
 // CHECK: @test46
 // CHECK: call void @f46({{.*}}<2 x float>* byval align 8 {{.*}}, <2 x float>* byval align 8 {{.*}})

 // CHECK-NEXT: store i32 {{.*}}, i32* {{.*}}
 // CHECK-NEXT: br label
 
 void test52_helper(int, ...);
 __m256 x52;
 void test52() {
   test52_helper(0, x52, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0i);
 }
-// AVX: @test52_helper(i32 0, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}})
+// AVXUP: @test52_helper(i32 0, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}})
 
 void test53(__m256 *m, __builtin_va_list argList) {
   *m = __builtin_va_arg(argList, __m256);
 }
-// AVX-LABEL: define void @test53
-// AVX-NOT: br i1
-// AVX: ret void
+// AVXUP-LABEL: define void @test53
+// AVXUP-NOT: br i1
+// AVXUP: ret void
 
 void test54_helper(__m256, ...);
 __m256 x54;
 void test54() {
   test54_helper(x54, x54, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0i);
   test54_helper(x54, x54, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0i);
 }
-// AVX: @test54_helper(<8 x float> {{%[a-zA-Z0-9]+}}, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}})
-// AVX: @test54_helper(<8 x float> {{%[a-zA-Z0-9]+}}, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, { double, double }* byval align 8 {{%[a-zA-Z0-9]+}})
+// AVXUP: @test54_helper(<8 x float> {{%[a-zA-Z0-9]+}}, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}})
+// AVXUP: @test54_helper(<8 x float> {{%[a-zA-Z0-9]+}}, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, { double, double }* byval align 8 {{%[a-zA-Z0-9]+}})
 
 typedef float __m512 __attribute__ ((__vector_size__ (64)));
 typedef struct {
   __m512 m;
 } s512;
 
 s512 x55;
 __m512 x56;
 
 // Even on AVX512, aggregates of size larger than four eightbytes have class
 // MEMORY (AVX512 draft 0.3 3.2.3p2 Rule 1).
 //
-// CHECK: declare void @f55(%struct.s512* byval align 64)
+// SSE: declare void @f55(%struct.s512* byval align 16)
+// AVX: declare void @f55(%struct.s512* byval align 32)
+// AVX512: declare void @f55(%struct.s512* byval align 64)
 void f55(s512 x);
 
 // However, __m512 has type SSE/SSEUP on AVX512.
 //
+// SSE: declare void @f56(<16 x float>* byval align 16)
+// AVX: declare void @f56(<16 x float>* byval align 32)
 // AVX512: declare void @f56(<16 x float>)
-// NO-AVX512: declare void @f56(<16 x float>* byval align 64)
 void f56(__m512 x);
 void f57() { f55(x55); f56(x56); }
 
 // Like for __m128 on AVX, check that the struct below is passed
 // in the same way regardless of AVX512 being used.
 //
-// CHECK: declare void @f58(%struct.t256* byval align 32)
+// SSE: declare void @f58(%struct.t256* byval align 16)
+// AVXUP: declare void @f58(%struct.t256* byval align 32)
 typedef struct t256 {
   __m256 m;
   __m256 n;
 } two256;
 
 extern void f58(two256 s);
 void f59(two256 s) {
   f58(s);
 }
 
-// CHECK: declare void @f60(%struct.sat256* byval align 32)
+// SSE: declare void @f60(%struct.sat256* byval align 16)
+// AVXUP: declare void @f60(%struct.sat256* byval align 32)
 typedef struct at256 {
   __m256 array[2];
 } Atwo256;
 typedef struct sat256 {
   Atwo256 x;
 } SAtwo256;
 
 extern void f60(SAtwo256 s);