[SimpleLoopUnswitch] Collect either logical ANDs/ORs but not both.

[fhahn]

Summary

After D97756, collectHomogenousInstGraphLoopInvariants may collect
conditions for both logical ANDs and logical ORs in case the root is a
select that matches both logical AND & OR.

This means the function won't return invariant values of either AND/OR
chains, but both. This can result in incorrect transformations.

See llvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-logical-and-or.ll.
Without the patch, Alive2 rejects the modified tests with:

Source and target don't have the same return domain.

Note that this also applies to the test case added in D97756
(@test_partial_condition_unswitch_or_select). We can't unswitch on
%cond6, because the graph leading to it contains and AND and an OR.

This only fixes trivial unswitching for now, but a similar problem
likely exists with non-trivial unswitching.

[nikic]

llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp

2773–2774

Looks like this code tries to handle this special case as well.

2785

Can we also determine ExitDirection here? I think the implementation of collectHomogenousInstGraphLoopInvariants() would be a good deal cleaner if we always passed in whether we expect or/and, rather than doing a guess in some of the cases.

[fhahn]

Update with alternative approach where helper functions are used to match either AND/OR but skipping (select _, true, false). This also removes a piece of code that may modify the function even if no unswitching happens (and we would claim no changes have been made)

llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp

2773–2774

Yeah, the code here already handles select _, true, false by skipping it and updating the branch condition before reaching collectHomogenousInstGraphLoopInvariants. But this is not ideal, as it can change the function even if we do not perform unswitching and claim we didn't change the function.

I will update the patch with an alternative approach, that replaces all instances where we use m_LogicalAnd/m_LogicalOr with helpers that skip select _, true, false.

2785

Unfortunately I don't think we can. I think here both target blocks may be in the loop and the unswitching direction is determined based on the match operation tree.

[aqjune]

There was a similar miscompilation report (which was introduced by my patch) and a bug fix due to the existence of select cond, true, false in the past: https://reviews.llvm.org/rG5bb38e84d3d0#986154 and https://reviews.llvm.org/rG6b4b1dc6ec6f0bf0a1bb414fbe751ccab99d41a0
Also a follow-up patch to enhance an assertion condition: https://reviews.llvm.org/rG431a40e1e28f181e87dd247b91a5e6872dd64ab4

This only fixes trivial unswitching for now, but a similar problem
likely exists with non-trivial unswitching.

If the select cond, true, false is a concern, what do you think about simplifying it to cond (https://alive2.llvm.org/ce/z/p5Ahrp) in advance before loop unswitch?

[fhahn]

In D124526#3483889, @aqjune wrote:

There was a similar miscompilation report (which was introduced by my patch) and a bug fix due to the existence of select cond, true, false in the past: https://reviews.llvm.org/rG5bb38e84d3d0#986154 and https://reviews.llvm.org/rG6b4b1dc6ec6f0bf0a1bb414fbe751ccab99d41a0
Also a follow-up patch to enhance an assertion condition: https://reviews.llvm.org/rG431a40e1e28f181e87dd247b91a5e6872dd64ab4

This only fixes trivial unswitching for now, but a similar problem
likely exists with non-trivial unswitching.

If the select cond, true, false is a concern, what do you think about simplifying it to cond (https://alive2.llvm.org/ce/z/p5Ahrp) in advance before loop unswitch?

Is it possible you did not check the latest version of the patch? It uses helpers to skip select cons, true, false when trying to match logical and/or.

I don't think we really should simplify/modify the IR if we are not unswitching, which is what 6b4b1dc6ec6f0bf0a1bb414fbe751ccab99d41a0 did, but SimpleLoopUnswitch claims no changes have been made.

[nikic]

llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp

124

Might make more sense to do the stripping as a separate step Cond = stripTrivialSelect(Cond), just without the bit that actually updates the condition in the branch instruction?

[aqjune]

In D124526#3483907, @fhahn wrote:

In D124526#3483889, @aqjune wrote:

There was a similar miscompilation report (which was introduced by my patch) and a bug fix due to the existence of select cond, true, false in the past: https://reviews.llvm.org/rG5bb38e84d3d0#986154 and https://reviews.llvm.org/rG6b4b1dc6ec6f0bf0a1bb414fbe751ccab99d41a0
Also a follow-up patch to enhance an assertion condition: https://reviews.llvm.org/rG431a40e1e28f181e87dd247b91a5e6872dd64ab4

This only fixes trivial unswitching for now, but a similar problem
likely exists with non-trivial unswitching.

If the select cond, true, false is a concern, what do you think about simplifying it to cond (https://alive2.llvm.org/ce/z/p5Ahrp) in advance before loop unswitch?

Is it possible you did not check the latest version of the patch? It uses helpers to skip select cons, true, false when trying to match logical and/or.

I don't think we really should simplify/modify the IR if we are not unswitching, which is what 6b4b1dc6ec6f0bf0a1bb414fbe751ccab99d41a0 did, but SimpleLoopUnswitch claims no changes have been made.

Oh, I totally forgot the conclusion that were discussed in the threads; I recalled that the select form was problematic in the past, but not discussions afterwards.
Even the branch condition-changing code (line 2754~) was still there. Thank you for cleaning up the code bit.

[fhahn]

Update to use skipTrivialSelect helper instead of separate helpers to skip select and check for and/or.

[fhahn]

llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp

124

I updated the patch to just use such a helper. Roughly the same places need updating and I think it's fine to go either way. Unfortunately I don't think there's a good way to prevent making the same mistake when adding new code :(

[nikic]

LGTM

[dmgreen]

Hello I think that since this patch there has been a failure on the PowerPC big endian bootstrap build. I had originally thought it was D123801 because it had the words "powerpc" and "bigendian" in it.

After being able to reproduce it, I think it's from this one though. This example through -simple-loop-unswitch fails now: https://godbolt.org/z/fjWd443P3
It's quite heavily reduced. If it does not reproduce, the original came from running:

bin/clang++ -DGTEST_HAS_RTTI=0 -D_DEBUG -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Ilib/Target/WebAssembly -I../llvm/lib/Target/WebAssembly -Iinclude -I../llvm/include -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wno-comment -Wstring-conversion -Wmisleading-indentation -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -fvisibility=hidden -fno-exceptions -fno-rtti -UNDEBUG -std=c++14 -c ../llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp --target=powerpc64-linux-gnu -I/usr/powerpc-linux-gnu/include/c++/7/powerpc-linux-gnu/64

[fhahn]

In D124526#3497540, @dmgreen wrote:

Hello I think that since this patch there has been a failure on the PowerPC big endian bootstrap build. I had originally thought it was D123801 because it had the words "powerpc" and "bigendian" in it.

After being able to reproduce it, I think it's from this one though. This example through -simple-loop-unswitch fails now: https://godbolt.org/z/fjWd443P3
It's quite heavily reduced. If it does not reproduce, the original came from running:

bin/clang++ -DGTEST_HAS_RTTI=0 -D_DEBUG -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Ilib/Target/WebAssembly -I../llvm/lib/Target/WebAssembly -Iinclude -I../llvm/include -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wno-comment -Wstring-conversion -Wmisleading-indentation -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -fvisibility=hidden -fno-exceptions -fno-rtti -UNDEBUG -std=c++14 -c ../llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp --target=powerpc64-linux-gnu -I/usr/powerpc-linux-gnu/include/c++/7/powerpc-linux-gnu/64

I've reverted the change for now, thanks!

[uabelho]

Hi,

I wrote
https://github.com/llvm/llvm-project/issues/55526
about a crash happening after this was recommited again in 41e142fdc7

llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp

MSSAThreshold("simple-loop-unswitch-memoryssa-threshold",
                   cl::desc("Max number of memory uses to explore during "
                            "partial unswitching analysis"),
                   cl::init(100), cl::Hidden);
 static cl::opt<bool> FreezeLoopUnswitchCond(
     "freeze-loop-unswitch-cond", cl::init(true), cl::Hidden,
     cl::desc("If enabled, the freeze instruction will be added to condition "
              "of loop unswitch to prevent miscompilation."));
 
+// Helper to check if \p Cond is only a logical AND operation. It skips (select
+// x, true, false), which could be both a logical AND and OR.
+static bool isOnlyLogicalAnd(Value *Cond) {
+  Value *CondNext;
+  while (match(Cond, m_Select(m_Value(CondNext), m_One(), m_Zero())))
+    Cond = CondNext;
+
+  return match(Cond, m_LogicalAnd());
+}
+
+// Helper to check if \p Cond is only a logical OR operation. It skips (select
+// x, true, false), which could be both a logical AND and OR.
+static bool isOnlyLogicalOr(Value *Cond) {
+  Value *CondNext;
+  while (match(Cond, m_Select(m_Value(CondNext), m_One(), m_Zero())))
+    Cond = CondNext;
+
+  return match(Cond, m_LogicalOr());
+}
+
 /// Collect all of the loop invariant input values transitively used by the
 /// homogeneous instruction graph from a given root.
 ///
 /// This essentially walks from a root recursively through loop variant operands
-/// which have the exact same opcode and finds all inputs which are loop
-/// invariant. For some operations these can be re-associated and unswitched out
-/// of the loop entirely.
+/// which have perform the same logical operation (AND or OR) and finds all
+/// inputs which are loop invariant. For some operations these can be
+/// re-associated and unswitched out of the loop entirely.
 static TinyPtrVector<Value *>
 collectHomogenousInstGraphLoopInvariants(Loop &L, Instruction &Root,
                                          LoopInfo &LI) {
   assert(!L.isLoopInvariant(&Root) &&
          "Only need to walk the graph if root itself is not invariant.");
   TinyPtrVector<Value *> Invariants;
 
-  bool IsRootAnd = match(&Root, m_LogicalAnd());
-  bool IsRootOr  = match(&Root, m_LogicalOr());
+  bool IsRootAnd = isOnlyLogicalAnd(&Root);
+  bool IsRootOr = isOnlyLogicalOr(&Root);
 
   // Build a worklist and recurse through operators collecting invariants.
   SmallVector<Instruction *, 4> Worklist;
   SmallPtrSet<Instruction *, 8> Visited;
   Worklist.push_back(&Root);
   Visited.insert(&Root);
   do {
     Instruction &I = *Worklist.pop_back_val();
     for (Value *OpV : I.operand_values()) {
       // Skip constants as unswitching isn't interesting for them.
       if (isa<Constant>(OpV))
         continue;
 
       // Add it to our result if loop invariant.
       if (L.isLoopInvariant(OpV)) {
         Invariants.push_back(OpV);
         continue;
       }
 
       // If not an instruction with the same opcode, nothing we can do.
       Instruction *OpI = dyn_cast<Instruction>(OpV);
 
-      if (OpI && ((IsRootAnd && match(OpI, m_LogicalAnd())) ||
-                  (IsRootOr  && match(OpI, m_LogicalOr())))) {
+      if (OpI && ((IsRootAnd && isOnlyLogicalAnd(OpI)) ||
+                  (IsRootOr && isOnlyLogicalOr(OpI)))) {
         // Visit this operand.
         if (Visited.insert(OpI).second)
           Worklist.push_back(OpI);
       }
     }
   } while (!Worklist.empty());
 
   return Invariants;
static bool unswitchTrivialBranch(Loop &L, BranchInst &BI, DominatorTree &DT,
   }
 
   // When unswitching only part of the branch's condition, we need the exit
   // block to be reached directly from the partially unswitched input. This can
   // be done when the exit block is along the true edge and the branch condition
   // is a graph of `or` operations, or the exit block is along the false edge
   // and the condition is a graph of `and` operations.
   if (!FullUnswitch) {
-    if (ExitDirection ? !match(BI.getCondition(), m_LogicalOr())
-                      : !match(BI.getCondition(), m_LogicalAnd())) {
+    if (ExitDirection ? !isOnlyLogicalOr(BI.getCondition())
+                      : !isOnlyLogicalAnd(BI.getCondition())) {
       LLVM_DEBUG(dbgs() << "   Branch condition is in improper form for "
                            "non-full unswitch!\n");
       return false;
     }
   }
 
   LLVM_DEBUG({
     dbgs() << "    unswitching trivial invariant conditions for: " << BI
if (MSSAU) {
       BranchInst::Create(ContinueBB, ParentBB);
     }
     BI.setSuccessor(LoopExitSuccIdx, UnswitchedBB);
     BI.setSuccessor(1 - LoopExitSuccIdx, NewPH);
   } else {
     // Only unswitching a subset of inputs to the condition, so we will need to
     // build a new branch that merges the invariant inputs.
     if (ExitDirection)
-      assert(match(BI.getCondition(), m_LogicalOr()) &&
+      assert(isOnlyLogicalOr(BI.getCondition()) &&
              "Must have an `or` of `i1`s or `select i1 X, true, Y`s for the "
              "condition!");
     else
-      assert(match(BI.getCondition(), m_LogicalAnd()) &&
+      assert(isOnlyLogicalAnd(BI.getCondition()) &&
              "Must have an `and` of `i1`s or `select i1 X, Y, false`s for the"
              " condition!");
     buildPartialUnswitchConditionalBranch(*OldPH, Invariants, ExitDirection,
                                           *UnswitchedBB, *NewPH, false);
   }
 
   // Update the dominator tree with the added edge.
   DT.insertEdge(OldPH, UnswitchedBB);
static void unswitchNontrivialInvariants(
   // invariants combined with `and` or `or` or partially invariant instructions,
   // the combining operation determines the best direction to unswitch: we want
   // to unswitch the direction that will collapse the branch.
   bool Direction = true;
   int ClonedSucc = 0;
   if (!FullUnswitch) {
     Value *Cond = BI->getCondition();
     (void)Cond;
-    assert(((match(Cond, m_LogicalAnd()) ^ match(Cond, m_LogicalOr())) ||
+    assert(((isOnlyLogicalAnd(Cond) ^ isOnlyLogicalOr(Cond)) ||
             PartiallyInvariant) &&
            "Only `or`, `and`, an `select`, partially invariant instructions "
            "can combine invariants being unswitched.");
-    if (!match(BI->getCondition(), m_LogicalOr())) {
-      if (match(BI->getCondition(), m_LogicalAnd()) ||
+    if (!isOnlyLogicalOr(BI->getCondition())) {
+      if (isOnlyLogicalAnd(BI->getCondition()) ||
           (PartiallyInvariant && !PartialIVInfo.KnownValue->isOneValue())) {
         Direction = false;
         ClonedSucc = 1;
       }
     }
   }
 
   BasicBlock *RetainedSuccBB =
if (auto *SI = dyn_cast<SwitchInst>(BB->getTerminator())) {
         UnswitchCandidates.push_back({SI, {SI->getCondition()}});
       continue;
     }
 
     auto *BI = dyn_cast<BranchInst>(BB->getTerminator());
     if (!BI || !BI->isConditional() || isa<Constant>(BI->getCondition()) ||
         BI->getSuccessor(0) == BI->getSuccessor(1))
       continue;
 
-    // If BI's condition is 'select _, true, false', simplify it to confuse
-    // matchers
-    Value *Cond = BI->getCondition(), *CondNext;
-    while (match(Cond, m_Select(m_Value(CondNext), m_One(), m_Zero())))
-      Cond = CondNext;
-    BI->setCondition(Cond);
-
-    if (isa<Constant>(Cond))
+    if (isa<Constant>(BI->getCondition()))
       continue;
 
     if (L.isLoopInvariant(BI->getCondition())) {
       UnswitchCandidates.push_back({BI, {BI->getCondition()}});
       continue;
     }
 
     Instruction &CondI = *cast<Instruction>(BI->getCondition());
-    if (match(&CondI, m_CombineOr(m_LogicalAnd(), m_LogicalOr()))) {
+    if (isOnlyLogicalAnd(&CondI) || isOnlyLogicalOr(&CondI)) {
       TinyPtrVector<Value *> Invariants =
           collectHomogenousInstGraphLoopInvariants(L, CondI, LI);
       if (Invariants.empty())
         continue;
 
       UnswitchCandidates.push_back({BI, std::move(Invariants)});
       continue;
     }
   }
 
for (BasicBlock *SuccBB : successors(&BB)) {
 
       // If this is a partial unswitch candidate, then it must be a conditional
       // branch with a condition of either `or`, `and`, their corresponding
       // select forms or partially invariant instructions. In that case, one of
       // the successors is necessarily duplicated, so don't even try to remove
       // its cost.
       if (!FullUnswitch) {
         auto &BI = cast<BranchInst>(TI);
-        if (match(BI.getCondition(), m_LogicalAnd())) {
+        if (isOnlyLogicalAnd(BI.getCondition())) {
           if (SuccBB == BI.getSuccessor(1))
             continue;
-        } else if (match(BI.getCondition(), m_LogicalOr())) {
+        } else if (isOnlyLogicalOr(BI.getCondition())) {
           if (SuccBB == BI.getSuccessor(0))
             continue;
         } else if ((PartialIVInfo.KnownValue->isOneValue() &&
                     SuccBB == BI.getSuccessor(0)) ||
                    (!PartialIVInfo.KnownValue->isOneValue() &&
                     SuccBB == BI.getSuccessor(1)))
           continue;
       }

llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-freeze.ll

 ; CHECK-NEXT:    br label [[EXIT_SPLIT_US:%.*]]
 ; CHECK:       exit.split.us:
 ; CHECK-NEXT:    br label [[EXIT:%.*]]
 ; CHECK:       entry.split:
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @a()
 ; CHECK-NEXT:    [[SEL:%.*]] = select i1 true, i1 true, i1 false
-; CHECK-NEXT:    br i1 true, label [[LOOP]], label [[EXIT_SPLIT:%.*]]
+; CHECK-NEXT:    br i1 [[SEL]], label [[LOOP]], label [[EXIT_SPLIT:%.*]]
 ; CHECK:       exit.split:
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   br label %loop
 
 loop:
   call i32 @a()
   %sel = select i1 %c.1, i1 %c.2, i1 false
   br i1 %sel, label %loop, label %exit
 
 exit:
   ret i32 0
 }

llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-invariant-select-bug.ll

 
 ; We shouldn't unswitch this loop.
 define void @foo() {
 ; CHECK-LABEL: @foo(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[HEADER:%.*]]
 ; CHECK:       header:
 ; CHECK-NEXT:    [[VAL:%.*]] = select i1 true, i1 true, i1 false
-; CHECK-NEXT:    br i1 true, label [[EXIT:%.*]], label [[HEADER]]
+; CHECK-NEXT:    br i1 [[VAL]], label [[EXIT:%.*]], label [[HEADER]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   br label %header
 
 header:
   %val = select i1 true, i1 true, i1 false
   br i1 %val, label %exit, label %header
 
 exit:
   ret void
 }

llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch.ll

 ; CHECK:       entry.split:
 ; CHECK-NEXT:    br label %loop_begin
 ;
 ; CHECK:       loop_begin:
 ; CHECK-NEXT:    %[[V1:.*]] = load i1, i1* %ptr1
 ; CHECK-NEXT:    %[[V2:.*]] = load i1, i1* %ptr2
 ; CHECK-NEXT:    %[[AND1:.*]] = select i1 %[[V1]], i1 true, i1 false
 ; CHECK-NEXT:    %[[AND2:.*]] = select i1 %[[AND1]], i1 true, i1 false
-; CHECK-NEXT:    br i1 %[[V1]], label %loop_a, label %loop_b
+; CHECK-NEXT:    br i1 %[[AND2]], label %loop_a, label %loop_b
 
 loop_a:
   call i32 @a()
   br label %latch
 ; CHECK:       loop_a:
 ; CHECK-NEXT:    call i32 @a()
 ; CHECK-NEXT:    br label %latch
 

 ; CHECK:       entry.split:
 ; CHECK-NEXT:    br label %loop_begin
 ;
 ; CHECK:       loop_begin:
 ; CHECK-NEXT:    %[[V1:.*]] = load i1, i1* %ptr1
 ; CHECK-NEXT:    %[[V2:.*]] = load i1, i1* %ptr2
 ; CHECK-NEXT:    %[[AND1:.*]] = select i1 %[[V1]], i1 true, i1 false
 ; CHECK-NEXT:    %[[AND2:.*]] = select i1 %[[AND1]], i1 true, i1 false
-; CHECK-NEXT:    br i1 %[[V1]], label %loop_b, label %loop_a
+; CHECK-NEXT:    br i1 %[[AND2]], label %loop_b, label %loop_a
 
 loop_a:
   call i32 @a()
   br label %latch
 ; CHECK:       loop_a:
 ; CHECK-NEXT:    call i32 @a()
 ; CHECK-NEXT:    br label %latch
 

llvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-freeze-individual-conditions.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -passes='loop(simple-loop-unswitch)' -S %s | FileCheck %s
 
 declare void @some_func()
 
 define i32 @need_freeze_of_individual_or_conditions1(i1 %cond1, i1 %cond2, i1 %cond3, i1 %cond4) {
 ; CHECK-LABEL: @need_freeze_of_individual_or_conditions1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = and i1 [[COND4:%.*]], [[COND1:%.*]]
 ; CHECK-NEXT:    br i1 [[TMP0]], label [[ENTRY_SPLIT:%.*]], label [[EXIT_SPLIT:%.*]]
 ; CHECK:       entry.split:
-; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[COND2:%.*]], [[COND3:%.*]]
-; CHECK-NEXT:    br i1 [[TMP1]], label [[ENTRY_SPLIT_SPLIT:%.*]], label [[EXIT_SPLIT1:%.*]]
-; CHECK:       entry.split.split:
 ; CHECK-NEXT:    br label [[LOOP_HEADER:%.*]]
 ; CHECK:       loop.header:
-; CHECK-NEXT:    [[OR:%.*]] = or i1 true, true
+; CHECK-NEXT:    [[OR:%.*]] = or i1 [[COND2:%.*]], [[COND3:%.*]]
 ; CHECK-NEXT:    [[AND1:%.*]] = and i1 [[OR]], true
 ; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[AND1]], i1 true, i1 false
 ; CHECK-NEXT:    br i1 [[AND2]], label [[LOOP_LATCH:%.*]], label [[EXIT:%.*]]
 ; CHECK:       loop.latch:
 ; CHECK-NEXT:    call void @some_func()
 ; CHECK-NEXT:    br label [[LOOP_HEADER]]
 ; CHECK:       exit:
-; CHECK-NEXT:    br label [[EXIT_SPLIT1]]
-; CHECK:       exit.split1:
 ; CHECK-NEXT:    br label [[EXIT_SPLIT]]
 ; CHECK:       exit.split:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   br label %loop.header
 
 loop.header:

 }
 
 define i32 @need_freeze_of_individual_or_conditions2(i1 noundef %cond1, i1 %cond2, i1 %cond3, i1 %cond4) {
 ; CHECK-LABEL: @need_freeze_of_individual_or_conditions2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = and i1 [[COND4:%.*]], [[COND1:%.*]]
 ; CHECK-NEXT:    br i1 [[TMP0]], label [[ENTRY_SPLIT:%.*]], label [[EXIT_SPLIT:%.*]]
 ; CHECK:       entry.split:
-; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[COND2:%.*]], [[COND3:%.*]]
-; CHECK-NEXT:    br i1 [[TMP1]], label [[ENTRY_SPLIT_SPLIT:%.*]], label [[EXIT_SPLIT1:%.*]]
-; CHECK:       entry.split.split:
 ; CHECK-NEXT:    br label [[LOOP_HEADER:%.*]]
 ; CHECK:       loop.header:
-; CHECK-NEXT:    [[OR:%.*]] = or i1 true, true
+; CHECK-NEXT:    [[OR:%.*]] = or i1 [[COND2:%.*]], [[COND3:%.*]]
 ; CHECK-NEXT:    [[AND1:%.*]] = and i1 [[OR]], true
 ; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[AND1]], i1 true, i1 false
 ; CHECK-NEXT:    br i1 [[AND2]], label [[LOOP_LATCH:%.*]], label [[EXIT:%.*]]
 ; CHECK:       loop.latch:
 ; CHECK-NEXT:    call void @some_func()
 ; CHECK-NEXT:    br label [[LOOP_HEADER]]
 ; CHECK:       exit:
-; CHECK-NEXT:    br label [[EXIT_SPLIT1]]
-; CHECK:       exit.split1:
 ; CHECK-NEXT:    br label [[EXIT_SPLIT]]
 ; CHECK:       exit.split:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   br label %loop.header
 
 loop.header:

 }
 
 define i32 @need_freeze_of_individual_or_conditions3(i1 %cond1, i1 %cond2, i1 %cond3, i1 noundef %cond4) {
 ; CHECK-LABEL: @need_freeze_of_individual_or_conditions3(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = and i1 [[COND4:%.*]], [[COND1:%.*]]
 ; CHECK-NEXT:    br i1 [[TMP0]], label [[ENTRY_SPLIT:%.*]], label [[EXIT_SPLIT:%.*]]
 ; CHECK:       entry.split:
-; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[COND2:%.*]], [[COND3:%.*]]
-; CHECK-NEXT:    br i1 [[TMP1]], label [[ENTRY_SPLIT_SPLIT:%.*]], label [[EXIT_SPLIT1:%.*]]
-; CHECK:       entry.split.split:
 ; CHECK-NEXT:    br label [[LOOP_HEADER:%.*]]
 ; CHECK:       loop.header:
-; CHECK-NEXT:    [[OR:%.*]] = or i1 true, true
+; CHECK-NEXT:    [[OR:%.*]] = or i1 [[COND2:%.*]], [[COND3:%.*]]
 ; CHECK-NEXT:    [[AND1:%.*]] = and i1 [[OR]], true
 ; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[AND1]], i1 true, i1 false
 ; CHECK-NEXT:    br i1 [[AND2]], label [[LOOP_LATCH:%.*]], label [[EXIT:%.*]]
 ; CHECK:       loop.latch:
 ; CHECK-NEXT:    call void @some_func()
 ; CHECK-NEXT:    br label [[LOOP_HEADER]]
 ; CHECK:       exit:
-; CHECK-NEXT:    br label [[EXIT_SPLIT1]]
-; CHECK:       exit.split1:
 ; CHECK-NEXT:    br label [[EXIT_SPLIT]]
 ; CHECK:       exit.split:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   br label %loop.header
 
 loop.header:

llvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-logical-and-or.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -passes='loop-mssa(simple-loop-unswitch)' -S %s | FileCheck %s
 
 ; Test cases for trivial unswitching with selects that matches both a logical and & or.
 
 declare void @some_func()
 
 define void @test_select_logical_and_or_with_and_1(i1 noundef %cond1, i1 noundef %cond2) {
 ; CHECK-LABEL: @test_select_logical_and_or_with_and_1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = or i1 [[COND2:%.*]], [[COND1:%.*]]
-; CHECK-NEXT:    br i1 [[TMP0]], label [[EXIT_SPLIT:%.*]], label [[ENTRY_SPLIT:%.*]]
-; CHECK:       entry.split:
 ; CHECK-NEXT:    br label [[LOOP_HEADER:%.*]]
 ; CHECK:       loop.header:
-; CHECK-NEXT:    [[COND_AND1:%.*]] = and i1 false, false
+; CHECK-NEXT:    [[COND_AND1:%.*]] = and i1 [[COND2:%.*]], [[COND1:%.*]]
 ; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[COND_AND1]], i1 true, i1 false
 ; CHECK-NEXT:    br i1 [[SEL]], label [[EXIT:%.*]], label [[LOOP_LATCH:%.*]]
 ; CHECK:       loop.latch:
 ; CHECK-NEXT:    call void @some_func()
 ; CHECK-NEXT:    br label [[LOOP_HEADER]]
 ; CHECK:       exit:
-; CHECK-NEXT:    br label [[EXIT_SPLIT]]
-; CHECK:       exit.split:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   br label %loop.header
 
 loop.header:
   %cond_and1 = and i1 %cond2, %cond1
   %sel = select i1 %cond_and1, i1 true, i1 false

 exit:
   ret void
 }
 
 
 define void @test_select_logical_and_or_with_or_2(i1 noundef %cond1, i1 noundef %cond2) {
 ; CHECK-LABEL: @test_select_logical_and_or_with_or_2(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = and i1 [[COND2:%.*]], [[COND1:%.*]]
-; CHECK-NEXT:    br i1 [[TMP0]], label [[ENTRY_SPLIT:%.*]], label [[EXIT_SPLIT:%.*]]
-; CHECK:       entry.split:
 ; CHECK-NEXT:    br label [[LOOP_HEADER:%.*]]
 ; CHECK:       loop.header:
-; CHECK-NEXT:    [[COND_AND1:%.*]] = or i1 true, true
+; CHECK-NEXT:    [[COND_AND1:%.*]] = or i1 [[COND2:%.*]], [[COND1:%.*]]
 ; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[COND_AND1]], i1 true, i1 false
 ; CHECK-NEXT:    br i1 [[SEL]], label [[LOOP_LATCH:%.*]], label [[EXIT:%.*]]
 ; CHECK:       loop.latch:
 ; CHECK-NEXT:    call void @some_func()
 ; CHECK-NEXT:    br label [[LOOP_HEADER]]
 ; CHECK:       exit:
-; CHECK-NEXT:    br label [[EXIT_SPLIT]]
-; CHECK:       exit.split:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   br label %loop.header
 
 loop.header:
   %cond_and1 = or i1 %cond2, %cond1
   %sel = select i1 %cond_and1, i1 true, i1 false
   br i1 %sel, label %loop.latch, label %exit
 
 loop.latch:
   call void @some_func()
   br label %loop.header
 
 exit:
   ret void
 }
 
 ; Check that loop unswitch looks through a combination of or and select instructions.
-; Note that cond6 can be unswitched because `select i1 %cond_or5, i1 true, i1 false` is
-; both logical-or and logical-and.
 define i32 @test_partial_condition_unswitch_or_select(i32* %var, i1 %cond1, i1 %cond2, i1 %cond3, i1 %cond4, i1 %cond5, i1 %cond6) {
 ; CHECK-LABEL: @test_partial_condition_unswitch_or_select(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = or i1 [[COND4:%.*]], [[COND2:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i1 [[TMP0]], [[COND3:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = or i1 [[TMP1]], [[COND1:%.*]]
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[LOOP_EXIT_SPLIT:%.*]], label [[ENTRY_SPLIT:%.*]]
 ; CHECK:       entry.split:
-; CHECK-NEXT:    br i1 [[COND6:%.*]], label [[LOOP_EXIT_SPLIT1:%.*]], label [[ENTRY_SPLIT_SPLIT:%.*]]
-; CHECK:       entry.split.split:
 ; CHECK-NEXT:    br label [[LOOP_BEGIN:%.*]]
 ; CHECK:       loop_begin:
 ; CHECK-NEXT:    [[VAR_VAL:%.*]] = load i32, i32* [[VAR:%.*]], align 4
 ; CHECK-NEXT:    [[VAR_COND:%.*]] = trunc i32 [[VAR_VAL]] to i1
 ; CHECK-NEXT:    [[COND_OR1:%.*]] = or i1 [[VAR_COND]], false
 ; CHECK-NEXT:    [[COND_OR2:%.*]] = or i1 false, false
 ; CHECK-NEXT:    [[COND_OR3:%.*]] = or i1 [[COND_OR1]], [[COND_OR2]]
 ; CHECK-NEXT:    [[COND_XOR1:%.*]] = xor i1 [[COND5:%.*]], [[VAR_COND]]
-; CHECK-NEXT:    [[COND_AND1:%.*]] = and i1 false, [[VAR_COND]]
+; CHECK-NEXT:    [[COND_AND1:%.*]] = and i1 [[COND6:%.*]], [[VAR_COND]]
 ; CHECK-NEXT:    [[COND_OR4:%.*]] = or i1 [[COND_XOR1]], [[COND_AND1]]
 ; CHECK-NEXT:    [[COND_OR5:%.*]] = select i1 [[COND_OR3]], i1 true, i1 [[COND_OR4]]
 ; CHECK-NEXT:    [[COND_OR6:%.*]] = select i1 [[COND_OR5]], i1 true, i1 false
 ; CHECK-NEXT:    br i1 [[COND_OR6]], label [[LOOP_EXIT:%.*]], label [[DO_SOMETHING:%.*]]
 ; CHECK:       do_something:
 ; CHECK-NEXT:    call void @some_func() #[[ATTR0:[0-9]+]]
 ; CHECK-NEXT:    br label [[LOOP_BEGIN]]
 ; CHECK:       loop_exit:
-; CHECK-NEXT:    br label [[LOOP_EXIT_SPLIT1]]
-; CHECK:       loop_exit.split1:
 ; CHECK-NEXT:    br label [[LOOP_EXIT_SPLIT]]
 ; CHECK:       loop_exit.split:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   br label %loop_begin
 
 loop_begin:

 do_something:
   call void @some_func() noreturn nounwind
   br label %loop_begin
 
 loop_exit:
   ret i32 0
 }
 
+; Same as test_partial_condition_unswitch_or_select, but with arguments marked
+; as noundef.
 define i32 @test_partial_condition_unswitch_or_select_noundef(i32* noundef %var, i1 noundef %cond1, i1 noundef %cond2, i1 noundef %cond3, i1 noundef %cond4, i1 noundef %cond5, i1 noundef %cond6) {
 ; CHECK-LABEL: @test_partial_condition_unswitch_or_select_noundef(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = or i1 [[COND4:%.*]], [[COND2:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i1 [[TMP0]], [[COND3:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = or i1 [[TMP1]], [[COND1:%.*]]
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[LOOP_EXIT_SPLIT:%.*]], label [[ENTRY_SPLIT:%.*]]
 ; CHECK:       entry.split:
-; CHECK-NEXT:    br i1 [[COND6:%.*]], label [[LOOP_EXIT_SPLIT1:%.*]], label [[ENTRY_SPLIT_SPLIT:%.*]]
-; CHECK:       entry.split.split:
 ; CHECK-NEXT:    br label [[LOOP_BEGIN:%.*]]
 ; CHECK:       loop_begin:
 ; CHECK-NEXT:    [[VAR_VAL:%.*]] = load i32, i32* [[VAR:%.*]], align 4
 ; CHECK-NEXT:    [[VAR_COND:%.*]] = trunc i32 [[VAR_VAL]] to i1
 ; CHECK-NEXT:    [[COND_OR1:%.*]] = or i1 [[VAR_COND]], false
 ; CHECK-NEXT:    [[COND_OR2:%.*]] = or i1 false, false
 ; CHECK-NEXT:    [[COND_OR3:%.*]] = or i1 [[COND_OR1]], [[COND_OR2]]
 ; CHECK-NEXT:    [[COND_XOR1:%.*]] = xor i1 [[COND5:%.*]], [[VAR_COND]]
-; CHECK-NEXT:    [[COND_AND1:%.*]] = and i1 false, [[VAR_COND]]
+; CHECK-NEXT:    [[COND_AND1:%.*]] = and i1 [[COND6:%.*]], [[VAR_COND]]
 ; CHECK-NEXT:    [[COND_OR4:%.*]] = or i1 [[COND_XOR1]], [[COND_AND1]]
 ; CHECK-NEXT:    [[COND_OR5:%.*]] = select i1 [[COND_OR3]], i1 true, i1 [[COND_OR4]]
 ; CHECK-NEXT:    [[COND_OR6:%.*]] = select i1 [[COND_OR5]], i1 true, i1 false
 ; CHECK-NEXT:    br i1 [[COND_OR6]], label [[LOOP_EXIT:%.*]], label [[DO_SOMETHING:%.*]]
 ; CHECK:       do_something:
 ; CHECK-NEXT:    call void @some_func() #[[ATTR0]]
 ; CHECK-NEXT:    br label [[LOOP_BEGIN]]
 ; CHECK:       loop_exit:
-; CHECK-NEXT:    br label [[LOOP_EXIT_SPLIT1]]
-; CHECK:       loop_exit.split1:
 ; CHECK-NEXT:    br label [[LOOP_EXIT_SPLIT]]
 ; CHECK:       loop_exit.split:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   br label %loop_begin
 
 loop_begin: