llvm-reduce: Add reduction pass to remove regalloc hints

[arsenm]

Summary

I'm a bit confused by what's actually stored for the allocation
hints. The MIR parser only handles the "simple" case where there's a
single hint. I don't really understand the assertion in
clearSimpleHint, or under what circumstances there are multiple hint
registers.

[markus]

As a general thought, I wonder if it would be wise to keep the MIR specific reducer passes separate from the IR ones. Either by directory or file naming conventions.

llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.h

11

Comment needs to be updated.

[arsenm]

Fix comment. Also not sure why every file likes to repeat this style of comment in the source and header

[arsenm]

In D124097#3463845, @markus wrote:

As a general thought, I wonder if it would be wise to keep the MIR specific reducer passes separate from the IR ones. Either by directory or file naming conventions.

I've thought about that and will probably move them into a subdirectory at some point

[MatzeB]

I'm a bit confused by what's actually stored for the allocation hints. The MIR parser only handles the "simple" case where there's a single hint. I don't really understand the assertion in clearSimpleHint, or under what circumstances there are multiple hint registers.

I'm not super familiar with the regalloc hints off-hand. But it seems ARM is the only target using target-specific regalloc hints. You can search for ARMRI::RegPairEven, ARMRI::RegPairOdd, ARMRI::RegLR there. Anyway assuming they are indeed just "hints" then it should be fine to drop them...

It seems to me that clearing a hint may work with setRegAllocationHint(vreg, 0, Register()). Though maybe it would be best to create a new clearRegAllocationHint(...) API for this to make it more explicit, what do you think?

LGTM (use setRegAllocationHint or add a new clearRegAllocationHint API at your discretion).

[arsenm]

In D124097#3476355, @MatzeB wrote:

I'm a bit confused by what's actually stored for the allocation hints. The MIR parser only handles the "simple" case where there's a single hint. I don't really understand the assertion in clearSimpleHint, or under what circumstances there are multiple hint registers.

I'm not super familiar with the regalloc hints off-hand. But it seems ARM is the only target using target-specific regalloc hints. You can search for ARMRI::RegPairEven, ARMRI::RegPairOdd, ARMRI::RegLR there. Anyway assuming they are indeed just "hints" then it should be fine to drop them...

It seems to me that clearing a hint may work with setRegAllocationHint(vreg, 0, Register()). Though maybe it would be best to create a new clearRegAllocationHint(...) API for this to make it more explicit, what do you think?

LGTM (use setRegAllocationHint or add a new clearRegAllocationHint API at your discretion).

clearSimpleHint already exists (and is used here) and as far as I can tell clears all hints, so I don't understand the naming

[MatzeB]

clearSimpleHint already exists (and is used here) and as far as I can tell clears all hints, so I don't understand the naming

Renaming that function to clearHint() and dropping the assert sounds good to me.

[arsenm]

a0dcbe45bd8387da51f94e4d171c3ecc3d266e64

llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir

 # REQUIRES: amdgpu-registered-target
-# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --delta-passes=instructions --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
 # RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
 
 # CHECK-INTERESTINGNESS: S_NOP 0
 
 # Make sure that register hints are preserved in the cloned function.
 
 # RESULT: registers:
 # RESULT-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }

llvm/test/tools/llvm-reduce/mir/reduce-register-hints.mir

+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -simplify-mir --delta-passes=register-hints -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS: - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
+# CHECK-INTERESTINGNESS: - { id: 2, class: vgpr_32, preferred-register: '%1' }
+# CHECK-INTERESTINGNESS-COUNT-5: V_MOV_B32
+
+# RESULT: registers:
+# RESULT-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
+# RESULT-NEXT: - { id: 1, class: vgpr_32 }
+# RESULT-NEXT: - { id: 2, class: vgpr_32, preferred-register: '%1' }
+# RESULT-NEXT: - { id: 3, class: vgpr_32 }
+# RESULT-NEXT: - { id: 4, class: vgpr_32 }
+
+---
+name: func
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
+  - { id: 1, class: vgpr_32, preferred-register: '' }
+  - { id: 2, class: vgpr_32, preferred-register: '%1' }
+  - { id: 3, class: vgpr_32, preferred-register: '%4' }
+  - { id: 4, class: vgpr_32, preferred-register: '%3' }
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    S_WAITCNT 0
+    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %1:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
+    S_NOP 0
+    S_ENDPGM 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4
+...
+

llvm/tools/llvm-reduce/CMakeLists.txt

add_llvm_tool(llvm-reduce
   deltas/ReduceOperandBundles.cpp
   deltas/ReduceSpecialGlobals.cpp
   deltas/ReduceOperands.cpp
   deltas/ReduceOperandsSkip.cpp
   deltas/ReduceOperandsToArgs.cpp
   deltas/ReduceInstructionsMIR.cpp
   deltas/ReduceInstructionFlagsMIR.cpp
   deltas/ReduceIRReferences.cpp
+  deltas/ReduceVirtualRegisters.cpp
   llvm-reduce.cpp
 
   DEPENDS
   intrinsics_gen
   )

llvm/tools/llvm-reduce/DeltaManager.cpp

 #include "deltas/ReduceInstructionsMIR.h"
 #include "deltas/ReduceMetadata.h"
 #include "deltas/ReduceModuleData.h"
 #include "deltas/ReduceOperandBundles.h"
 #include "deltas/ReduceOperands.h"
 #include "deltas/ReduceOperandsSkip.h"
 #include "deltas/ReduceOperandsToArgs.h"
 #include "deltas/ReduceSpecialGlobals.h"
+#include "deltas/ReduceVirtualRegisters.h"
 #include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
 extern cl::OptionCategory LLVMReduceOptions;
 static cl::opt<std::string>
     DeltaPasses("delta-passes",
                 cl::desc("Delta passes to run, separated by commas. By "
#define DELTA_PASSES                                                           \
   DELTA_PASS("module-data", reduceModuleDataDeltaPass)
 
 #define DELTA_PASSES_MIR                                                       \
   DELTA_PASS("instructions", reduceInstructionsMIRDeltaPass)                   \
   DELTA_PASS("ir-instruction-references",                                      \
              reduceIRInstructionReferencesDeltaPass)                           \
   DELTA_PASS("ir-block-references", reduceIRBlockReferencesDeltaPass)          \
   DELTA_PASS("ir-function-references", reduceIRFunctionReferencesDeltaPass)    \
-  DELTA_PASS("instruction-flags", reduceInstructionFlagsMIRDeltaPass)
+  DELTA_PASS("instruction-flags", reduceInstructionFlagsMIRDeltaPass)          \
+  DELTA_PASS("register-hints", reduceVirtualRegisterHintsDeltaPass)
 
 static void runAllDeltaPasses(TestRunner &Tester) {
 #define DELTA_PASS(NAME, FUNC) FUNC(Tester);
   if (Tester.getProgram().isMIR()) {
     DELTA_PASSES_MIR
   } else {
     DELTA_PASSES
   }

llvm/tools/llvm-reduce/ReducerWorkItem.cpp

static uint64_t computeMIRComplexityScoreImpl(const MachineFunction &MF) {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
 
   // Add for stack objects
   Score += MFI.getNumObjects();
 
   // Add in the block count.
   Score += 2 * MF.size();
 
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+    Register Reg = Register::index2VirtReg(I);
+    Score += MRI.getRegAllocationHints(Reg).second.size();
+  }
+
   for (const MachineBasicBlock &MBB : MF) {
     for (const MachineInstr &MI : MBB) {
       const unsigned Opc = MI.getOpcode();
 
       // Reductions may want or need to introduce implicit_defs, so don't count
       // them.
       // TODO: These probably should count in some way.
       if (Opc == TargetOpcode::IMPLICIT_DEF ||

llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.h

+//===- ReduceVirtualRegisters.h  - Specialized Delta Pass -------*- c++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a function which calls the Generic Delta pass in order
+// to simplify virtual register information.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_TOOLS_LLVM_REDUCE_DELTAS_REDUCEVIRTUALREGISTERS_H
+#define LLVM_TOOLS_LLVM_REDUCE_DELTAS_REDUCEVIRTUALREGISTERS_H
+
+namespace llvm {
+class TestRunner;
+
+/// Remove register allocation hints from virtual registes.
+void reduceVirtualRegisterHintsDeltaPass(TestRunner &Test);
+
+} // namespace llvm
+
+#endif

llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.cpp

+//===- ReduceVirtualRegisters.cpp - Specialized Delta Pass ----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a function which calls the Generic Delta pass in order
+// to simplify virtual registers in MIR.
+//
+//===----------------------------------------------------------------------===//
+
+#include "ReduceVirtualRegisters.h"
+#include "Delta.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+
+using namespace llvm;
+
+static void dropRegisterHintsFromFunction(Oracle &O, MachineFunction &MF) {
+  MachineRegisterInfo &MRI = MF.getRegInfo();
+  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+    Register Reg = Register::index2VirtReg(I);
+
+    const std::pair<Register, SmallVector<Register, 4>> &Hints =
+        MRI.getRegAllocationHints(Reg);
+    if (Hints.second.empty())
+      continue;
+
+    if (!O.shouldKeep())
+      MRI.clearSimpleHint(Reg);
+  }
+}
+
+static void dropRegisterHintsFromFunctions(Oracle &O,
+                                           ReducerWorkItem &WorkItem) {
+  for (const Function &F : WorkItem.getModule()) {
+    if (auto *MF = WorkItem.MMI->getMachineFunction(F))
+      dropRegisterHintsFromFunction(O, *MF);
+  }
+}
+
+void llvm::reduceVirtualRegisterHintsDeltaPass(TestRunner &Test) {
+  outs() << "*** Reducing virtual register hints from functions...\n";
+  runDeltaPass(Test, dropRegisterHintsFromFunctions);
+}