This is an archive of the discontinued LLVM Phabricator instance.

Differential D123330

[AMDGPU] Split unaligned LDS access instead of scalarizing
ClosedPublic

Authored by rampitec on Apr 7 2022, 11:48 AM.

Details

Reviewers
arsenm
foad
Commits
rGe66f0edb4031: [AMDGPU] Split unaligned LDS access instead of scalarizing
Summary

There is no need to fully scalarize an unaligned operation in
some case, just split it to alignment.

Diff Detail

Event Timeline

rampitec created this revision.Apr 7 2022, 11:48 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 7 2022, 11:48 AM
Herald added subscribers: hsmhsm, kerbowa, hiraditya and 7 others. · View Herald Transcript
rampitec requested review of this revision.Apr 7 2022, 11:48 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 7 2022, 11:48 AM
Herald added a subscriber: wdng. · View Herald Transcript
rampitec added inline comments.Apr 7 2022, 12:08 PM
llvm/test/CodeGen/AMDGPU/load-local.96.ll
355

This is the most essential effect. Here and in some other places.

arsenm accepted this revision.Apr 7 2022, 2:08 PM

expandUnalignedLoad/Store should probably be smarter

This revision is now accepted and ready to land.Apr 7 2022, 2:08 PM
Harbormaster completed remote builds in B158546: Diff 421306.Apr 7 2022, 2:22 PM
This revision was landed with ongoing or failed builds.Apr 7 2022, 2:27 PM
Closed by commit rGe66f0edb4031: [AMDGPU] Split unaligned LDS access instead of scalarizing (authored by rampitec). · Explain Why
This revision was automatically updated to reflect the committed changes.
rampitec added a commit: rGe66f0edb4031: [AMDGPU] Split unaligned LDS access instead of scalarizing.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
11 lines
test/
CodeGen/
AMDGPU/
148 lines
13 lines
308 lines
184 lines

Diff 421339

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 2,988 Lines • ▼ Show 20 Lines if (Alignment < Size && isTypeLegal(VT)) {
bool IsFast; bool IsFast;
unsigned AS = LN->getAddressSpace(); unsigned AS = LN->getAddressSpace();
// Expand unaligned loads earlier than legalization. Due to visitation order // Expand unaligned loads earlier than legalization. Due to visitation order
// problems during legalization, the emitted instructions to pack and unpack // problems during legalization, the emitted instructions to pack and unpack
// the bytes again are not eliminated in the case of an unaligned copy. // the bytes again are not eliminated in the case of an unaligned copy.
if (!allowsMisalignedMemoryAccesses( if (!allowsMisalignedMemoryAccesses(
VT, AS, Alignment, LN->getMemOperand()->getFlags(), &IsFast)) { VT, AS, Alignment, LN->getMemOperand()->getFlags(), &IsFast)) {
SDValue Ops[2];
if (VT.isVector()) if (VT.isVector())
std::tie(Ops[0], Ops[1]) = scalarizeVectorLoad(LN, DAG); return SplitVectorLoad(SDValue(LN, 0), DAG);
else
SDValue Ops[2];
std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(LN, DAG); std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(LN, DAG);
return DAG.getMergeValues(Ops, SDLoc(N)); return DAG.getMergeValues(Ops, SDLoc(N));
} }
if (!IsFast) if (!IsFast)
return SDValue(); return SDValue();
} }
Show All 34 Lines if (Alignment < Size && isTypeLegal(VT)) {
// Expand unaligned stores earlier than legalization. Due to visitation // Expand unaligned stores earlier than legalization. Due to visitation
// order problems during legalization, the emitted instructions to pack and // order problems during legalization, the emitted instructions to pack and
// unpack the bytes again are not eliminated in the case of an unaligned // unpack the bytes again are not eliminated in the case of an unaligned
// copy. // copy.
if (!allowsMisalignedMemoryAccesses( if (!allowsMisalignedMemoryAccesses(
VT, AS, Alignment, SN->getMemOperand()->getFlags(), &IsFast)) { VT, AS, Alignment, SN->getMemOperand()->getFlags(), &IsFast)) {
if (VT.isVector()) if (VT.isVector())
return scalarizeVectorStore(SN, DAG); return SplitVectorStore(SDValue(SN, 0), DAG);
return expandUnalignedStore(SN, DAG); return expandUnalignedStore(SN, DAG);
} }
if (!IsFast) if (!IsFast)
return SDValue(); return SDValue();
} }
▲ Show 20 Lines • Show All 1,855 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/ds-alignment.ll

Show First 20 Lines • Show All 389 Lines • ▼ Show 20 Lines
; ALIGNED-SDAG-NEXT: ds_read_u8 v6, v0 offset:5 ; ALIGNED-SDAG-NEXT: ds_read_u8 v6, v0 offset:5
; ALIGNED-SDAG-NEXT: ds_read_u8 v7, v0 offset:6 ; ALIGNED-SDAG-NEXT: ds_read_u8 v7, v0 offset:6
; ALIGNED-SDAG-NEXT: ds_read_u8 v8, v0 offset:7 ; ALIGNED-SDAG-NEXT: ds_read_u8 v8, v0 offset:7
; ALIGNED-SDAG-NEXT: ds_read_u8 v9, v0 offset:8 ; ALIGNED-SDAG-NEXT: ds_read_u8 v9, v0 offset:8
; ALIGNED-SDAG-NEXT: ds_read_u8 v10, v0 offset:9 ; ALIGNED-SDAG-NEXT: ds_read_u8 v10, v0 offset:9
; ALIGNED-SDAG-NEXT: ds_read_u8 v11, v0 offset:10 ; ALIGNED-SDAG-NEXT: ds_read_u8 v11, v0 offset:10
; ALIGNED-SDAG-NEXT: ds_read_u8 v0, v0 offset:11 ; ALIGNED-SDAG-NEXT: ds_read_u8 v0, v0 offset:11
; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v12, s1 ; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v12, s1
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(7)
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v5 offset:4
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(7)
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v6 offset:5
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(3) ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(3)
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v9 offset:8 ; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v11 offset:10
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(3) ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(3)
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v0 offset:11
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v9 offset:8
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v10 offset:9 ; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v10 offset:9
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v3 offset:2
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v4 offset:3
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v1 ; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v1
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v2 offset:1 ; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v2 offset:1
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v5 offset:4 ; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v3 offset:2
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v6 offset:5 ; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v4 offset:3
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v7 offset:6 ; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v7 offset:6
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v8 offset:7 ; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v8 offset:7
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(11)
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v11 offset:10
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(11)
; ALIGNED-SDAG-NEXT: ds_write_b8 v12, v0 offset:11
; ALIGNED-SDAG-NEXT: s_endpgm ; ALIGNED-SDAG-NEXT: s_endpgm
; ;
; ALIGNED-GISEL-LABEL: ds12align1: ; ALIGNED-GISEL-LABEL: ds12align1:
; ALIGNED-GISEL: ; %bb.0: ; ALIGNED-GISEL: ; %bb.0:
; ALIGNED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; ALIGNED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; ALIGNED-GISEL-NEXT: s_mov_b32 s2, 8 ; ALIGNED-GISEL-NEXT: s_mov_b32 s2, 8
; ALIGNED-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; ALIGNED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; ALIGNED-GISEL-NEXT: v_mov_b32_e32 v0, s0 ; ALIGNED-GISEL-NEXT: v_mov_b32_e32 v0, s0
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
} }
define amdgpu_kernel void @ds12align2(<3 x i32> addrspace(3)* %in, <3 x i32> addrspace(3)* %out) { define amdgpu_kernel void @ds12align2(<3 x i32> addrspace(3)* %in, <3 x i32> addrspace(3)* %out) {
; ALIGNED-SDAG-LABEL: ds12align2: ; ALIGNED-SDAG-LABEL: ds12align2:
; ALIGNED-SDAG: ; %bb.0: ; ALIGNED-SDAG: ; %bb.0:
; ALIGNED-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; ALIGNED-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(0) ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v0, s0 ; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v0, s0
; ALIGNED-SDAG-NEXT: ds_read_u16 v1, v0 offset:8 ; ALIGNED-SDAG-NEXT: ds_read_u16 v1, v0
; ALIGNED-SDAG-NEXT: ds_read_u16 v2, v0 ; ALIGNED-SDAG-NEXT: ds_read_u16 v2, v0 offset:2
; ALIGNED-SDAG-NEXT: ds_read_u16 v3, v0 offset:2 ; ALIGNED-SDAG-NEXT: ds_read_u16 v3, v0 offset:4
; ALIGNED-SDAG-NEXT: ds_read_u16 v4, v0 offset:4 ; ALIGNED-SDAG-NEXT: ds_read_u16 v4, v0 offset:10
; ALIGNED-SDAG-NEXT: ds_read_u16 v5, v0 offset:6 ; ALIGNED-SDAG-NEXT: ds_read_u16 v5, v0 offset:8
; ALIGNED-SDAG-NEXT: ds_read_u16 v0, v0 offset:6
; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v6, s1 ; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v6, s1
; ALIGNED-SDAG-NEXT: ds_read_u16 v0, v0 offset:10 ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(3)
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(5) ; ALIGNED-SDAG-NEXT: ds_write_b16 v6, v3 offset:4
; ALIGNED-SDAG-NEXT: ds_write_b16 v6, v1 offset:8 ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(3)
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(4) ; ALIGNED-SDAG-NEXT: ds_write_b16 v6, v4 offset:10
; ALIGNED-SDAG-NEXT: ds_write_b16 v6, v3 offset:2 ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(3)
; ALIGNED-SDAG-NEXT: ds_write_b16 v6, v2 ; ALIGNED-SDAG-NEXT: ds_write_b16 v6, v5 offset:8
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(5) ; ALIGNED-SDAG-NEXT: ds_write_b16 v6, v1
; ALIGNED-SDAG-NEXT: ds_write_b16 v6, v4 offset:4 ; ALIGNED-SDAG-NEXT: ds_write_b16 v6, v2 offset:2
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(5)
; ALIGNED-SDAG-NEXT: ds_write_b16 v6, v5 offset:6
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(5) ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(5)
; ALIGNED-SDAG-NEXT: ds_write_b16 v6, v0 offset:10 ; ALIGNED-SDAG-NEXT: ds_write_b16 v6, v0 offset:6
; ALIGNED-SDAG-NEXT: s_endpgm ; ALIGNED-SDAG-NEXT: s_endpgm
; ;
; ALIGNED-GISEL-LABEL: ds12align2: ; ALIGNED-GISEL-LABEL: ds12align2:
; ALIGNED-GISEL: ; %bb.0: ; ALIGNED-GISEL: ; %bb.0:
; ALIGNED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; ALIGNED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; ALIGNED-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; ALIGNED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; ALIGNED-GISEL-NEXT: v_mov_b32_e32 v0, s0 ; ALIGNED-GISEL-NEXT: v_mov_b32_e32 v0, s0
; ALIGNED-GISEL-NEXT: ds_read_u16 v1, v0 ; ALIGNED-GISEL-NEXT: ds_read_u16 v1, v0
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
} }
; TODO: Why does the ALIGNED-SDAG code use ds_write_b64 but not ds_read_b64? ; TODO: Why does the ALIGNED-SDAG code use ds_write_b64 but not ds_read_b64?
define amdgpu_kernel void @ds12align8(<3 x i32> addrspace(3)* %in, <3 x i32> addrspace(3)* %out) { define amdgpu_kernel void @ds12align8(<3 x i32> addrspace(3)* %in, <3 x i32> addrspace(3)* %out) {
; ALIGNED-SDAG-LABEL: ds12align8: ; ALIGNED-SDAG-LABEL: ds12align8:
; ALIGNED-SDAG: ; %bb.0: ; ALIGNED-SDAG: ; %bb.0:
; ALIGNED-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; ALIGNED-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(0) ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v0, s0 ; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v2, s0
; ALIGNED-SDAG-NEXT: ds_read_b32 v2, v0 offset:8 ; ALIGNED-SDAG-NEXT: ds_read_b64 v[0:1], v2
; ALIGNED-SDAG-NEXT: ds_read2_b32 v[0:1], v0 offset1:1 ; ALIGNED-SDAG-NEXT: ds_read_b32 v2, v2 offset:8
; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v3, s1 ; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v3, s1
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(1) ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(1)
; ALIGNED-SDAG-NEXT: ds_write_b32 v3, v2 offset:8
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(1)
; ALIGNED-SDAG-NEXT: ds_write_b64 v3, v[0:1] ; ALIGNED-SDAG-NEXT: ds_write_b64 v3, v[0:1]
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(1)
; ALIGNED-SDAG-NEXT: ds_write_b32 v3, v2 offset:8
; ALIGNED-SDAG-NEXT: s_endpgm ; ALIGNED-SDAG-NEXT: s_endpgm
; ;
; ALIGNED-GISEL-LABEL: ds12align8: ; ALIGNED-GISEL-LABEL: ds12align8:
; ALIGNED-GISEL: ; %bb.0: ; ALIGNED-GISEL: ; %bb.0:
; ALIGNED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; ALIGNED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; ALIGNED-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; ALIGNED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; ALIGNED-GISEL-NEXT: v_mov_b32_e32 v2, s0 ; ALIGNED-GISEL-NEXT: v_mov_b32_e32 v2, s0
; ALIGNED-GISEL-NEXT: ds_read2_b32 v[0:1], v2 offset1:1 ; ALIGNED-GISEL-NEXT: ds_read2_b32 v[0:1], v2 offset1:1
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; ALIGNED-SDAG-NEXT: ds_read_u8 v10, v0 offset:9 ; ALIGNED-SDAG-NEXT: ds_read_u8 v10, v0 offset:9
; ALIGNED-SDAG-NEXT: ds_read_u8 v11, v0 offset:10 ; ALIGNED-SDAG-NEXT: ds_read_u8 v11, v0 offset:10
; ALIGNED-SDAG-NEXT: ds_read_u8 v12, v0 offset:11 ; ALIGNED-SDAG-NEXT: ds_read_u8 v12, v0 offset:11
; ALIGNED-SDAG-NEXT: ds_read_u8 v13, v0 offset:12 ; ALIGNED-SDAG-NEXT: ds_read_u8 v13, v0 offset:12
; ALIGNED-SDAG-NEXT: ds_read_u8 v14, v0 offset:13 ; ALIGNED-SDAG-NEXT: ds_read_u8 v14, v0 offset:13
; ALIGNED-SDAG-NEXT: ds_read_u8 v15, v0 offset:14 ; ALIGNED-SDAG-NEXT: ds_read_u8 v15, v0 offset:14
; ALIGNED-SDAG-NEXT: ds_read_u8 v0, v0 offset:15 ; ALIGNED-SDAG-NEXT: ds_read_u8 v0, v0 offset:15
; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v16, s1 ; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v16, s1
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(3) ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(13)
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v13 offset:12
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(3)
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v14 offset:13
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v3 offset:2 ; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v3 offset:2
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(13)
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v4 offset:3 ; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v4 offset:3
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v1 ; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v1
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v2 offset:1 ; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v2 offset:1
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v5 offset:4 ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(13)
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v6 offset:5
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v9 offset:8
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v10 offset:9
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v7 offset:6 ; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v7 offset:6
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(13)
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v8 offset:7 ; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v8 offset:7
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v5 offset:4
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v6 offset:5
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(13)
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v11 offset:10 ; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v11 offset:10
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(13)
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v12 offset:11 ; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v12 offset:11
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(14) ; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v9 offset:8
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v10 offset:9
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(13)
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v15 offset:14 ; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v15 offset:14
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(13)
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v0 offset:15 ; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v0 offset:15
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v13 offset:12
; ALIGNED-SDAG-NEXT: ds_write_b8 v16, v14 offset:13
; ALIGNED-SDAG-NEXT: s_endpgm ; ALIGNED-SDAG-NEXT: s_endpgm
; ;
; ALIGNED-GISEL-LABEL: ds16align1: ; ALIGNED-GISEL-LABEL: ds16align1:
; ALIGNED-GISEL: ; %bb.0: ; ALIGNED-GISEL: ; %bb.0:
; ALIGNED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; ALIGNED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; ALIGNED-GISEL-NEXT: s_mov_b32 s2, 8 ; ALIGNED-GISEL-NEXT: s_mov_b32 s2, 8
; ALIGNED-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; ALIGNED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; ALIGNED-GISEL-NEXT: v_mov_b32_e32 v0, s0 ; ALIGNED-GISEL-NEXT: v_mov_b32_e32 v0, s0
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
} }
define amdgpu_kernel void @ds16align2(<4 x i32> addrspace(3)* %in, <4 x i32> addrspace(3)* %out) { define amdgpu_kernel void @ds16align2(<4 x i32> addrspace(3)* %in, <4 x i32> addrspace(3)* %out) {
; ALIGNED-SDAG-LABEL: ds16align2: ; ALIGNED-SDAG-LABEL: ds16align2:
; ALIGNED-SDAG: ; %bb.0: ; ALIGNED-SDAG: ; %bb.0:
; ALIGNED-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; ALIGNED-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(0) ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v0, s0 ; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v0, s0
; ALIGNED-SDAG-NEXT: ds_read_u16 v1, v0 offset:12
; ALIGNED-SDAG-NEXT: ds_read_u16 v2, v0 ; ALIGNED-SDAG-NEXT: ds_read_u16 v2, v0
; ALIGNED-SDAG-NEXT: ds_read_u16 v3, v0 offset:2 ; ALIGNED-SDAG-NEXT: ds_read_u16 v3, v0 offset:2
; ALIGNED-SDAG-NEXT: ds_read_u16 v4, v0 offset:4 ; ALIGNED-SDAG-NEXT: ds_read_u16 v4, v0 offset:4
; ALIGNED-SDAG-NEXT: ds_read_u16 v5, v0 offset:6 ; ALIGNED-SDAG-NEXT: ds_read_u16 v5, v0 offset:6
; ALIGNED-SDAG-NEXT: ds_read_u16 v6, v0 offset:8 ; ALIGNED-SDAG-NEXT: ds_read_u16 v6, v0 offset:8
; ALIGNED-SDAG-NEXT: ds_read_u16 v7, v0 offset:10 ; ALIGNED-SDAG-NEXT: ds_read_u16 v7, v0 offset:10
; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v8, s1 ; ALIGNED-SDAG-NEXT: ds_read_u16 v8, v0 offset:12
; ALIGNED-SDAG-NEXT: ds_read_u16 v0, v0 offset:14 ; ALIGNED-SDAG-NEXT: ds_read_u16 v0, v0 offset:14
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(7) ; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v1, s1
; ALIGNED-SDAG-NEXT: ds_write_b16 v8, v1 offset:12
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(6) ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(6)
; ALIGNED-SDAG-NEXT: ds_write_b16 v8, v3 offset:2 ; ALIGNED-SDAG-NEXT: ds_write_b16 v1, v3 offset:2
; ALIGNED-SDAG-NEXT: ds_write_b16 v8, v2 ; ALIGNED-SDAG-NEXT: ds_write_b16 v1, v2
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(7)
; ALIGNED-SDAG-NEXT: ds_write_b16 v8, v4 offset:4
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(6) ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(6)
; ALIGNED-SDAG-NEXT: ds_write_b16 v8, v6 offset:8 ; ALIGNED-SDAG-NEXT: ds_write_b16 v1, v5 offset:6
; ALIGNED-SDAG-NEXT: ds_write_b16 v8, v5 offset:6 ; ALIGNED-SDAG-NEXT: ds_write_b16 v1, v4 offset:4
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(7) ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(6)
; ALIGNED-SDAG-NEXT: ds_write_b16 v8, v7 offset:10 ; ALIGNED-SDAG-NEXT: ds_write_b16 v1, v7 offset:10
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(7) ; ALIGNED-SDAG-NEXT: ds_write_b16 v1, v6 offset:8
; ALIGNED-SDAG-NEXT: ds_write_b16 v8, v0 offset:14 ; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(6)
; ALIGNED-SDAG-NEXT: ds_write_b16 v1, v0 offset:14
; ALIGNED-SDAG-NEXT: ds_write_b16 v1, v8 offset:12
; ALIGNED-SDAG-NEXT: s_endpgm ; ALIGNED-SDAG-NEXT: s_endpgm
; ;
; ALIGNED-GISEL-LABEL: ds16align2: ; ALIGNED-GISEL-LABEL: ds16align2:
; ALIGNED-GISEL: ; %bb.0: ; ALIGNED-GISEL: ; %bb.0:
; ALIGNED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; ALIGNED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; ALIGNED-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; ALIGNED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; ALIGNED-GISEL-NEXT: v_mov_b32_e32 v0, s0 ; ALIGNED-GISEL-NEXT: v_mov_b32_e32 v0, s0
; ALIGNED-GISEL-NEXT: ds_read_u16 v1, v0 ; ALIGNED-GISEL-NEXT: ds_read_u16 v1, v0
Show All 34 Lines
; UNALIGNED-NEXT: ds_write2_b64 v4, v[0:1], v[2:3] offset1:1 ; UNALIGNED-NEXT: ds_write2_b64 v4, v[0:1], v[2:3] offset1:1
; UNALIGNED-NEXT: s_endpgm ; UNALIGNED-NEXT: s_endpgm
%val = load <4 x i32>, <4 x i32> addrspace(3)* %in, align 2 %val = load <4 x i32>, <4 x i32> addrspace(3)* %in, align 2
store <4 x i32> %val, <4 x i32> addrspace(3)* %out, align 2 store <4 x i32> %val, <4 x i32> addrspace(3)* %out, align 2
ret void ret void
} }
define amdgpu_kernel void @ds16align4(<4 x i32> addrspace(3)* %in, <4 x i32> addrspace(3)* %out) { define amdgpu_kernel void @ds16align4(<4 x i32> addrspace(3)* %in, <4 x i32> addrspace(3)* %out) {
; ALIGNED-SDAG-LABEL: ds16align4: ; ALIGNED-LABEL: ds16align4:
; ALIGNED-SDAG: ; %bb.0: ; ALIGNED: ; %bb.0:
; ALIGNED-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; ALIGNED-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(0) ; ALIGNED-NEXT: s_waitcnt lgkmcnt(0)
; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v2, s0 ; ALIGNED-NEXT: v_mov_b32_e32 v2, s0
; ALIGNED-SDAG-NEXT: ds_read2_b32 v[0:1], v2 offset0:2 offset1:3 ; ALIGNED-NEXT: ds_read2_b32 v[0:1], v2 offset1:1
; ALIGNED-SDAG-NEXT: ds_read2_b32 v[2:3], v2 offset1:1 ; ALIGNED-NEXT: ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
; ALIGNED-SDAG-NEXT: v_mov_b32_e32 v4, s1 ; ALIGNED-NEXT: v_mov_b32_e32 v4, s1
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(1) ; ALIGNED-NEXT: s_waitcnt lgkmcnt(1)
; ALIGNED-SDAG-NEXT: ds_write2_b32 v4, v0, v1 offset0:2 offset1:3 ; ALIGNED-NEXT: ds_write2_b32 v4, v0, v1 offset1:1
; ALIGNED-SDAG-NEXT: s_waitcnt lgkmcnt(1) ; ALIGNED-NEXT: s_waitcnt lgkmcnt(1)
; ALIGNED-SDAG-NEXT: ds_write2_b32 v4, v2, v3 offset1:1 ; ALIGNED-NEXT: ds_write2_b32 v4, v2, v3 offset0:2 offset1:3
; ALIGNED-SDAG-NEXT: s_endpgm ; ALIGNED-NEXT: s_endpgm
;
; ALIGNED-GISEL-LABEL: ds16align4:
; ALIGNED-GISEL: ; %bb.0:
; ALIGNED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; ALIGNED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; ALIGNED-GISEL-NEXT: v_mov_b32_e32 v2, s0
; ALIGNED-GISEL-NEXT: ds_read2_b32 v[0:1], v2 offset1:1
; ALIGNED-GISEL-NEXT: ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
; ALIGNED-GISEL-NEXT: v_mov_b32_e32 v4, s1
; ALIGNED-GISEL-NEXT: s_waitcnt lgkmcnt(1)
; ALIGNED-GISEL-NEXT: ds_write2_b32 v4, v0, v1 offset1:1
; ALIGNED-GISEL-NEXT: s_waitcnt lgkmcnt(1)
; ALIGNED-GISEL-NEXT: ds_write2_b32 v4, v2, v3 offset0:2 offset1:3
; ALIGNED-GISEL-NEXT: s_endpgm
; ;
; UNALIGNED-LABEL: ds16align4: ; UNALIGNED-LABEL: ds16align4:
; UNALIGNED: ; %bb.0: ; UNALIGNED: ; %bb.0:
; UNALIGNED-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; UNALIGNED-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; UNALIGNED-NEXT: s_waitcnt lgkmcnt(0) ; UNALIGNED-NEXT: s_waitcnt lgkmcnt(0)
; UNALIGNED-NEXT: v_mov_b32_e32 v0, s0 ; UNALIGNED-NEXT: v_mov_b32_e32 v0, s0
; UNALIGNED-NEXT: ds_read2_b64 v[0:3], v0 offset1:1 ; UNALIGNED-NEXT: ds_read2_b64 v[0:3], v0 offset1:1
; UNALIGNED-NEXT: v_mov_b32_e32 v4, s1 ; UNALIGNED-NEXT: v_mov_b32_e32 v4, s1
Show All 39 Lines

llvm/test/CodeGen/AMDGPU/load-local.96.ll

Show First 20 Lines • Show All 346 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
ret <3 x i32> %load ret <3 x i32> %load
} }
define <3 x i32> @load_lds_v3i32_align8(<3 x i32> addrspace(3)* %ptr) { define <3 x i32> @load_lds_v3i32_align8(<3 x i32> addrspace(3)* %ptr) {
; GFX9-LABEL: load_lds_v3i32_align8: ; GFX9-LABEL: load_lds_v3i32_align8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, v0
; GFX9-NEXT: ds_read2_b32 v[0:1], v0 offset1:1 ; GFX9-NEXT: ds_read_b64 v[0:1], v0
rampitecAuthorUnsubmitted
Done
ReplyInline Actions

This is the most essential effect. Here and in some other places.

rampitec: This is the most essential effect. Here and in some other places.
; GFX9-NEXT: ds_read_b32 v2, v2 offset:8 ; GFX9-NEXT: ds_read_b32 v2, v2 offset:8
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX7-LABEL: load_lds_v3i32_align8: ; GFX7-LABEL: load_lds_v3i32_align8:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v2, v0 ; GFX7-NEXT: v_mov_b32_e32 v2, v0
; GFX7-NEXT: s_mov_b32 m0, -1 ; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: ds_read2_b32 v[0:1], v0 offset1:1 ; GFX7-NEXT: ds_read_b64 v[0:1], v0
; GFX7-NEXT: ds_read_b32 v2, v2 offset:8 ; GFX7-NEXT: ds_read_b32 v2, v2 offset:8
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31] ; GFX7-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX6-LABEL: load_lds_v3i32_align8: ; GFX6-LABEL: load_lds_v3i32_align8:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 4, v0 ; GFX6-NEXT: v_mov_b32_e32 v2, v0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 8, v0
; GFX6-NEXT: s_mov_b32 m0, -1 ; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 8, v2
; GFX6-NEXT: ds_read_b64 v[0:1], v0
; GFX6-NEXT: ds_read_b32 v2, v2 ; GFX6-NEXT: ds_read_b32 v2, v2
; GFX6-NEXT: ds_read_b32 v0, v0
; GFX6-NEXT: ds_read_b32 v1, v1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: load_lds_v3i32_align8: ; GFX10-LABEL: load_lds_v3i32_align8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v2, v0 ; GFX10-NEXT: v_mov_b32_e32 v2, v0
; GFX10-NEXT: ds_read2_b32 v[0:1], v0 offset1:1 ; GFX10-NEXT: ds_read_b64 v[0:1], v0
; GFX10-NEXT: ds_read_b32 v2, v2 offset:8 ; GFX10-NEXT: ds_read_b32 v2, v2 offset:8
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 8 %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 8
ret <3 x i32> %load ret <3 x i32> %load
} }
define <3 x i32> @load_lds_v3i32_align16(<3 x i32> addrspace(3)* %ptr) { define <3 x i32> @load_lds_v3i32_align16(<3 x i32> addrspace(3)* %ptr) {
Show All 36 Lines

llvm/test/CodeGen/AMDGPU/store-local.128.ll

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @store_lds_v4i32_align1(<4 x i32> addrspace(3)* %out, <4 x i32> %x) { define amdgpu_kernel void @store_lds_v4i32_align1(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
; GFX9-LABEL: store_lds_v4i32_align1: ; GFX9-LABEL: store_lds_v4i32_align1:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s7 ; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_mov_b32_e32 v2, s6 ; GFX9-NEXT: v_mov_b32_e32 v2, s7
; GFX9-NEXT: ds_write_b8 v0, v1 offset:12 ; GFX9-NEXT: ds_write_b8 v0, v1 offset:8
; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:14 ; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:10
; GFX9-NEXT: ds_write_b8 v0, v2 offset:8 ; GFX9-NEXT: ds_write_b8 v0, v2 offset:12
; GFX9-NEXT: ds_write_b8_d16_hi v0, v2 offset:10 ; GFX9-NEXT: ds_write_b8_d16_hi v0, v2 offset:14
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: ds_write_b8 v0, v1 offset:4
; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:6
; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: s_lshr_b32 s0, s7, 8
; GFX9-NEXT: ds_write_b8 v0, v1 ; GFX9-NEXT: ds_write_b8 v0, v1
; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:2 ; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:2
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_lshr_b32 s0, s7, 24
; GFX9-NEXT: ds_write_b8 v0, v1 offset:13
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s6, 8 ; GFX9-NEXT: s_lshr_b32 s0, s6, 8
; GFX9-NEXT: ds_write_b8 v0, v1 offset:15 ; GFX9-NEXT: ds_write_b8 v0, v1 offset:4
; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:6
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s6, 24 ; GFX9-NEXT: s_lshr_b32 s0, s6, 24
; GFX9-NEXT: ds_write_b8 v0, v1 offset:9 ; GFX9-NEXT: ds_write_b8 v0, v1 offset:9
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s5, 8 ; GFX9-NEXT: s_lshr_b32 s0, s7, 8
; GFX9-NEXT: ds_write_b8 v0, v1 offset:11 ; GFX9-NEXT: ds_write_b8 v0, v1 offset:11
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s5, 24 ; GFX9-NEXT: s_lshr_b32 s0, s7, 24
; GFX9-NEXT: ds_write_b8 v0, v1 offset:5 ; GFX9-NEXT: ds_write_b8 v0, v1 offset:13
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s4, 8 ; GFX9-NEXT: s_lshr_b32 s0, s4, 8
; GFX9-NEXT: ds_write_b8 v0, v1 offset:7 ; GFX9-NEXT: ds_write_b8 v0, v1 offset:15
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s4, 24 ; GFX9-NEXT: s_lshr_b32 s0, s4, 24
; GFX9-NEXT: ds_write_b8 v0, v1 offset:1 ; GFX9-NEXT: ds_write_b8 v0, v1 offset:1
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s5, 8
; GFX9-NEXT: ds_write_b8 v0, v1 offset:3 ; GFX9-NEXT: ds_write_b8 v0, v1 offset:3
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s5, 24
; GFX9-NEXT: ds_write_b8 v0, v1 offset:5
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: ds_write_b8 v0, v1 offset:7
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX7-LABEL: store_lds_v4i32_align1: ; GFX7-LABEL: store_lds_v4i32_align1:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4 ; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4
; GFX7-NEXT: s_mov_b32 m0, -1 ; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s4 ; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s3 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s2 ; GFX7-NEXT: v_mov_b32_e32 v2, s3
; GFX7-NEXT: ds_write_b8 v0, v1 offset:12 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:8
; GFX7-NEXT: ds_write_b8 v0, v2 offset:8 ; GFX7-NEXT: ds_write_b8 v0, v2 offset:12
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_write_b8 v0, v1 offset:4
; GFX7-NEXT: v_mov_b32_e32 v1, s0 ; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: s_lshr_b32 s4, s3, 8
; GFX7-NEXT: ds_write_b8 v0, v1 ; GFX7-NEXT: ds_write_b8 v0, v1
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_lshr_b32 s4, s2, 8
; GFX7-NEXT: ds_write_b8 v0, v1 offset:4
; GFX7-NEXT: v_mov_b32_e32 v1, s4 ; GFX7-NEXT: v_mov_b32_e32 v1, s4
; GFX7-NEXT: s_lshr_b32 s4, s3, 24 ; GFX7-NEXT: s_lshr_b32 s4, s2, 24
; GFX7-NEXT: ds_write_b8 v0, v1 offset:13
; GFX7-NEXT: v_mov_b32_e32 v1, s4
; GFX7-NEXT: s_lshr_b32 s3, s3, 16
; GFX7-NEXT: ds_write_b8 v0, v1 offset:15
; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: s_lshr_b32 s3, s2, 8
; GFX7-NEXT: ds_write_b8 v0, v1 offset:14
; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: s_lshr_b32 s3, s2, 24
; GFX7-NEXT: ds_write_b8 v0, v1 offset:9 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:9
; GFX7-NEXT: v_mov_b32_e32 v1, s3 ; GFX7-NEXT: v_mov_b32_e32 v1, s4
; GFX7-NEXT: s_lshr_b32 s2, s2, 16 ; GFX7-NEXT: s_lshr_b32 s2, s2, 16
; GFX7-NEXT: ds_write_b8 v0, v1 offset:11 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:11
; GFX7-NEXT: v_mov_b32_e32 v1, s2 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_lshr_b32 s2, s1, 8 ; GFX7-NEXT: s_lshr_b32 s2, s3, 8
; GFX7-NEXT: ds_write_b8 v0, v1 offset:10 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:10
; GFX7-NEXT: v_mov_b32_e32 v1, s2 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_lshr_b32 s2, s1, 24 ; GFX7-NEXT: s_lshr_b32 s2, s3, 24
; GFX7-NEXT: ds_write_b8 v0, v1 offset:5 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:13
; GFX7-NEXT: v_mov_b32_e32 v1, s2 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_lshr_b32 s1, s1, 16 ; GFX7-NEXT: s_lshr_b32 s2, s3, 16
; GFX7-NEXT: ds_write_b8 v0, v1 offset:7 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:15
; GFX7-NEXT: v_mov_b32_e32 v1, s1 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_lshr_b32 s1, s0, 8 ; GFX7-NEXT: s_lshr_b32 s2, s0, 8
; GFX7-NEXT: ds_write_b8 v0, v1 offset:6 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:14
; GFX7-NEXT: v_mov_b32_e32 v1, s1 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_lshr_b32 s1, s0, 24 ; GFX7-NEXT: s_lshr_b32 s2, s0, 24
; GFX7-NEXT: ds_write_b8 v0, v1 offset:1 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:1
; GFX7-NEXT: v_mov_b32_e32 v1, s1 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_lshr_b32 s0, s0, 16 ; GFX7-NEXT: s_lshr_b32 s0, s0, 16
; GFX7-NEXT: ds_write_b8 v0, v1 offset:3 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:3
; GFX7-NEXT: v_mov_b32_e32 v1, s0 ; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: s_lshr_b32 s0, s1, 8
; GFX7-NEXT: ds_write_b8 v0, v1 offset:2 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:2
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: s_lshr_b32 s0, s1, 24
; GFX7-NEXT: ds_write_b8 v0, v1 offset:5
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: s_lshr_b32 s0, s1, 16
; GFX7-NEXT: ds_write_b8 v0, v1 offset:7
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: ds_write_b8 v0, v1 offset:6
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX6-LABEL: store_lds_v4i32_align1: ; GFX6-LABEL: store_lds_v4i32_align1:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX6-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4
; GFX6-NEXT: s_mov_b32 m0, -1 ; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s4 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: v_mov_b32_e32 v2, s2 ; GFX6-NEXT: v_mov_b32_e32 v2, s3
; GFX6-NEXT: ds_write_b8 v0, v1 offset:12 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:8
; GFX6-NEXT: ds_write_b8 v0, v2 offset:8 ; GFX6-NEXT: ds_write_b8 v0, v2 offset:12
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: ds_write_b8 v0, v1 offset:4
; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: s_lshr_b32 s4, s3, 8
; GFX6-NEXT: ds_write_b8 v0, v1 ; GFX6-NEXT: ds_write_b8 v0, v1
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: s_lshr_b32 s4, s2, 8
; GFX6-NEXT: ds_write_b8 v0, v1 offset:4
; GFX6-NEXT: v_mov_b32_e32 v1, s4 ; GFX6-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NEXT: s_lshr_b32 s4, s3, 24 ; GFX6-NEXT: s_lshr_b32 s4, s2, 24
; GFX6-NEXT: ds_write_b8 v0, v1 offset:13
; GFX6-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: ds_write_b8 v0, v1 offset:15
; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: s_lshr_b32 s3, s2, 8
; GFX6-NEXT: ds_write_b8 v0, v1 offset:14
; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: s_lshr_b32 s3, s2, 24
; GFX6-NEXT: ds_write_b8 v0, v1 offset:9 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:9
; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NEXT: s_lshr_b32 s2, s2, 16 ; GFX6-NEXT: s_lshr_b32 s2, s2, 16
; GFX6-NEXT: ds_write_b8 v0, v1 offset:11 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:11
; GFX6-NEXT: v_mov_b32_e32 v1, s2 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: s_lshr_b32 s2, s1, 8 ; GFX6-NEXT: s_lshr_b32 s2, s3, 8
; GFX6-NEXT: ds_write_b8 v0, v1 offset:10 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:10
; GFX6-NEXT: v_mov_b32_e32 v1, s2 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: s_lshr_b32 s2, s1, 24 ; GFX6-NEXT: s_lshr_b32 s2, s3, 24
; GFX6-NEXT: ds_write_b8 v0, v1 offset:5 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:13
; GFX6-NEXT: v_mov_b32_e32 v1, s2 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: s_lshr_b32 s1, s1, 16 ; GFX6-NEXT: s_lshr_b32 s2, s3, 16
; GFX6-NEXT: ds_write_b8 v0, v1 offset:7 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:15
; GFX6-NEXT: v_mov_b32_e32 v1, s1 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: s_lshr_b32 s1, s0, 8 ; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: ds_write_b8 v0, v1 offset:6 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:14
; GFX6-NEXT: v_mov_b32_e32 v1, s1 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: s_lshr_b32 s1, s0, 24 ; GFX6-NEXT: s_lshr_b32 s2, s0, 24
; GFX6-NEXT: ds_write_b8 v0, v1 offset:1 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:1
; GFX6-NEXT: v_mov_b32_e32 v1, s1 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: s_lshr_b32 s0, s0, 16 ; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: ds_write_b8 v0, v1 offset:3 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:3
; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: s_lshr_b32 s0, s1, 8
; GFX6-NEXT: ds_write_b8 v0, v1 offset:2 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:2
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: s_lshr_b32 s0, s1, 24
; GFX6-NEXT: ds_write_b8 v0, v1 offset:5
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: s_lshr_b32 s0, s1, 16
; GFX6-NEXT: ds_write_b8 v0, v1 offset:7
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: ds_write_b8 v0, v1 offset:6
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_lds_v4i32_align1: ; GFX10-LABEL: store_lds_v4i32_align1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s7 ; GFX10-NEXT: v_mov_b32_e32 v1, s6
; GFX10-NEXT: s_lshr_b32 s3, s6, 24 ; GFX10-NEXT: s_lshr_b32 s3, s7, 24
; GFX10-NEXT: v_mov_b32_e32 v2, s6 ; GFX10-NEXT: v_mov_b32_e32 v2, s7
; GFX10-NEXT: s_lshr_b32 s0, s7, 8 ; GFX10-NEXT: s_lshr_b32 s0, s6, 8
; GFX10-NEXT: s_lshr_b32 s2, s6, 8 ; GFX10-NEXT: s_lshr_b32 s1, s6, 24
; GFX10-NEXT: s_lshr_b32 s6, s5, 8 ; GFX10-NEXT: s_lshr_b32 s6, s4, 8
; GFX10-NEXT: v_mov_b32_e32 v3, s5 ; GFX10-NEXT: v_mov_b32_e32 v3, s4
; GFX10-NEXT: s_lshr_b32 s1, s7, 24 ; GFX10-NEXT: s_lshr_b32 s2, s7, 8
; GFX10-NEXT: s_lshr_b32 s5, s5, 24 ; GFX10-NEXT: s_lshr_b32 s4, s4, 24
; GFX10-NEXT: v_mov_b32_e32 v8, s3 ; GFX10-NEXT: v_mov_b32_e32 v8, s3
; GFX10-NEXT: v_mov_b32_e32 v5, s0 ; GFX10-NEXT: v_mov_b32_e32 v5, s0
; GFX10-NEXT: v_mov_b32_e32 v9, s6 ; GFX10-NEXT: v_mov_b32_e32 v9, s6
; GFX10-NEXT: s_lshr_b32 s0, s4, 8 ; GFX10-NEXT: s_lshr_b32 s0, s5, 8
; GFX10-NEXT: v_mov_b32_e32 v4, s4 ; GFX10-NEXT: v_mov_b32_e32 v4, s5
; GFX10-NEXT: v_mov_b32_e32 v6, s1 ; GFX10-NEXT: v_mov_b32_e32 v6, s1
; GFX10-NEXT: v_mov_b32_e32 v7, s2 ; GFX10-NEXT: v_mov_b32_e32 v7, s2
; GFX10-NEXT: ds_write_b8 v0, v1 offset:12 ; GFX10-NEXT: ds_write_b8 v0, v1 offset:8
; GFX10-NEXT: ds_write_b8_d16_hi v0, v1 offset:14 ; GFX10-NEXT: ds_write_b8_d16_hi v0, v1 offset:10
; GFX10-NEXT: ds_write_b8 v0, v2 offset:8 ; GFX10-NEXT: ds_write_b8 v0, v2 offset:12
; GFX10-NEXT: ds_write_b8_d16_hi v0, v2 offset:10 ; GFX10-NEXT: ds_write_b8_d16_hi v0, v2 offset:14
; GFX10-NEXT: ds_write_b8 v0, v3 offset:4 ; GFX10-NEXT: ds_write_b8 v0, v3
; GFX10-NEXT: ds_write_b8_d16_hi v0, v3 offset:6 ; GFX10-NEXT: ds_write_b8_d16_hi v0, v3 offset:2
; GFX10-NEXT: ds_write_b8 v0, v4 ; GFX10-NEXT: ds_write_b8 v0, v4 offset:4
; GFX10-NEXT: ds_write_b8_d16_hi v0, v4 offset:2 ; GFX10-NEXT: ds_write_b8_d16_hi v0, v4 offset:6
; GFX10-NEXT: ds_write_b8 v0, v5 offset:13 ; GFX10-NEXT: ds_write_b8 v0, v5 offset:9
; GFX10-NEXT: ds_write_b8 v0, v6 offset:15 ; GFX10-NEXT: ds_write_b8 v0, v6 offset:11
; GFX10-NEXT: ds_write_b8 v0, v7 offset:9 ; GFX10-NEXT: ds_write_b8 v0, v7 offset:13
; GFX10-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-NEXT: v_mov_b32_e32 v1, s4
; GFX10-NEXT: s_lshr_b32 s1, s4, 24 ; GFX10-NEXT: s_lshr_b32 s1, s5, 24
; GFX10-NEXT: v_mov_b32_e32 v2, s0 ; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: v_mov_b32_e32 v3, s1 ; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: ds_write_b8 v0, v8 offset:11 ; GFX10-NEXT: ds_write_b8 v0, v8 offset:15
; GFX10-NEXT: ds_write_b8 v0, v9 offset:5 ; GFX10-NEXT: ds_write_b8 v0, v9 offset:1
; GFX10-NEXT: ds_write_b8 v0, v1 offset:7 ; GFX10-NEXT: ds_write_b8 v0, v1 offset:3
; GFX10-NEXT: ds_write_b8 v0, v2 offset:1 ; GFX10-NEXT: ds_write_b8 v0, v2 offset:5
; GFX10-NEXT: ds_write_b8 v0, v3 offset:3 ; GFX10-NEXT: ds_write_b8 v0, v3 offset:7
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 1 store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 1
ret void ret void
} }
define amdgpu_kernel void @store_lds_v4i32_align2(<4 x i32> addrspace(3)* %out, <4 x i32> %x) { define amdgpu_kernel void @store_lds_v4i32_align2(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
; GFX9-LABEL: store_lds_v4i32_align2: ; GFX9-LABEL: store_lds_v4i32_align2:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s7 ; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_mov_b32_e32 v2, s6 ; GFX9-NEXT: v_mov_b32_e32 v2, s7
; GFX9-NEXT: ds_write_b16 v0, v1 offset:12 ; GFX9-NEXT: ds_write_b16 v0, v1 offset:8
; GFX9-NEXT: ds_write_b16_d16_hi v0, v1 offset:14 ; GFX9-NEXT: ds_write_b16_d16_hi v0, v1 offset:10
; GFX9-NEXT: ds_write_b16 v0, v2 offset:8 ; GFX9-NEXT: ds_write_b16 v0, v2 offset:12
; GFX9-NEXT: ds_write_b16_d16_hi v0, v2 offset:10 ; GFX9-NEXT: ds_write_b16_d16_hi v0, v2 offset:14
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: ds_write_b16 v0, v1 offset:4
; GFX9-NEXT: ds_write_b16_d16_hi v0, v1 offset:6
; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: ds_write_b16 v0, v1 ; GFX9-NEXT: ds_write_b16 v0, v1
; GFX9-NEXT: ds_write_b16_d16_hi v0, v1 offset:2 ; GFX9-NEXT: ds_write_b16_d16_hi v0, v1 offset:2
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: ds_write_b16 v0, v1 offset:4
; GFX9-NEXT: ds_write_b16_d16_hi v0, v1 offset:6
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX7-LABEL: store_lds_v4i32_align2: ; GFX7-LABEL: store_lds_v4i32_align2:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4 ; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4
; GFX7-NEXT: s_mov_b32 m0, -1 ; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s4 ; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s3 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s2 ; GFX7-NEXT: v_mov_b32_e32 v2, s3
; GFX7-NEXT: ds_write_b16 v0, v1 offset:12 ; GFX7-NEXT: ds_write_b16 v0, v1 offset:8
; GFX7-NEXT: ds_write_b16 v0, v2 offset:8 ; GFX7-NEXT: ds_write_b16 v0, v2 offset:12
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_write_b16 v0, v1 offset:4
; GFX7-NEXT: v_mov_b32_e32 v1, s0 ; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: s_lshr_b32 s3, s3, 16
; GFX7-NEXT: ds_write_b16 v0, v1 ; GFX7-NEXT: ds_write_b16 v0, v1
; GFX7-NEXT: v_mov_b32_e32 v1, s3 ; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_lshr_b32 s2, s2, 16 ; GFX7-NEXT: s_lshr_b32 s2, s2, 16
; GFX7-NEXT: ds_write_b16 v0, v1 offset:14 ; GFX7-NEXT: ds_write_b16 v0, v1 offset:4
; GFX7-NEXT: v_mov_b32_e32 v1, s2 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_lshr_b32 s1, s1, 16 ; GFX7-NEXT: s_lshr_b32 s2, s3, 16
; GFX7-NEXT: ds_write_b16 v0, v1 offset:10 ; GFX7-NEXT: ds_write_b16 v0, v1 offset:10
; GFX7-NEXT: v_mov_b32_e32 v1, s1 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_lshr_b32 s0, s0, 16 ; GFX7-NEXT: s_lshr_b32 s0, s0, 16
; GFX7-NEXT: ds_write_b16 v0, v1 offset:6 ; GFX7-NEXT: ds_write_b16 v0, v1 offset:14
; GFX7-NEXT: v_mov_b32_e32 v1, s0 ; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: s_lshr_b32 s0, s1, 16
; GFX7-NEXT: ds_write_b16 v0, v1 offset:2 ; GFX7-NEXT: ds_write_b16 v0, v1 offset:2
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: ds_write_b16 v0, v1 offset:6
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX6-LABEL: store_lds_v4i32_align2: ; GFX6-LABEL: store_lds_v4i32_align2:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX6-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4
; GFX6-NEXT: s_mov_b32 m0, -1 ; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s4 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: v_mov_b32_e32 v2, s2 ; GFX6-NEXT: v_mov_b32_e32 v2, s3
; GFX6-NEXT: ds_write_b16 v0, v1 offset:12 ; GFX6-NEXT: ds_write_b16 v0, v1 offset:8
; GFX6-NEXT: ds_write_b16 v0, v2 offset:8 ; GFX6-NEXT: ds_write_b16 v0, v2 offset:12
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: ds_write_b16 v0, v1 offset:4
; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: ds_write_b16 v0, v1 ; GFX6-NEXT: ds_write_b16 v0, v1
; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: s_lshr_b32 s2, s2, 16 ; GFX6-NEXT: s_lshr_b32 s2, s2, 16
; GFX6-NEXT: ds_write_b16 v0, v1 offset:14 ; GFX6-NEXT: ds_write_b16 v0, v1 offset:4
; GFX6-NEXT: v_mov_b32_e32 v1, s2 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: s_lshr_b32 s1, s1, 16 ; GFX6-NEXT: s_lshr_b32 s2, s3, 16
; GFX6-NEXT: ds_write_b16 v0, v1 offset:10 ; GFX6-NEXT: ds_write_b16 v0, v1 offset:10
; GFX6-NEXT: v_mov_b32_e32 v1, s1 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: s_lshr_b32 s0, s0, 16 ; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: ds_write_b16 v0, v1 offset:6 ; GFX6-NEXT: ds_write_b16 v0, v1 offset:14
; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: s_lshr_b32 s0, s1, 16
; GFX6-NEXT: ds_write_b16 v0, v1 offset:2 ; GFX6-NEXT: ds_write_b16 v0, v1 offset:2
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: ds_write_b16 v0, v1 offset:6
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_lds_v4i32_align2: ; GFX10-LABEL: store_lds_v4i32_align2:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s7 ; GFX10-NEXT: v_mov_b32_e32 v1, s6
; GFX10-NEXT: v_mov_b32_e32 v2, s6 ; GFX10-NEXT: v_mov_b32_e32 v2, s7
; GFX10-NEXT: v_mov_b32_e32 v3, s5 ; GFX10-NEXT: v_mov_b32_e32 v3, s4
; GFX10-NEXT: v_mov_b32_e32 v4, s4 ; GFX10-NEXT: v_mov_b32_e32 v4, s5
; GFX10-NEXT: ds_write_b16 v0, v1 offset:12 ; GFX10-NEXT: ds_write_b16 v0, v1 offset:8
; GFX10-NEXT: ds_write_b16_d16_hi v0, v1 offset:14 ; GFX10-NEXT: ds_write_b16_d16_hi v0, v1 offset:10
; GFX10-NEXT: ds_write_b16 v0, v2 offset:8 ; GFX10-NEXT: ds_write_b16 v0, v2 offset:12
; GFX10-NEXT: ds_write_b16_d16_hi v0, v2 offset:10 ; GFX10-NEXT: ds_write_b16_d16_hi v0, v2 offset:14
; GFX10-NEXT: ds_write_b16 v0, v3 offset:4 ; GFX10-NEXT: ds_write_b16 v0, v3
; GFX10-NEXT: ds_write_b16_d16_hi v0, v3 offset:6 ; GFX10-NEXT: ds_write_b16_d16_hi v0, v3 offset:2
; GFX10-NEXT: ds_write_b16 v0, v4 ; GFX10-NEXT: ds_write_b16 v0, v4 offset:4
; GFX10-NEXT: ds_write_b16_d16_hi v0, v4 offset:2 ; GFX10-NEXT: ds_write_b16_d16_hi v0, v4 offset:6
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 2 store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 2
ret void ret void
} }
define amdgpu_kernel void @store_lds_v4i32_align4(<4 x i32> addrspace(3)* %out, <4 x i32> %x) { define amdgpu_kernel void @store_lds_v4i32_align4(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
; GFX9-LABEL: store_lds_v4i32_align4: ; GFX9-LABEL: store_lds_v4i32_align4:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
Show All 26 Lines
; ;
; GFX6-LABEL: store_lds_v4i32_align4: ; GFX6-LABEL: store_lds_v4i32_align4:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX6-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4
; GFX6-NEXT: s_mov_b32 m0, -1 ; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s4 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v2, s1
; GFX6-NEXT: ds_write2_b32 v0, v1, v2 offset1:1
; GFX6-NEXT: v_mov_b32_e32 v1, s2 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: v_mov_b32_e32 v2, s3 ; GFX6-NEXT: v_mov_b32_e32 v2, s3
; GFX6-NEXT: ds_write2_b32 v0, v1, v2 offset0:2 offset1:3 ; GFX6-NEXT: ds_write2_b32 v0, v1, v2 offset0:2 offset1:3
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v2, s1
; GFX6-NEXT: ds_write2_b32 v0, v1, v2 offset1:1
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_lds_v4i32_align4: ; GFX10-LABEL: store_lds_v4i32_align4:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
▲ Show 20 Lines • Show All 129 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/store-local.96.ll

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @store_lds_v3i32_align1(<3 x i32> addrspace(3)* %out, <3 x i32> %x) { define amdgpu_kernel void @store_lds_v3i32_align1(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
; GFX9-LABEL: store_lds_v3i32_align1: ; GFX9-LABEL: store_lds_v3i32_align1:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_mov_b32_e32 v2, s5 ; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: ds_write_b8 v0, v1 offset:8 ; GFX9-NEXT: ds_write_b8 v0, v1 offset:8
; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:10 ; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:10
; GFX9-NEXT: ds_write_b8 v0, v2 offset:4 ; GFX9-NEXT: ds_write_b8 v0, v2
; GFX9-NEXT: ds_write_b8_d16_hi v0, v2 offset:6 ; GFX9-NEXT: ds_write_b8_d16_hi v0, v2 offset:2
; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_lshr_b32 s0, s6, 8 ; GFX9-NEXT: s_lshr_b32 s0, s6, 8
; GFX9-NEXT: ds_write_b8 v0, v1 ; GFX9-NEXT: ds_write_b8 v0, v1 offset:4
; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:2 ; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:6
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s6, 24 ; GFX9-NEXT: s_lshr_b32 s0, s6, 24
; GFX9-NEXT: ds_write_b8 v0, v1 offset:9 ; GFX9-NEXT: ds_write_b8 v0, v1 offset:9
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s5, 8
; GFX9-NEXT: ds_write_b8 v0, v1 offset:11
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s5, 24
; GFX9-NEXT: ds_write_b8 v0, v1 offset:5
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s4, 8 ; GFX9-NEXT: s_lshr_b32 s0, s4, 8
; GFX9-NEXT: ds_write_b8 v0, v1 offset:7 ; GFX9-NEXT: ds_write_b8 v0, v1 offset:11
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s4, 24 ; GFX9-NEXT: s_lshr_b32 s0, s4, 24
; GFX9-NEXT: ds_write_b8 v0, v1 offset:1 ; GFX9-NEXT: ds_write_b8 v0, v1 offset:1
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s5, 8
; GFX9-NEXT: ds_write_b8 v0, v1 offset:3 ; GFX9-NEXT: ds_write_b8 v0, v1 offset:3
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_lshr_b32 s0, s5, 24
; GFX9-NEXT: ds_write_b8 v0, v1 offset:5
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: ds_write_b8 v0, v1 offset:7
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX7-LABEL: store_lds_v3i32_align1: ; GFX7-LABEL: store_lds_v3i32_align1:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4 ; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4
; GFX7-NEXT: s_mov_b32 m0, -1 ; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s4 ; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s2 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1 ; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: ds_write_b8 v0, v1 offset:8 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:8
; GFX7-NEXT: ds_write_b8 v0, v2 offset:4 ; GFX7-NEXT: ds_write_b8 v0, v2
; GFX7-NEXT: v_mov_b32_e32 v1, s0 ; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_lshr_b32 s3, s2, 8 ; GFX7-NEXT: s_lshr_b32 s3, s2, 8
; GFX7-NEXT: ds_write_b8 v0, v1 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:4
; GFX7-NEXT: v_mov_b32_e32 v1, s3 ; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: s_lshr_b32 s3, s2, 24 ; GFX7-NEXT: s_lshr_b32 s3, s2, 24
; GFX7-NEXT: ds_write_b8 v0, v1 offset:9 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:9
; GFX7-NEXT: v_mov_b32_e32 v1, s3 ; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: s_lshr_b32 s2, s2, 16 ; GFX7-NEXT: s_lshr_b32 s2, s2, 16
; GFX7-NEXT: ds_write_b8 v0, v1 offset:11 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:11
; GFX7-NEXT: v_mov_b32_e32 v1, s2 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_lshr_b32 s2, s1, 8 ; GFX7-NEXT: s_lshr_b32 s2, s0, 8
; GFX7-NEXT: ds_write_b8 v0, v1 offset:10 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:10
; GFX7-NEXT: v_mov_b32_e32 v1, s2 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_lshr_b32 s2, s1, 24 ; GFX7-NEXT: s_lshr_b32 s2, s0, 24
; GFX7-NEXT: ds_write_b8 v0, v1 offset:5
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_lshr_b32 s1, s1, 16
; GFX7-NEXT: ds_write_b8 v0, v1 offset:7
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_lshr_b32 s1, s0, 8
; GFX7-NEXT: ds_write_b8 v0, v1 offset:6
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_lshr_b32 s1, s0, 24
; GFX7-NEXT: ds_write_b8 v0, v1 offset:1 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:1
; GFX7-NEXT: v_mov_b32_e32 v1, s1 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_lshr_b32 s0, s0, 16 ; GFX7-NEXT: s_lshr_b32 s0, s0, 16
; GFX7-NEXT: ds_write_b8 v0, v1 offset:3 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:3
; GFX7-NEXT: v_mov_b32_e32 v1, s0 ; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: s_lshr_b32 s0, s1, 8
; GFX7-NEXT: ds_write_b8 v0, v1 offset:2 ; GFX7-NEXT: ds_write_b8 v0, v1 offset:2
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: s_lshr_b32 s0, s1, 24
; GFX7-NEXT: ds_write_b8 v0, v1 offset:5
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: s_lshr_b32 s0, s1, 16
; GFX7-NEXT: ds_write_b8 v0, v1 offset:7
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: ds_write_b8 v0, v1 offset:6
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX6-LABEL: store_lds_v3i32_align1: ; GFX6-LABEL: store_lds_v3i32_align1:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX6-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4
; GFX6-NEXT: s_mov_b32 m0, -1 ; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s4 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: v_mov_b32_e32 v1, s2 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: v_mov_b32_e32 v2, s1 ; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_write_b8 v0, v1 offset:8 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:8
; GFX6-NEXT: ds_write_b8 v0, v2 offset:4 ; GFX6-NEXT: ds_write_b8 v0, v2
; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: s_lshr_b32 s3, s2, 8 ; GFX6-NEXT: s_lshr_b32 s3, s2, 8
; GFX6-NEXT: ds_write_b8 v0, v1 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:4
; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: s_lshr_b32 s3, s2, 24 ; GFX6-NEXT: s_lshr_b32 s3, s2, 24
; GFX6-NEXT: ds_write_b8 v0, v1 offset:9 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:9
; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: s_lshr_b32 s2, s2, 16 ; GFX6-NEXT: s_lshr_b32 s2, s2, 16
; GFX6-NEXT: ds_write_b8 v0, v1 offset:11 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:11
; GFX6-NEXT: v_mov_b32_e32 v1, s2 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: s_lshr_b32 s2, s1, 8 ; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: ds_write_b8 v0, v1 offset:10 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:10
; GFX6-NEXT: v_mov_b32_e32 v1, s2 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: s_lshr_b32 s2, s1, 24 ; GFX6-NEXT: s_lshr_b32 s2, s0, 24
; GFX6-NEXT: ds_write_b8 v0, v1 offset:5
; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: ds_write_b8 v0, v1 offset:7
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: s_lshr_b32 s1, s0, 8
; GFX6-NEXT: ds_write_b8 v0, v1 offset:6
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: s_lshr_b32 s1, s0, 24
; GFX6-NEXT: ds_write_b8 v0, v1 offset:1 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:1
; GFX6-NEXT: v_mov_b32_e32 v1, s1 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: s_lshr_b32 s0, s0, 16 ; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: ds_write_b8 v0, v1 offset:3 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:3
; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: s_lshr_b32 s0, s1, 8
; GFX6-NEXT: ds_write_b8 v0, v1 offset:2 ; GFX6-NEXT: ds_write_b8 v0, v1 offset:2
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: s_lshr_b32 s0, s1, 24
; GFX6-NEXT: ds_write_b8 v0, v1 offset:5
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: s_lshr_b32 s0, s1, 16
; GFX6-NEXT: ds_write_b8 v0, v1 offset:7
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: ds_write_b8 v0, v1 offset:6
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_lds_v3i32_align1: ; GFX10-LABEL: store_lds_v3i32_align1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-NEXT: v_mov_b32_e32 v1, s6
; GFX10-NEXT: v_mov_b32_e32 v2, s5 ; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: v_mov_b32_e32 v3, s4 ; GFX10-NEXT: v_mov_b32_e32 v3, s5
; GFX10-NEXT: s_lshr_b32 s0, s6, 8 ; GFX10-NEXT: s_lshr_b32 s0, s6, 8
; GFX10-NEXT: s_lshr_b32 s1, s6, 24 ; GFX10-NEXT: s_lshr_b32 s1, s6, 24
; GFX10-NEXT: s_lshr_b32 s2, s5, 8 ; GFX10-NEXT: s_lshr_b32 s2, s4, 8
; GFX10-NEXT: s_lshr_b32 s3, s5, 24 ; GFX10-NEXT: s_lshr_b32 s3, s4, 24
; GFX10-NEXT: s_lshr_b32 s5, s4, 8 ; GFX10-NEXT: s_lshr_b32 s4, s5, 8
; GFX10-NEXT: s_lshr_b32 s4, s4, 24 ; GFX10-NEXT: s_lshr_b32 s5, s5, 24
; GFX10-NEXT: v_mov_b32_e32 v4, s0 ; GFX10-NEXT: v_mov_b32_e32 v4, s0
; GFX10-NEXT: v_mov_b32_e32 v5, s1 ; GFX10-NEXT: v_mov_b32_e32 v5, s1
; GFX10-NEXT: v_mov_b32_e32 v6, s2 ; GFX10-NEXT: v_mov_b32_e32 v6, s2
; GFX10-NEXT: v_mov_b32_e32 v7, s3 ; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: v_mov_b32_e32 v8, s5 ; GFX10-NEXT: v_mov_b32_e32 v8, s4
; GFX10-NEXT: v_mov_b32_e32 v9, s4 ; GFX10-NEXT: v_mov_b32_e32 v9, s5
; GFX10-NEXT: ds_write_b8 v0, v1 offset:8 ; GFX10-NEXT: ds_write_b8 v0, v1 offset:8
; GFX10-NEXT: ds_write_b8_d16_hi v0, v1 offset:10 ; GFX10-NEXT: ds_write_b8_d16_hi v0, v1 offset:10
; GFX10-NEXT: ds_write_b8 v0, v2 offset:4 ; GFX10-NEXT: ds_write_b8 v0, v2
; GFX10-NEXT: ds_write_b8_d16_hi v0, v2 offset:6 ; GFX10-NEXT: ds_write_b8_d16_hi v0, v2 offset:2
; GFX10-NEXT: ds_write_b8 v0, v3 ; GFX10-NEXT: ds_write_b8 v0, v3 offset:4
; GFX10-NEXT: ds_write_b8_d16_hi v0, v3 offset:2 ; GFX10-NEXT: ds_write_b8_d16_hi v0, v3 offset:6
; GFX10-NEXT: ds_write_b8 v0, v4 offset:9 ; GFX10-NEXT: ds_write_b8 v0, v4 offset:9
; GFX10-NEXT: ds_write_b8 v0, v5 offset:11 ; GFX10-NEXT: ds_write_b8 v0, v5 offset:11
; GFX10-NEXT: ds_write_b8 v0, v6 offset:5 ; GFX10-NEXT: ds_write_b8 v0, v6 offset:1
; GFX10-NEXT: ds_write_b8 v0, v7 offset:7 ; GFX10-NEXT: ds_write_b8 v0, v7 offset:3
; GFX10-NEXT: ds_write_b8 v0, v8 offset:1 ; GFX10-NEXT: ds_write_b8 v0, v8 offset:5
; GFX10-NEXT: ds_write_b8 v0, v9 offset:3 ; GFX10-NEXT: ds_write_b8 v0, v9 offset:7
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 1 store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 1
ret void ret void
} }
define amdgpu_kernel void @store_lds_v3i32_align2(<3 x i32> addrspace(3)* %out, <3 x i32> %x) { define amdgpu_kernel void @store_lds_v3i32_align2(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
; GFX9-LABEL: store_lds_v3i32_align2: ; GFX9-LABEL: store_lds_v3i32_align2:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_mov_b32_e32 v2, s5 ; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: ds_write_b16 v0, v1 offset:8 ; GFX9-NEXT: ds_write_b16 v0, v1 offset:8
; GFX9-NEXT: ds_write_b16_d16_hi v0, v1 offset:10 ; GFX9-NEXT: ds_write_b16_d16_hi v0, v1 offset:10
; GFX9-NEXT: ds_write_b16 v0, v2 offset:4 ; GFX9-NEXT: ds_write_b16 v0, v2
; GFX9-NEXT: ds_write_b16_d16_hi v0, v2 offset:6 ; GFX9-NEXT: ds_write_b16_d16_hi v0, v2 offset:2
; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: ds_write_b16 v0, v1 ; GFX9-NEXT: ds_write_b16 v0, v1 offset:4
; GFX9-NEXT: ds_write_b16_d16_hi v0, v1 offset:2 ; GFX9-NEXT: ds_write_b16_d16_hi v0, v1 offset:6
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX7-LABEL: store_lds_v3i32_align2: ; GFX7-LABEL: store_lds_v3i32_align2:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4 ; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4
; GFX7-NEXT: s_mov_b32 m0, -1 ; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s4 ; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s2 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: v_mov_b32_e32 v2, s1 ; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: ds_write_b16 v0, v1 offset:8 ; GFX7-NEXT: ds_write_b16 v0, v1 offset:8
; GFX7-NEXT: ds_write_b16 v0, v2 offset:4 ; GFX7-NEXT: ds_write_b16 v0, v2
; GFX7-NEXT: v_mov_b32_e32 v1, s0 ; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_lshr_b32 s2, s2, 16 ; GFX7-NEXT: s_lshr_b32 s2, s2, 16
; GFX7-NEXT: ds_write_b16 v0, v1 ; GFX7-NEXT: ds_write_b16 v0, v1 offset:4
; GFX7-NEXT: v_mov_b32_e32 v1, s2 ; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_lshr_b32 s1, s1, 16
; GFX7-NEXT: ds_write_b16 v0, v1 offset:10
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_lshr_b32 s0, s0, 16 ; GFX7-NEXT: s_lshr_b32 s0, s0, 16
; GFX7-NEXT: ds_write_b16 v0, v1 offset:6 ; GFX7-NEXT: ds_write_b16 v0, v1 offset:10
; GFX7-NEXT: v_mov_b32_e32 v1, s0 ; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: s_lshr_b32 s0, s1, 16
; GFX7-NEXT: ds_write_b16 v0, v1 offset:2 ; GFX7-NEXT: ds_write_b16 v0, v1 offset:2
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: ds_write_b16 v0, v1 offset:6
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX6-LABEL: store_lds_v3i32_align2: ; GFX6-LABEL: store_lds_v3i32_align2:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX6-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4
; GFX6-NEXT: s_mov_b32 m0, -1 ; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s4 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: v_mov_b32_e32 v1, s2 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: v_mov_b32_e32 v2, s1 ; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_write_b16 v0, v1 offset:8 ; GFX6-NEXT: ds_write_b16 v0, v1 offset:8
; GFX6-NEXT: ds_write_b16 v0, v2 offset:4 ; GFX6-NEXT: ds_write_b16 v0, v2
; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: s_lshr_b32 s2, s2, 16 ; GFX6-NEXT: s_lshr_b32 s2, s2, 16
; GFX6-NEXT: ds_write_b16 v0, v1 ; GFX6-NEXT: ds_write_b16 v0, v1 offset:4
; GFX6-NEXT: v_mov_b32_e32 v1, s2 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: ds_write_b16 v0, v1 offset:10
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 16 ; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: ds_write_b16 v0, v1 offset:6 ; GFX6-NEXT: ds_write_b16 v0, v1 offset:10
; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: s_lshr_b32 s0, s1, 16
; GFX6-NEXT: ds_write_b16 v0, v1 offset:2 ; GFX6-NEXT: ds_write_b16 v0, v1 offset:2
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: ds_write_b16 v0, v1 offset:6
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_lds_v3i32_align2: ; GFX10-LABEL: store_lds_v3i32_align2:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-NEXT: v_mov_b32_e32 v1, s6
; GFX10-NEXT: v_mov_b32_e32 v2, s5 ; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: v_mov_b32_e32 v3, s4 ; GFX10-NEXT: v_mov_b32_e32 v3, s5
; GFX10-NEXT: ds_write_b16 v0, v1 offset:8 ; GFX10-NEXT: ds_write_b16 v0, v1 offset:8
; GFX10-NEXT: ds_write_b16_d16_hi v0, v1 offset:10 ; GFX10-NEXT: ds_write_b16_d16_hi v0, v1 offset:10
; GFX10-NEXT: ds_write_b16 v0, v2 offset:4 ; GFX10-NEXT: ds_write_b16 v0, v2
; GFX10-NEXT: ds_write_b16_d16_hi v0, v2 offset:6 ; GFX10-NEXT: ds_write_b16_d16_hi v0, v2 offset:2
; GFX10-NEXT: ds_write_b16 v0, v3 ; GFX10-NEXT: ds_write_b16 v0, v3 offset:4
; GFX10-NEXT: ds_write_b16_d16_hi v0, v3 offset:2 ; GFX10-NEXT: ds_write_b16_d16_hi v0, v3 offset:6
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 2 store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 2
ret void ret void
} }
define amdgpu_kernel void @store_lds_v3i32_align4(<3 x i32> addrspace(3)* %out, <3 x i32> %x) { define amdgpu_kernel void @store_lds_v3i32_align4(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
; GFX9-LABEL: store_lds_v3i32_align4: ; GFX9-LABEL: store_lds_v3i32_align4:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
Show All 24 Lines
; ;
; GFX6-LABEL: store_lds_v3i32_align4: ; GFX6-LABEL: store_lds_v3i32_align4:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX6-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x4
; GFX6-NEXT: s_mov_b32 m0, -1 ; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s4 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v2, s1
; GFX6-NEXT: ds_write2_b32 v0, v1, v2 offset1:1
; GFX6-NEXT: v_mov_b32_e32 v1, s2 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: ds_write_b32 v0, v1 offset:8 ; GFX6-NEXT: ds_write_b32 v0, v1 offset:8
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: ds_write2_b32 v0, v2, v1 offset1:1
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_lds_v3i32_align4: ; GFX10-LABEL: store_lds_v3i32_align4:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
▲ Show 20 Lines • Show All 125 Lines • Show Last 20 Lines