make fast unaligned memory accesses implicit with SSE4.2 or SSE4a

[spatel]

Summary

This is a follow-on from the discussion in http://reviews.llvm.org/D12154.

This change allows memset/memcpy to use SSE or AVX memory accesses for any chip that has generally fast unaligned memory ops.

A motivating use case for this change is a clang invocation that doesn't explicitly set the CPU, but does target a feature that we know only exists on a CPU that supports fast unaligned memops. For example:
$ clang -O1 foo.c -mavx

This resolves a difference in lowering noted in PR24449:
https://llvm.org/bugs/show_bug.cgi?id=24449

Currently, we use different store types depending on whether the example can be lowered as a memset or not.

[RKSimon]

LGTM - My only concern was Via Nano which Agner says has particularly bad unaligned memory access. But these appear to only have SSE41.

[zansari]

Hi Sanjay,

Just one tiny comment, otherwise lgtm.

Thanks,
Zia.

lib/Target/X86/X86Subtarget.cpp

197 ↗

(On Diff #32957)

Nehalem/Silvermont

[spatel]

lib/Target/X86/X86Subtarget.cpp

197 ↗

(On Diff #32957)

Thanks - updated.

llvm/trunk/lib/Target/X86/X86Subtarget.cpp

if (!FullFS.empty())
       FullFS = "+64bit,+sse2," + FullFS;
     else
       FullFS = "+64bit,+sse2";
   }
 
   // Parse features string and set the CPU.
   ParseSubtargetFeatures(CPUName, FullFS);
 
+  // All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
+  // 16-bytes and under that are reasonably fast. These features were
+  // introduced with Intel's Nehalem/Silvermont and AMD's Family10h
+  // micro-architectures respectively.
+  if (hasSSE42() || hasSSE4A())
+    IsUAMemUnder32Slow = false;
+  
   InstrItins = getInstrItineraryForCPU(CPUName);
 
   // It's important to keep the MCSubtargetInfo feature bits in sync with
   // target data structure which is shared with MC code emitter, etc.
   if (In64BitMode)
     ToggleFeature(X86::Mode64Bit);
   else if (In32BitMode)
     ToggleFeature(X86::Mode32Bit);

llvm/trunk/test/CodeGen/X86/slow-unaligned-mem.ll

 ; Other chips with slow unaligned memory accesses
 
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=c3-2          2>&1 | FileCheck %s --check-prefix=SLOW
 
 ; Verify that the slow/fast unaligned memory attribute is set correctly for each CPU model.
 ; Slow chips use 4-byte stores. Fast chips with SSE or later use something other than 4-byte stores.
 ; Chips that don't have SSE use 4-byte stores either way, so they're not tested.
 
+; Also verify that SSE4.2 or SSE4a imply fast unaligned accesses.
+
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse4.2       2>&1 | FileCheck %s --check-prefix=FAST
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse4a        2>&1 | FileCheck %s --check-prefix=FAST
+
 define void @store_zeros(i8* %a) {
 ; SLOW-NOT: not a recognized processor
 ; SLOW-LABEL: store_zeros:
 ; SLOW:       # BB#0:
 ; SLOW-NEXT:    movl
 ; SLOW-NEXT:    movl
 ; SLOW-NEXT:    movl
 ; SLOW-NEXT:    movl