[CSKY] Fix some Clang warnings. NFC

[MaskRay]

.

[zixuan-wu]

Thank you for this patch. I was also going to draft it. Following unused variable in td file can also be removed.

diff --git a/llvm/lib/Target/CSKY/CSKYInstrFormats.td b/llvm/lib/Target/CSKY/CSKYInstrFormats.td
index 9b6ef9c..8144a50 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrFormats.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrFormats.td
@@ -655,7 +655,7 @@ class R_Z_1<bits<6> sop, bits<5> pcode, string op>

 // Format< OP[6] | RZ[5] | 00000[5] | SOP[6] | PCODE[5] | 00000[5] >
 // Instructions:(2) clrf32, clrt32
-class R_Z_2<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
+class R_Z_2<bits<6> sop, bits<5> pcode, string op>
     : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
     (ins CARRY:$ca, GPR:$false), !strconcat(op, "\t$rz"), []> {
   bits<5> rz;
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.td b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
index 28e364c..300ecce 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
@@ -734,8 +734,8 @@ let Predicates= [iHasE2] in {

 let Predicates = [iHas2E3] in {
   def MVCV32 : R_Z_1<0x1, 0x10, "mvcv32">;
-  def CLRF32 : R_Z_2<0xB, 0x1, "clrf32", []>;
-  def CLRT32 : R_Z_2<0xB, 0x2, "clrt32", []>;
+  def CLRF32 : R_Z_2<0xB, 0x1, "clrf32">;
+  def CLRT32 : R_Z_2<0xB, 0x2, "clrt32">;
 }

llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp

36

this can also be removed

[zixuan-wu]

In D122872#3421455, @zixuan-wu wrote:

Thank you for this patch. I was also going to draft it. Following unused variable in td file can also be removed.

diff --git a/llvm/lib/Target/CSKY/CSKYInstrFormats.td b/llvm/lib/Target/CSKY/CSKYInstrFormats.td
index 9b6ef9c..8144a50 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrFormats.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrFormats.td
@@ -655,7 +655,7 @@ class R_Z_1<bits<6> sop, bits<5> pcode, string op>

 // Format< OP[6] | RZ[5] | 00000[5] | SOP[6] | PCODE[5] | 00000[5] >
 // Instructions:(2) clrf32, clrt32
-class R_Z_2<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
+class R_Z_2<bits<6> sop, bits<5> pcode, string op>
     : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
     (ins CARRY:$ca, GPR:$false), !strconcat(op, "\t$rz"), []> {
   bits<5> rz;
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.td b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
index 28e364c..300ecce 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
@@ -734,8 +734,8 @@ let Predicates= [iHasE2] in {

 let Predicates = [iHas2E3] in {
   def MVCV32 : R_Z_1<0x1, 0x10, "mvcv32">;
-  def CLRF32 : R_Z_2<0xB, 0x1, "clrf32", []>;
-  def CLRT32 : R_Z_2<0xB, 0x2, "clrt32", []>;
+  def CLRF32 : R_Z_2<0xB, 0x1, "clrf32">;
+  def CLRT32 : R_Z_2<0xB, 0x2, "clrt32">;
 }

I mean you can continue this patch @MaskRay

llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp

case CSKY::BR16:
     Bits = 10;
     Scale = 2;
     break;
   case CSKY::BR32:
     Bits = 16;
     Scale = 2;
     break;
   default:
-    assert(0);
-    break;
+    llvm_unreachable("");
   }
 
   unsigned MaxOffs = ((1 << (Bits - 1)) - 1) * Scale;
   return MaxOffs;
 }
 
 /// findAvailableWater - Look for an existing entry in the WaterList in which
 /// we can place the CPE referenced from U so it's within range of U's MI.

llvm/lib/Target/CSKY/CSKYInstrFormats.td

class R_Z_1<bits<6> sop, bits<5> pcode, string op>
   let Inst{20 - 16} = 0;
   let Inst{15 - 10} = sop;
   let Inst{9 - 5} = pcode;
   let Inst{4 - 0} = rz;
 }
 
 // Format< OP[6] | RZ[5] | 00000[5] | SOP[6] | PCODE[5] | 00000[5] >
 // Instructions:(2) clrf32, clrt32
-class R_Z_2<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
+class R_Z_2<bits<6> sop, bits<5> pcode, string op>
     : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
     (ins CARRY:$ca, GPR:$false), !strconcat(op, "\t$rz"), []> {
   bits<5> rz;
   let Inst{25 - 21} = rz;
   let Inst{20 - 16} = 0;
   let Inst{15 - 10} = sop;
   let Inst{9 - 5} = pcode;
   let Inst{4 - 0} = 0;

llvm/lib/Target/CSKY/CSKYInstrInfo.cpp

BuildMI(MBB, I, DL, get(Opcode), DestReg)
       .addImm(0)
       .addMemOperand(MMO);
 }
 
 void CSKYInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator I,
                                 const DebugLoc &DL, MCRegister DestReg,
                                 MCRegister SrcReg, bool KillSrc) const {
-
-  MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
-
   if (CSKY::GPRRegClass.contains(SrcReg) &&
       CSKY::CARRYRegClass.contains(DestReg)) {
     if (STI.hasE2()) {
       BuildMI(MBB, I, DL, get(CSKY::BTSTI32), DestReg)
           .addReg(SrcReg, getKillRegState(KillSrc))
           .addImm(0);
     } else {
       assert(SrcReg < CSKY::R8);

llvm/lib/Target/CSKY/CSKYInstrInfo.td

let Predicates= [iHasE2] in {
 
   let usesCustomInserter = 1 in
   def ISEL32 : CSKYPseudo<(outs GPR:$dst), (ins CARRY:$cond, GPR:$src1, GPR:$src2),
     "!isel32\t$dst, $src1, src2", [(set GPR:$dst, (select CARRY:$cond, GPR:$src1, GPR:$src2))]>;
 }
 
 let Predicates = [iHas2E3] in {
   def MVCV32 : R_Z_1<0x1, 0x10, "mvcv32">;
-  def CLRF32 : R_Z_2<0xB, 0x1, "clrf32", []>;
-  def CLRT32 : R_Z_2<0xB, 0x2, "clrt32", []>;
+  def CLRF32 : R_Z_2<0xB, 0x1, "clrf32">;
+  def CLRT32 : R_Z_2<0xB, 0x2, "clrt32">;
 }
 
 //===----------------------------------------------------------------------===//
 // Branch and call instructions.
 //===----------------------------------------------------------------------===//
 
 let isBranch = 1, isTerminator = 1 in {
   let isBarrier = 1, isPredicable = 1 in

 
 let hasSideEffects = 0, isNotDuplicable = 1 in
 def CONSTPOOL_ENTRY : CSKYPseudo<(outs),
   (ins i32imm:$instid, i32imm:$cpidx, i32imm:$size), "", []>;
 
 include "CSKYInstrInfo16Instr.td"
 include "CSKYInstrInfoF1.td"
 include "CSKYInstrInfoF2.td"
-include "CSKYInstrAlias.td"
+include "CSKYInstrAlias.td"
 

llvm/lib/Target/CSKY/CSKYMachineFunctionInfo.h

 #ifndef LLVM_LIB_TARGET_CSKY_CSKYMACHINEFUNCTIONINFO_H
 #define LLVM_LIB_TARGET_CSKY_CSKYMACHINEFUNCTIONINFO_H
 
 #include "llvm/CodeGen/MachineFunction.h"
 
 namespace llvm {
 
 class CSKYMachineFunctionInfo : public MachineFunctionInfo {
-  MachineFunction &MF;
-
   Register GlobalBaseReg = 0;
   bool SpillsCR = false;
 
   int VarArgsFrameIndex = 0;
   unsigned VarArgsSaveSize = 0;
 
   int spillAreaSize = 0;
 
   bool LRSpilled = false;
 
   unsigned PICLabelUId = 0;
 
 public:
-  CSKYMachineFunctionInfo(MachineFunction &MF) : MF(MF) {}
+  CSKYMachineFunctionInfo(MachineFunction &) {}
 
   Register getGlobalBaseReg() const { return GlobalBaseReg; }
   void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; }
 
   void setSpillsCR() { SpillsCR = true; }
   bool isCRSpilled() const { return SpillsCR; }
 
   void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; }

llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp

 
 #define DEBUG_TYPE "csky-disassembler"
 
 typedef MCDisassembler::DecodeStatus DecodeStatus;
 
 namespace {
 class CSKYDisassembler : public MCDisassembler {
   std::unique_ptr<MCInstrInfo const> const MCII;
-  mutable bool inDataRegion = false;
   mutable StringRef symbolName;
 
   DecodeStatus handleCROperand(MCInst &Instr) const;
 
 public:
   CSKYDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
                    MCInstrInfo const *MCII);
 
   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
                                              const MCDisassembler *Decoder) {
   if (RegNo >= 32)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
+// TODO
+LLVM_ATTRIBUTE_UNUSED
 static DecodeStatus DecodesFPR128RegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
                                                const MCDisassembler *Decoder) {
   if (RegNo >= 16)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(FPR128DecoderTable[RegNo]));
   return MCDisassembler::Success;
static DecodeStatus DecodemGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             const MCDisassembler *Decoder) {
   if (RegNo >= 8)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
   return MCDisassembler::Success;
 }
 
+// TODO
+LLVM_ATTRIBUTE_UNUSED
 static DecodeStatus DecodeGPRSPRegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
                                              const MCDisassembler *Decoder) {
   if (RegNo != 14)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
   return MCDisassembler::Success;

llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp

if (Expr->getKind() == MCExpr::Target) {
       case MCSymbolRefExpr::VK_GOTOFF:
         return ELF::R_CKCORE_GOTOFF;
       case MCSymbolRefExpr::VK_PLT:
         return ELF::R_CKCORE_PLT32;
       case MCSymbolRefExpr::VK_None:
         return ELF::R_CKCORE_ADDR32;
       }
     }
+    return ELF::R_CKCORE_NONE;
   case FK_Data_8:
     Ctx.reportError(Fixup.getLoc(), "8-byte data relocations not supported");
     return ELF::R_CKCORE_NONE;
   case CSKY::fixup_csky_addr32:
     return ELF::R_CKCORE_ADDR32;
   case CSKY::fixup_csky_addr_hi16:
     return ELF::R_CKCORE_ADDR_HI16;
   case CSKY::fixup_csky_addr_lo16:

llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFStreamer.h

void emitInstruction(const MCInst &Inst,
                        const MCSubtargetInfo &STI) override {
     EmitMappingSymbol("$t");
     MCELFStreamer::emitInstruction(Inst, STI);
   }
   void emitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) override {
     EmitMappingSymbol("$d");
     MCELFStreamer::emitValueImpl(Value, Size, Loc);
   }
-  void reset() {
+  void reset() override {
     MappingSymbolCounter = 0;
     State = EMS_None;
     MCELFStreamer::reset();
   }
 };
 
 } // namespace llvm
 #endif