[MCA] Moving six instruction flags out of InstrDesc and into InstructionBase.

[holland11]

Summary

TLDR: This patch proposes moving a few instruction flags out of the InstrDesc and into the InstructionBase. This move allows for those flags to be modified by InstrPostProcess.

This is patch is an audible from https://reviews.llvm.org/D117451 . The primary goal of that/this patch was to give developers the ability (through InstrPostProcess and/or CustomBehaviour) to modify instruction flags such as RetireOOO. The reason why flags like RetireOOO (and the others affected by this patch) can't be modified yet is because they are stored within the InstrDesc object and InstrDesc objects are made const after creation. In my original attempt to solve this problem, I figured that I'd take the opportunity to allow for the other attributes within the InstrDesc to be modified by InstrPostProcess at the same time. This would allow for mca users to be able to do things like modify the instruction's Reads / Writes, MaxLatency, NumMicroOps, and which resources are used. This is something that I wanted to accomplish eventually because currently, CB and IPP have the ability to add *new* hazards to instructions, but they don't have the ability to remove *existing* hazards.

The first problem with my initial proposal was that it was way too "open-ended". The way it let IPP modify the InstrDesc objects gave the user way too much control and not enough guidance. The second problem (and one that contributes to why the first problem is a problem) is that doing things like modifying the MaxLatency attribute, or removing a Use / Def from the Writes / Reads vectors isn't nearly as straight forward as just modifying / removing them. These attributes are originally set with each other in mind and so to modify them correctly, you may need to modify a group of them in a logical way. For example, if you lower an instruction's MaxLatency, you will likely get an error when running MCA due to MCA thinking the instruction is finished executing, but it still has Reads / Writes active for more cycles.

To solve both of those problems, making the API much more rigid and self explanatory would be desired, if not required. On top of that, I would also need to make sure that I have a full understanding of how all of these attributes are connected together so that I could either design the API in a way that makes it difficult for users to make mistakes or just provide very detailed comments that help users make their modifications in the proper ways.

At this time, I do not feel confident in my ability to do the second part of the above paragraph, but I do still want to be able to modify the flags from this patch that do not have dependencies like the ones described above (MayLoad, MayStore, HasSideEffects, BeginGroup, EndGroup, and RetireOOO).

There are two main ways that I can achieve this. The first is shown in this diff. What I have done is moved those flags out of the InstrDesc struct and into the InstructionBase class.

The alternative is to leave the flags as part of the InstrDesc struct and inject IPP into the InstrDesc creation function so that it can have a chance to modify the flags. (If done this way, I would have the IPP injection done in a way that would restrict IPP to only modifying these flags.)

The main advantages of doing it in the proposed way are:

• The flags can be modified easily by IPP without actually having to change anything about the way IPP works or is injected.
• The flags can be modified per individual instruction rather than being forced to modify them for every single instruction which matches a particular opcode (only one InstrDesc object is created per opcode so you could have several instructions in the same input that share the same InstrDesc, but they do not share the same InstructionBase).

The main disadvantage is:

• Those flags are now duplicated for every single instruction with the same opcode. So if your input file has multiple instructions all with the same opcode (and you don't want to modify them independently), you'll end up using unnecessary memory from those duplicated / redundant flags.

Since what's being duplicated is only 6 bools, I don't see this as a major disadvantage, but I am absolutely open to changing this patch to conform to the second option (leave the flags in InstrDesc and then inject IPP in a restrictive way to let it modify those flags) if you feel it would be best. I am also open to other ideas, suggestions, questions, and feedback.

This patch also includes a few unrelated and minor changes. I added the opcode to the debug printing for an instruction (so that it's not as much of a hassle to get the opcode number of an in input instruction) and I added the IPP::resetState() function. It's theoretically possible that a target's IPP may maintain some state during its lifetime to help it make decisions based on what it has previously seen in the input. But since IPP is created outside of the CodeRegion loop, IPP should have an opportunity to reset its state whenever a new CodeRegion is being evaluated (since the CodeRegions are supposed to be evaluated independently of each other). Neither of these are particularly disruptive and I don't imagine they'll be controversial so I figured they'd be fine to tack on here.

As always, thank you very much for your time. I would appreciate any form of input that anybody might have.

[andreadb]

Just a couple of minor comments. Otherwise, patch looks good to me.

Thanks!

llvm/include/llvm/MCA/CustomBehaviour.h

53–60

The last sentence alone is already descriptive enough.

I suggest that we keep that last sentence only, and get rid of the reference to llvm-mca.cpp. While it is true that the llvm-mca driver is currently the only user of this logic (at least, this is true for upstream), there may be other downstream users of this library.

llvm/include/llvm/MCA/Instruction.h

513–525

Could you please convert all these eight boolean flags (starting from IsALoadBarrier, ending with your new flags) to bitfields?

Example:

bool IsALoadBarrier : 1;
bool IsAStoreBarrier : 1;
...
bool RetireOOO : 1;

llvm/tools/llvm-mca/llvm-mca.cpp

516–517

This comment is a bit repetitive and it can be removed. A similar comment is already added by this patch to the declaration of resetState. So, I am not convinced that it is adding extra information to the reader.

[holland11]

In D121508#3376937, @andreadb wrote:

Just a couple of minor comments. Otherwise, patch looks good to me.

Thanks!

I'd never learned about that bitfield declaration pattern before. Just googled it and it makes a lot of sense. I've seen that pattern around mca's codebase, but I always assumed it was just an alternative way to give default values. Thanks for the suggestions!

[holland11]

Made the changes that were suggested by Andrea.

llvm/include/llvm/MCA/CustomBehaviour.h

public:
   virtual ~InstrPostProcess() = default;
 
   /// This method can be overriden by targets to modify the mca::Instruction
   /// object after it has been lowered from the MCInst.
   /// This is generally a less disruptive alternative to modifying the
   /// scheduling model.
   virtual void postProcessInstruction(std::unique_ptr<Instruction> &Inst,
                                       const MCInst &MCI) {}
+
+  // The resetState() method gets invoked at the beginning of each code region
+  // so that targets that override this function can clear any state that they
+  // have left from the previous code region.
+  virtual void resetState() {}
 };
 
 /// Class which can be overriden by targets to enforce instruction
 /// dependencies and behaviours that aren't expressed well enough
 /// within the scheduling model for mca to automatically simulate
 /// them properly.
 /// If you implement this class for your target, make sure to also implement
 /// a target specific InstrPostProcess class as well.
 class CustomBehaviour {
 protected:
   const MCSubtargetInfo &STI;
   const mca::SourceMgr &SrcMgr;

llvm/include/llvm/MCA/Instruction.h

struct InstrDesc {
   unsigned MaxLatency;
   // Number of MicroOps for this instruction.
   unsigned NumMicroOps;
   // SchedClassID used to construct this InstrDesc.
   // This information is currently used by views to do fast queries on the
   // subtarget when computing the reciprocal throughput.
   unsigned SchedClassID;
 
-  unsigned MayLoad : 1;
-  unsigned MayStore : 1;
-  unsigned HasSideEffects : 1;
-  unsigned BeginGroup : 1;
-  unsigned EndGroup : 1;
-  unsigned RetireOOO : 1;
-
   // True if all buffered resources are in-order, and there is at least one
   // buffer which is a dispatch hazard (BufferSize = 0).
   unsigned MustIssueImmediately : 1;
 
   // A zero latency instruction doesn't consume any scheduler resources.
   bool isZeroLatency() const { return !MaxLatency && Resources.empty(); }
 
   InstrDesc() = default;
class InstructionBase {
   SmallVector<ReadState, 4> Uses;
 
   // List of operands which can be used by mca::CustomBehaviour
   std::vector<MCAOperand> Operands;
 
   // Instruction opcode which can be used by mca::CustomBehaviour
   unsigned Opcode;
 
   // Flags used by the LSUnit.
-  bool IsALoadBarrier;
-  bool IsAStoreBarrier;
+  bool IsALoadBarrier : 1;
+  bool IsAStoreBarrier : 1;
+  // Flags copied from the InstrDesc and potentially modified by
+  // CustomBehaviour or (more likely) InstrPostProcess.
+  bool MayLoad : 1;
+  bool MayStore : 1;
+  bool HasSideEffects : 1;
+  bool BeginGroup : 1;
+  bool EndGroup : 1;
+  bool RetireOOO : 1;
 
 public:
   InstructionBase(const InstrDesc &D, const unsigned Opcode)
       : Desc(D), IsOptimizableMove(false), Operands(0), Opcode(Opcode),
         IsALoadBarrier(false), IsAStoreBarrier(false) {}
 
   SmallVectorImpl<WriteState> &getDefs() { return Defs; }
   ArrayRef<WriteState> getDefs() const { return Defs; }
   SmallVectorImpl<ReadState> &getUses() { return Uses; }
   ArrayRef<ReadState> getUses() const { return Uses; }
unsigned getNumUsers() const {
     for (const WriteState &Def : Defs)
       NumUsers += Def.getNumUsers();
     return NumUsers;
   }
 
   // Returns true if this instruction is a candidate for move elimination.
   bool isOptimizableMove() const { return IsOptimizableMove; }
   void setOptimizableMove() { IsOptimizableMove = true; }
-  bool isMemOp() const { return Desc.MayLoad || Desc.MayStore; }
+  bool isMemOp() const { return MayLoad || MayStore; }
+
+  // Getters and setters for general instruction flags.
+  void setMayLoad(bool newVal) { MayLoad = newVal; }
+  void setMayStore(bool newVal) { MayStore = newVal; }
+  void setHasSideEffects(bool newVal) { HasSideEffects = newVal; }
+  void setBeginGroup(bool newVal) { BeginGroup = newVal; }
+  void setEndGroup(bool newVal) { EndGroup = newVal; }
+  void setRetireOOO(bool newVal) { RetireOOO = newVal; }
+
+  bool getMayLoad() const { return MayLoad; }
+  bool getMayStore() const { return MayStore; }
+  bool getHasSideEffects() const { return HasSideEffects; }
+  bool getBeginGroup() const { return BeginGroup; }
+  bool getEndGroup() const { return EndGroup; }
+  bool getRetireOOO() const { return RetireOOO; }
 };
 
 /// An instruction propagated through the simulated instruction pipeline.
 ///
 /// This class is used to monitor changes to the internal state of instructions
 /// that are sent to the various components of the simulated hardware pipeline.
 class Instruction : public InstructionBase {
   enum InstrStage {

llvm/lib/MCA/HardwareUnits/LSUnit.cpp

dbgs() << "[LSUnit] Group (" << GroupIt.first << "): "
            << ", #Inst = " << Group.getNumInstructions()
            << ", #IIssued = " << Group.getNumExecuting()
            << ", #IExecuted = " << Group.getNumExecuted() << '\n';
   }
 }
 #endif
 
 unsigned LSUnit::dispatch(const InstRef &IR) {
-  const InstrDesc &Desc = IR.getInstruction()->getDesc();
-  bool IsStoreBarrier = IR.getInstruction()->isAStoreBarrier();
-  bool IsLoadBarrier = IR.getInstruction()->isALoadBarrier();
-  assert((Desc.MayLoad || Desc.MayStore) && "Not a memory operation!");
+  const Instruction &IS = *IR.getInstruction();
+  bool IsStoreBarrier = IS.isAStoreBarrier();
+  bool IsLoadBarrier = IS.isALoadBarrier();
+  assert((IS.getMayLoad() || IS.getMayStore()) && "Not a memory operation!");
 
-  if (Desc.MayLoad)
+  if (IS.getMayLoad())
     acquireLQSlot();
-  if (Desc.MayStore)
+  if (IS.getMayStore())
     acquireSQSlot();
 
-  if (Desc.MayStore) {
+  if (IS.getMayStore()) {
     unsigned NewGID = createMemoryGroup();
     MemoryGroup &NewGroup = getGroup(NewGID);
     NewGroup.addInstruction();
 
     // A store may not pass a previous load or load barrier.
     unsigned ImmediateLoadDominator =
         std::max(CurrentLoadGroupID, CurrentLoadBarrierGroupID);
     if (ImmediateLoadDominator) {
if (CurrentStoreGroupID &&
       StoreGroup.addSuccessor(&NewGroup, !assumeNoAlias());
     }
 
 
     CurrentStoreGroupID = NewGID;
     if (IsStoreBarrier)
       CurrentStoreBarrierGroupID = NewGID;
 
-    if (Desc.MayLoad) {
+    if (IS.getMayLoad()) {
       CurrentLoadGroupID = NewGID;
       if (IsLoadBarrier)
         CurrentLoadBarrierGroupID = NewGID;
     }
 
     return NewGID;
   }
 
-  assert(Desc.MayLoad && "Expected a load!");
+  assert(IS.getMayLoad() && "Expected a load!");
 
   unsigned ImmediateLoadDominator =
       std::max(CurrentLoadGroupID, CurrentLoadBarrierGroupID);
 
   // A new load group is created if we are in one of the following situations:
   // 1) This is a load barrier (by construction, a load barrier is always
   //    assigned to a different memory group).
   // 2) There is no load in flight (by construction we always keep loads and
unsigned LSUnit::dispatch(const InstRef &IR) {
 
   // A load may pass a previous load.
   MemoryGroup &Group = getGroup(CurrentLoadGroupID);
   Group.addInstruction();
   return CurrentLoadGroupID;
 }
 
 LSUnit::Status LSUnit::isAvailable(const InstRef &IR) const {
-  const InstrDesc &Desc = IR.getInstruction()->getDesc();
-  if (Desc.MayLoad && isLQFull())
+  const Instruction &IS = *IR.getInstruction();
+  if (IS.getMayLoad() && isLQFull())
     return LSUnit::LSU_LQUEUE_FULL;
-  if (Desc.MayStore && isSQFull())
+  if (IS.getMayStore() && isSQFull())
     return LSUnit::LSU_SQUEUE_FULL;
   return LSUnit::LSU_AVAILABLE;
 }
 
 void LSUnitBase::onInstructionExecuted(const InstRef &IR) {
   unsigned GroupID = IR.getInstruction()->getLSUTokenID();
   auto It = Groups.find(GroupID);
   assert(It != Groups.end() && "Instruction not dispatched to the LS unit");
   It->second->onInstructionExecuted(IR);
   if (It->second->isExecuted())
     Groups.erase(It);
 }
 
 void LSUnitBase::onInstructionRetired(const InstRef &IR) {
-  const InstrDesc &Desc = IR.getInstruction()->getDesc();
-  bool IsALoad = Desc.MayLoad;
-  bool IsAStore = Desc.MayStore;
+  const Instruction &IS = *IR.getInstruction();
+  bool IsALoad = IS.getMayLoad();
+  bool IsAStore = IS.getMayStore();
   assert((IsALoad || IsAStore) && "Expected a memory operation!");
 
   if (IsALoad) {
     releaseLQSlot();
     LLVM_DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << IR.getSourceIndex()
                       << " has been removed from the load queue.\n");
   }
 

llvm/lib/MCA/InstrBuilder.cpp

InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
   if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
     return make_error<InstructionError<MCInst>>(
         "found an unsupported instruction in the input assembly sequence.",
         MCI);
   }
 
   LLVM_DEBUG(dbgs() << "\n\t\tOpcode Name= " << MCII.getName(Opcode) << '\n');
   LLVM_DEBUG(dbgs() << "\t\tSchedClassID=" << SchedClassID << '\n');
+  LLVM_DEBUG(dbgs() << "\t\tOpcode=" << Opcode << '\n');
 
   // Create a new empty descriptor.
   std::unique_ptr<InstrDesc> ID = std::make_unique<InstrDesc>();
   ID->NumMicroOps = SCDesc.NumMicroOps;
   ID->SchedClassID = SchedClassID;
 
   if (MCDesc.isCall() && FirstCallInst) {
     // We don't correctly model calls.
     WithColor::warning() << "found a call in the input assembly sequence.\n";
     WithColor::note() << "call instructions are not correctly modeled. "
                       << "Assume a latency of 100cy.\n";
     FirstCallInst = false;
   }
 
   if (MCDesc.isReturn() && FirstReturnInst) {
     WithColor::warning() << "found a return instruction in the input"
                          << " assembly sequence.\n";
     WithColor::note() << "program counter updates are ignored.\n";
     FirstReturnInst = false;
   }
 
-  ID->MayLoad = MCDesc.mayLoad();
-  ID->MayStore = MCDesc.mayStore();
-  ID->HasSideEffects = MCDesc.hasUnmodeledSideEffects();
-  ID->BeginGroup = SCDesc.BeginGroup;
-  ID->EndGroup = SCDesc.EndGroup;
-  ID->RetireOOO = SCDesc.RetireOOO;
-
   initializeUsedResources(*ID, SCDesc, STI, ProcResourceMasks);
   computeMaxLatency(*ID, MCDesc, SCDesc, STI);
 
   if (Error Err = verifyOperands(MCDesc, MCI))
     return std::move(Err);
 
   populateWrites(*ID, MCI, SchedClassID);
   populateReads(*ID, MCI, SchedClassID);

 InstrBuilder::createInstruction(const MCInst &MCI) {
   Expected<const InstrDesc &> DescOrErr = getOrCreateInstrDesc(MCI);
   if (!DescOrErr)
     return DescOrErr.takeError();
   const InstrDesc &D = *DescOrErr;
   std::unique_ptr<Instruction> NewIS =
       std::make_unique<Instruction>(D, MCI.getOpcode());
 
+  const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
+  const MCSchedClassDesc &SCDesc =
+      *STI.getSchedModel().getSchedClassDesc(D.SchedClassID);
+
+  NewIS->setMayLoad(MCDesc.mayLoad());
+  NewIS->setMayStore(MCDesc.mayStore());
+  NewIS->setHasSideEffects(MCDesc.hasUnmodeledSideEffects());
+  NewIS->setBeginGroup(SCDesc.BeginGroup);
+  NewIS->setEndGroup(SCDesc.EndGroup);
+  NewIS->setRetireOOO(SCDesc.RetireOOO);
+
   // Check if this is a dependency breaking instruction.
   APInt Mask;
 
   bool IsZeroIdiom = false;
   bool IsDepBreaking = false;
   if (MCIA) {
     unsigned ProcID = STI.getSchedModel().getProcessorID();
     IsZeroIdiom = MCIA->isZeroIdiom(MCI, Mask, ProcID);

llvm/lib/MCA/Stages/DispatchStage.cpp

bool DispatchStage::canDispatch(const InstRef &IR) const {
   CanDispatch &= checkPRF(IR);
   CanDispatch &= checkNextStage(IR);
   return CanDispatch;
 }
 
 Error DispatchStage::dispatch(InstRef IR) {
   assert(!CarryOver && "Cannot dispatch another instruction!");
   Instruction &IS = *IR.getInstruction();
-  const InstrDesc &Desc = IS.getDesc();
   const unsigned NumMicroOps = IS.getNumMicroOps();
   if (NumMicroOps > DispatchWidth) {
     assert(AvailableEntries == DispatchWidth);
     AvailableEntries = 0;
     CarryOver = NumMicroOps - DispatchWidth;
     CarriedOver = IR;
   } else {
     assert(AvailableEntries >= NumMicroOps);
     AvailableEntries -= NumMicroOps;
   }
 
   // Check if this instructions ends the dispatch group.
-  if (Desc.EndGroup)
+  if (IS.getEndGroup())
     AvailableEntries = 0;
 
   // Check if this is an optimizable reg-reg move or an XCHG-like instruction.
   if (IS.isOptimizableMove())
     if (PRF.tryEliminateMoveOrSwap(IS.getDefs(), IS.getUses()))
       IS.setEliminated();
 
   // A dependency-breaking instruction doesn't have to wait on the register
bool DispatchStage::isAvailable(const InstRef &IR) const {
 
   const Instruction &Inst = *IR.getInstruction();
   unsigned NumMicroOps = Inst.getNumMicroOps();
   const InstrDesc &Desc = Inst.getDesc();
   unsigned Required = std::min(NumMicroOps, DispatchWidth);
   if (Required > AvailableEntries)
     return false;
 
-  if (Desc.BeginGroup && AvailableEntries != DispatchWidth)
+  if (Inst.getBeginGroup() && AvailableEntries != DispatchWidth)
     return false;
 
   // The dispatch logic doesn't internally buffer instructions.  It only accepts
   // instructions that can be successfully moved to the next stage during this
   // same cycle.
   return canDispatch(IR);
 }
 

llvm/lib/MCA/Stages/ExecuteStage.cpp

 #ifndef NDEBUG
 static void verifyInstructionEliminated(const InstRef &IR) {
   const Instruction &Inst = *IR.getInstruction();
   assert(Inst.isEliminated() && "Instruction was not eliminated!");
   assert(Inst.isReady() && "Instruction in an inconsistent state!");
 
   // Ensure that instructions eliminated at register renaming stage are in a
   // consistent state.
-  const InstrDesc &Desc = Inst.getDesc();
-  assert(!Desc.MayLoad && !Desc.MayStore && "Cannot eliminate a memory op!");
+  assert(!Inst.getMayLoad() && !Inst.getMayStore() &&
+         "Cannot eliminate a memory op!");
 }
 #endif
 
 Error ExecuteStage::handleInstructionEliminated(InstRef &IR) {
 #ifndef NDEBUG
   verifyInstructionEliminated(IR);
 #endif
   notifyInstructionPending(IR);

llvm/lib/MCA/Stages/InOrderIssueStage.cpp

 }
 
 bool InOrderIssueStage::isAvailable(const InstRef &IR) const {
   if (SI.isValid() || CarriedOver)
     return false;
 
   const Instruction &Inst = *IR.getInstruction();
   unsigned NumMicroOps = Inst.getNumMicroOps();
-  const InstrDesc &Desc = Inst.getDesc();
 
   bool ShouldCarryOver = NumMicroOps > getIssueWidth();
   if (Bandwidth < NumMicroOps && !ShouldCarryOver)
     return false;
 
   // Instruction with BeginGroup must be the first instruction to be issued in a
   // cycle.
-  if (Desc.BeginGroup && NumIssued != 0)
+  if (Inst.getBeginGroup() && NumIssued != 0)
     return false;
 
   return true;
 }
 
 static bool hasResourceHazard(const ResourceManager &RM, const InstRef &IR) {
   if (RM.checkAvailability(IR.getInstruction()->getDesc())) {
     LLVM_DEBUG(dbgs() << "[E] Stall #" << IR << '\n');
bool InOrderIssueStage::canExecute(const InstRef &IR) {
   }
 
   if (unsigned CustomStallCycles = CB.checkCustomHazard(IssuedInst, IR)) {
     SI.update(IR, CustomStallCycles, StallInfo::StallKind::CUSTOM_STALL);
     return false;
   }
 
   if (LastWriteBackCycle) {
-    if (!IR.getInstruction()->getDesc().RetireOOO) {
+    if (!IR.getInstruction()->getRetireOOO()) {
       unsigned NextWriteBackCycle = findFirstWriteBackCycle(IR);
       // Delay the instruction to ensure that writes happen in program order.
       if (NextWriteBackCycle < LastWriteBackCycle) {
         SI.update(IR, LastWriteBackCycle - NextWriteBackCycle,
                   StallInfo::StallKind::DELAY);
         return false;
       }
     }
llvm::Error InOrderIssueStage::tryIssue(InstRef &IR) {
   if (ShouldCarryOver) {
     CarryOver = NumMicroOps - Bandwidth;
     CarriedOver = IR;
     Bandwidth = 0;
     NumIssued += Bandwidth;
     LLVM_DEBUG(dbgs() << "[N] Carry over #" << IR << " \n");
   } else {
     NumIssued += NumMicroOps;
-    Bandwidth = Desc.EndGroup ? 0 : Bandwidth - NumMicroOps;
+    Bandwidth = IS.getEndGroup() ? 0 : Bandwidth - NumMicroOps;
   }
 
   // If the instruction has a latency of 0, we need to handle
   // the execution and retirement now.
   if (IS.isExecuted()) {
     PRF.onInstructionExecuted(&IS);
     LSU.onInstructionExecuted(IR);
     notifyEvent<HWInstructionEvent>(
         HWInstructionEvent(HWInstructionEvent::Executed, IR));
     LLVM_DEBUG(dbgs() << "[E] Instruction #" << IR << " is executed\n");
 
     retireInstruction(IR);
     return llvm::ErrorSuccess();
   }
 
   IssuedInst.push_back(IR);
 
-  if (!IR.getInstruction()->getDesc().RetireOOO)
+  if (!IR.getInstruction()->getRetireOOO())
     LastWriteBackCycle = IS.getCyclesLeft();
 
   return llvm::ErrorSuccess();
 }
 
 void InOrderIssueStage::updateIssuedInst() {
   // Update other instructions. Executed instructions will be retired during the
   // next cycle.
if (CarryOver > Bandwidth) {
     Bandwidth = 0;
     LLVM_DEBUG(dbgs() << "[N] Carry over (" << CarryOver << "uops left) #"
                       << CarriedOver << " \n");
     return;
   }
 
   LLVM_DEBUG(dbgs() << "[N] Carry over (complete) #" << CarriedOver << " \n");
 
-  if (CarriedOver.getInstruction()->getDesc().EndGroup)
+  if (CarriedOver.getInstruction()->getEndGroup())
     Bandwidth = 0;
   else
     Bandwidth -= CarryOver;
 
   CarriedOver = InstRef();
   CarryOver = 0;
 }
 

llvm/tools/llvm-mca/Views/SchedulerStatistics.cpp

 // making assumptions on how LSUnit internally works (See PR39828).
 void SchedulerStatistics::onEvent(const HWInstructionEvent &Event) {
   if (Event.Type == HWInstructionEvent::Issued) {
     const Instruction &Inst = *Event.IR.getInstruction();
     NumIssued += Inst.getDesc().NumMicroOps;
   } else if (Event.Type == HWInstructionEvent::Dispatched) {
     const Instruction &Inst = *Event.IR.getInstruction();
     const unsigned Index = Event.IR.getSourceIndex();
-    if (LQResourceID && Inst.getDesc().MayLoad &&
+    if (LQResourceID && Inst.getMayLoad() &&
         MostRecentLoadDispatched != Index) {
       Usage[LQResourceID].SlotsInUse++;
       MostRecentLoadDispatched = Index;
     }
-    if (SQResourceID && Inst.getDesc().MayStore &&
+    if (SQResourceID && Inst.getMayStore() &&
         MostRecentStoreDispatched != Index) {
       Usage[SQResourceID].SlotsInUse++;
       MostRecentStoreDispatched = Index;
     }
   } else if (Event.Type == HWInstructionEvent::Executed) {
     const Instruction &Inst = *Event.IR.getInstruction();
-    if (LQResourceID && Inst.getDesc().MayLoad) {
+    if (LQResourceID && Inst.getMayLoad()) {
       assert(Usage[LQResourceID].SlotsInUse);
       Usage[LQResourceID].SlotsInUse--;
     }
-    if (SQResourceID && Inst.getDesc().MayStore) {
+    if (SQResourceID && Inst.getMayStore()) {
       assert(Usage[SQResourceID].SlotsInUse);
       Usage[SQResourceID].SlotsInUse--;
     }
   }
 }
 
 void SchedulerStatistics::onReservedBuffers(const InstRef & /* unused */,
                                             ArrayRef<unsigned> Buffers) {

llvm/tools/llvm-mca/llvm-mca.cpp

int main(int argc, char **argv) {
 
   // Set the display preference for hex vs. decimal immediates.
   IP->setPrintImmHex(PrintImmHex);
 
   std::unique_ptr<ToolOutputFile> TOF = std::move(*OF);
 
   const MCSchedModel &SM = STI->getSchedModel();
 
+  std::unique_ptr<mca::InstrPostProcess> IPP;
+  if (!DisableCustomBehaviour) {
+    // TODO: It may be a good idea to separate CB and IPP so that they can
+    // be used independently of each other. What I mean by this is to add
+    // an extra command-line arg --disable-ipp so that CB and IPP can be
+    // toggled without needing to toggle both of them together.
+    IPP = std::unique_ptr<mca::InstrPostProcess>(
+        TheTarget->createInstrPostProcess(*STI, *MCII));
+  }
+  if (!IPP) {
+    // If the target doesn't have its own IPP implemented (or the -disable-cb
+    // flag is set) then we use the base class (which does nothing).
+    IPP = std::make_unique<mca::InstrPostProcess>(*STI, *MCII);
+  }
+
   // Create an instruction builder.
   mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get());
 
   // Create a context to control ownership of the pipeline hardware.
   mca::Context MCA(*MRI, *STI);
 
   mca::PipelineOptions PO(MicroOpQueue, DecoderThroughput, DispatchWidth,
                           RegisterFileSize, LoadQueueSize, StoreQueueSize,
if (Region->empty())
       continue;
 
     IB.clear();
 
     // Lower the MCInst sequence into an mca::Instruction sequence.
     ArrayRef<MCInst> Insts = Region->getInstructions();
     mca::CodeEmitter CE(*STI, *MAB, *MCE, Insts);
 
-    std::unique_ptr<mca::InstrPostProcess> IPP;
-    if (!DisableCustomBehaviour) {
-      IPP = std::unique_ptr<mca::InstrPostProcess>(
-          TheTarget->createInstrPostProcess(*STI, *MCII));
-    }
-    if (!IPP)
-      // If the target doesn't have its own IPP implemented (or the
-      // -disable-cb flag is set) then we use the base class
-      // (which does nothing).
-      IPP = std::make_unique<mca::InstrPostProcess>(*STI, *MCII);
+    IPP->resetState();
 
     SmallVector<std::unique_ptr<mca::Instruction>> LoweredSequence;
     for (const MCInst &MCI : Insts) {
       Expected<std::unique_ptr<mca::Instruction>> Inst =
           IB.createInstruction(MCI);
       if (!Inst) {
         if (auto NewE = handleErrors(
                 Inst.takeError(),
                 [&IP, &STI](const mca::InstructionError<MCInst> &IE) {