[X86] combineCMP - peek through zero-extensions for X86cmp(zext(x0),0) zero tests (PR38960)

[RKSimon]

Summary

If we're comparing a value against zero, strip away any zero-extension and perform the comparison on the pre-extended value

[pengfei]

Good point!

llvm/lib/Target/X86/X86ISelLowering.cpp

if (ShAmt.ult(BitWidth)) { // Avoid undefined shifts.
         Op = DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0),
                          DAG.getConstant(Mask, dl, VT));
         return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
                            DAG.getConstant(0, dl, VT));
       }
     }
   }
 
+  // Peek through any zero-extend if we're only testing for a zero result.
+  if (Op.getOpcode() == ISD::ZERO_EXTEND && onlyZeroFlagUsed(SDValue(N, 0))) {
+    SDValue Src = Op.getOperand(0);
+    EVT SrcVT = Src.getValueType();
+    if (SrcVT.getScalarSizeInBits() >= 8 &&
+        DAG.getTargetLoweringInfo().isTypeLegal(SrcVT))
+      return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Src,
+                         DAG.getConstant(0, dl, SrcVT));
+  }
+
   // Look for a truncate.
   if (Op.getOpcode() != ISD::TRUNCATE)
     return SDValue();
 
   SDValue Trunc = Op;
   Op = Op.getOperand(0);
 
   // See if we can compare with zero against the truncation source,

llvm/test/CodeGen/X86/comi-flags.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefix=SSE
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx  | FileCheck %s --check-prefix=AVX
 
 ;
 ; SSE
 ;
 
 define i32 @test_x86_sse_comieq_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
 ; SSE-LABEL: test_x86_sse_comieq_ss:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    movl %edi, %eax
 ; SSE-NEXT:    comiss %xmm1, %xmm0
 ; SSE-NEXT:    setnp %cl
 ; SSE-NEXT:    sete %dl
-; SSE-NEXT:    andb %cl, %dl
-; SSE-NEXT:    movzbl %dl, %ecx
-; SSE-NEXT:    testl %ecx, %ecx
+; SSE-NEXT:    testb %cl, %dl
 ; SSE-NEXT:    cmovnel %esi, %eax
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test_x86_sse_comieq_ss:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    movl %edi, %eax
 ; AVX-NEXT:    vcomiss %xmm1, %xmm0
 ; AVX-NEXT:    setnp %cl
 ; AVX-NEXT:    sete %dl
-; AVX-NEXT:    andb %cl, %dl
-; AVX-NEXT:    movzbl %dl, %ecx
-; AVX-NEXT:    testl %ecx, %ecx
+; AVX-NEXT:    testb %cl, %dl
 ; AVX-NEXT:    cmovnel %esi, %eax
 ; AVX-NEXT:    retq
   %call = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1)
   %cmp = icmp eq i32 %call, 0
   %res = select i1 %cmp, i32 %a2, i32 %a3
   ret i32 %res
 }
 declare i32 @llvm.x86.sse.comieq.ss(<4 x float>, <4 x float>) nounwind readnone
; AVX-NEXT:    retq
   %res = select i1 %cmp, i32 %a2, i32 %a3
   ret i32 %res
 }
 declare i32 @llvm.x86.sse.comilt.ss(<4 x float>, <4 x float>) nounwind readnone
 
 define i32 @test_x86_sse_comineq_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
 ; SSE-LABEL: test_x86_sse_comineq_ss:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    movl %edi, %eax
+; SSE-NEXT:    movl %esi, %eax
 ; SSE-NEXT:    comiss %xmm1, %xmm0
-; SSE-NEXT:    setp %cl
-; SSE-NEXT:    setne %dl
-; SSE-NEXT:    orb %cl, %dl
-; SSE-NEXT:    movzbl %dl, %ecx
-; SSE-NEXT:    testl %ecx, %ecx
-; SSE-NEXT:    cmovel %esi, %eax
+; SSE-NEXT:    cmovnel %edi, %eax
+; SSE-NEXT:    cmovpl %edi, %eax
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test_x86_sse_comineq_ss:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    movl %edi, %eax
+; AVX-NEXT:    movl %esi, %eax
 ; AVX-NEXT:    vcomiss %xmm1, %xmm0
-; AVX-NEXT:    setp %cl
-; AVX-NEXT:    setne %dl
-; AVX-NEXT:    orb %cl, %dl
-; AVX-NEXT:    movzbl %dl, %ecx
-; AVX-NEXT:    testl %ecx, %ecx
-; AVX-NEXT:    cmovel %esi, %eax
+; AVX-NEXT:    cmovnel %edi, %eax
+; AVX-NEXT:    cmovpl %edi, %eax
 ; AVX-NEXT:    retq
   %call = call i32 @llvm.x86.sse.comineq.ss(<4 x float> %a0, <4 x float> %a1)
   %cmp = icmp ne i32 %call, 0
   %res = select i1 %cmp, i32 %a2, i32 %a3
   ret i32 %res
 }
 declare i32 @llvm.x86.sse.comineq.ss(<4 x float>, <4 x float>) nounwind readnone
 
 define i32 @test_x86_sse_ucomieq_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
 ; SSE-LABEL: test_x86_sse_ucomieq_ss:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    movl %edi, %eax
 ; SSE-NEXT:    ucomiss %xmm1, %xmm0
 ; SSE-NEXT:    setnp %cl
 ; SSE-NEXT:    sete %dl
-; SSE-NEXT:    andb %cl, %dl
-; SSE-NEXT:    movzbl %dl, %ecx
-; SSE-NEXT:    testl %ecx, %ecx
+; SSE-NEXT:    testb %cl, %dl
 ; SSE-NEXT:    cmovnel %esi, %eax
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test_x86_sse_ucomieq_ss:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    movl %edi, %eax
 ; AVX-NEXT:    vucomiss %xmm1, %xmm0
 ; AVX-NEXT:    setnp %cl
 ; AVX-NEXT:    sete %dl
-; AVX-NEXT:    andb %cl, %dl
-; AVX-NEXT:    movzbl %dl, %ecx
-; AVX-NEXT:    testl %ecx, %ecx
+; AVX-NEXT:    testb %cl, %dl
 ; AVX-NEXT:    cmovnel %esi, %eax
 ; AVX-NEXT:    retq
   %call = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1)
   %cmp = icmp eq i32 %call, 0
   %res = select i1 %cmp, i32 %a2, i32 %a3
   ret i32 %res
 }
 declare i32 @llvm.x86.sse.ucomieq.ss(<4 x float>, <4 x float>) nounwind readnone
; AVX-NEXT:    retq
   %res = select i1 %cmp, i32 %a2, i32 %a3
   ret i32 %res
 }
 declare i32 @llvm.x86.sse.ucomilt.ss(<4 x float>, <4 x float>) nounwind readnone
 
 define i32 @test_x86_sse_ucomineq_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
 ; SSE-LABEL: test_x86_sse_ucomineq_ss:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    movl %edi, %eax
+; SSE-NEXT:    movl %esi, %eax
 ; SSE-NEXT:    ucomiss %xmm1, %xmm0
-; SSE-NEXT:    setp %cl
-; SSE-NEXT:    setne %dl
-; SSE-NEXT:    orb %cl, %dl
-; SSE-NEXT:    movzbl %dl, %ecx
-; SSE-NEXT:    testl %ecx, %ecx
-; SSE-NEXT:    cmovel %esi, %eax
+; SSE-NEXT:    cmovnel %edi, %eax
+; SSE-NEXT:    cmovpl %edi, %eax
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test_x86_sse_ucomineq_ss:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    movl %edi, %eax
+; AVX-NEXT:    movl %esi, %eax
 ; AVX-NEXT:    vucomiss %xmm1, %xmm0
-; AVX-NEXT:    setp %cl
-; AVX-NEXT:    setne %dl
-; AVX-NEXT:    orb %cl, %dl
-; AVX-NEXT:    movzbl %dl, %ecx
-; AVX-NEXT:    testl %ecx, %ecx
-; AVX-NEXT:    cmovel %esi, %eax
+; AVX-NEXT:    cmovnel %edi, %eax
+; AVX-NEXT:    cmovpl %edi, %eax
 ; AVX-NEXT:    retq
   %call = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %a0, <4 x float> %a1)
   %cmp = icmp ne i32 %call, 0
   %res = select i1 %cmp, i32 %a2, i32 %a3
   ret i32 %res
 }
 declare i32 @llvm.x86.sse.ucomineq.ss(<4 x float>, <4 x float>) nounwind readnone
 
 ;
 ; SSE2
 ;
 
 define i32 @test_x86_sse2_comieq_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
 ; SSE-LABEL: test_x86_sse2_comieq_sd:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    movl %edi, %eax
 ; SSE-NEXT:    comisd %xmm1, %xmm0
 ; SSE-NEXT:    setnp %cl
 ; SSE-NEXT:    sete %dl
-; SSE-NEXT:    andb %cl, %dl
-; SSE-NEXT:    movzbl %dl, %ecx
-; SSE-NEXT:    testl %ecx, %ecx
+; SSE-NEXT:    testb %cl, %dl
 ; SSE-NEXT:    cmovnel %esi, %eax
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test_x86_sse2_comieq_sd:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    movl %edi, %eax
 ; AVX-NEXT:    vcomisd %xmm1, %xmm0
 ; AVX-NEXT:    setnp %cl
 ; AVX-NEXT:    sete %dl
-; AVX-NEXT:    andb %cl, %dl
-; AVX-NEXT:    movzbl %dl, %ecx
-; AVX-NEXT:    testl %ecx, %ecx
+; AVX-NEXT:    testb %cl, %dl
 ; AVX-NEXT:    cmovnel %esi, %eax
 ; AVX-NEXT:    retq
   %call = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   %cmp = icmp eq i32 %call, 0
   %res = select i1 %cmp, i32 %a2, i32 %a3
   ret i32 %res
 }
 declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnone
; AVX-NEXT:    retq
   %res = select i1 %cmp, i32 %a2, i32 %a3
   ret i32 %res
 }
 declare i32 @llvm.x86.sse2.comilt.sd(<2 x double>, <2 x double>) nounwind readnone
 
 define i32 @test_x86_sse2_comineq_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
 ; SSE-LABEL: test_x86_sse2_comineq_sd:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    movl %edi, %eax
+; SSE-NEXT:    movl %esi, %eax
 ; SSE-NEXT:    comisd %xmm1, %xmm0
-; SSE-NEXT:    setp %cl
-; SSE-NEXT:    setne %dl
-; SSE-NEXT:    orb %cl, %dl
-; SSE-NEXT:    movzbl %dl, %ecx
-; SSE-NEXT:    testl %ecx, %ecx
-; SSE-NEXT:    cmovel %esi, %eax
+; SSE-NEXT:    cmovnel %edi, %eax
+; SSE-NEXT:    cmovpl %edi, %eax
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test_x86_sse2_comineq_sd:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    movl %edi, %eax
+; AVX-NEXT:    movl %esi, %eax
 ; AVX-NEXT:    vcomisd %xmm1, %xmm0
-; AVX-NEXT:    setp %cl
-; AVX-NEXT:    setne %dl
-; AVX-NEXT:    orb %cl, %dl
-; AVX-NEXT:    movzbl %dl, %ecx
-; AVX-NEXT:    testl %ecx, %ecx
-; AVX-NEXT:    cmovel %esi, %eax
+; AVX-NEXT:    cmovnel %edi, %eax
+; AVX-NEXT:    cmovpl %edi, %eax
 ; AVX-NEXT:    retq
   %call = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   %cmp = icmp ne i32 %call, 0
   %res = select i1 %cmp, i32 %a2, i32 %a3
   ret i32 %res
 }
 declare i32 @llvm.x86.sse2.comineq.sd(<2 x double>, <2 x double>) nounwind readnone
 
 define i32 @test_x86_sse2_ucomieq_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
 ; SSE-LABEL: test_x86_sse2_ucomieq_sd:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    movl %edi, %eax
 ; SSE-NEXT:    ucomisd %xmm1, %xmm0
 ; SSE-NEXT:    setnp %cl
 ; SSE-NEXT:    sete %dl
-; SSE-NEXT:    andb %cl, %dl
-; SSE-NEXT:    movzbl %dl, %ecx
-; SSE-NEXT:    testl %ecx, %ecx
+; SSE-NEXT:    testb %cl, %dl
 ; SSE-NEXT:    cmovnel %esi, %eax
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test_x86_sse2_ucomieq_sd:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    movl %edi, %eax
 ; AVX-NEXT:    vucomisd %xmm1, %xmm0
 ; AVX-NEXT:    setnp %cl
 ; AVX-NEXT:    sete %dl
-; AVX-NEXT:    andb %cl, %dl
-; AVX-NEXT:    movzbl %dl, %ecx
-; AVX-NEXT:    testl %ecx, %ecx
+; AVX-NEXT:    testb %cl, %dl
 ; AVX-NEXT:    cmovnel %esi, %eax
 ; AVX-NEXT:    retq
   %call = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   %cmp = icmp eq i32 %call, 0
   %res = select i1 %cmp, i32 %a2, i32 %a3
   ret i32 %res
 }
 declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>) nounwind readnone
; AVX-NEXT:    retq
   %res = select i1 %cmp, i32 %a2, i32 %a3
   ret i32 %res
 }
 declare i32 @llvm.x86.sse2.ucomilt.sd(<2 x double>, <2 x double>) nounwind readnone
 
 define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
 ; SSE-LABEL: test_x86_sse2_ucomineq_sd:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    movl %edi, %eax
+; SSE-NEXT:    movl %esi, %eax
 ; SSE-NEXT:    ucomisd %xmm1, %xmm0
-; SSE-NEXT:    setp %cl
-; SSE-NEXT:    setne %dl
-; SSE-NEXT:    orb %cl, %dl
-; SSE-NEXT:    movzbl %dl, %ecx
-; SSE-NEXT:    testl %ecx, %ecx
-; SSE-NEXT:    cmovel %esi, %eax
+; SSE-NEXT:    cmovnel %edi, %eax
+; SSE-NEXT:    cmovpl %edi, %eax
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: test_x86_sse2_ucomineq_sd:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    movl %edi, %eax
+; AVX-NEXT:    movl %esi, %eax
 ; AVX-NEXT:    vucomisd %xmm1, %xmm0
-; AVX-NEXT:    setp %cl
-; AVX-NEXT:    setne %dl
-; AVX-NEXT:    orb %cl, %dl
-; AVX-NEXT:    movzbl %dl, %ecx
-; AVX-NEXT:    testl %ecx, %ecx
-; AVX-NEXT:    cmovel %esi, %eax
+; AVX-NEXT:    cmovnel %edi, %eax
+; AVX-NEXT:    cmovpl %edi, %eax
 ; AVX-NEXT:    retq
   %call = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
   %cmp = icmp ne i32 %call, 0
   %res = select i1 %cmp, i32 %a2, i32 %a3
   ret i32 %res
 }
 declare i32 @llvm.x86.sse2.ucomineq.sd(<2 x double>, <2 x double>) nounwind readnone
 
 define void @PR38960_eq(<4 x float> %A, <4 x float> %B) {
 ; SSE-LABEL: PR38960_eq:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    comiss %xmm1, %xmm0
 ; SSE-NEXT:    setnp %al
 ; SSE-NEXT:    sete %cl
-; SSE-NEXT:    andb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
-; SSE-NEXT:    testl %eax, %eax
+; SSE-NEXT:    testb %al, %cl
 ; SSE-NEXT:    je .LBB24_1
 ; SSE-NEXT:  # %bb.2: # %if.then
 ; SSE-NEXT:    jmp foo@PLT # TAILCALL
 ; SSE-NEXT:  .LBB24_1: # %if.end
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: PR38960_eq:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vcomiss %xmm1, %xmm0
 ; AVX-NEXT:    setnp %al
 ; AVX-NEXT:    sete %cl
-; AVX-NEXT:    andb %al, %cl
-; AVX-NEXT:    movzbl %cl, %eax
-; AVX-NEXT:    testl %eax, %eax
+; AVX-NEXT:    testb %al, %cl
 ; AVX-NEXT:    je .LBB24_1
 ; AVX-NEXT:  # %bb.2: # %if.then
 ; AVX-NEXT:    jmp foo@PLT # TAILCALL
 ; AVX-NEXT:  .LBB24_1: # %if.end
 ; AVX-NEXT:    retq
 entry:
   %call = tail call i32 @llvm.x86.sse.comieq.ss(<4 x float> %A, <4 x float> %B) #3
   %cmp = icmp eq i32 %call, 0

 
 define void @PR38960_neq(<4 x float> %A, <4 x float> %B) {
 ; SSE-LABEL: PR38960_neq:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    comiss %xmm1, %xmm0
 ; SSE-NEXT:    setp %al
 ; SSE-NEXT:    setne %cl
 ; SSE-NEXT:    orb %al, %cl
-; SSE-NEXT:    movzbl %cl, %eax
-; SSE-NEXT:    testl %eax, %eax
 ; SSE-NEXT:    je .LBB25_1
 ; SSE-NEXT:  # %bb.2: # %if.then
 ; SSE-NEXT:    jmp foo@PLT # TAILCALL
 ; SSE-NEXT:  .LBB25_1: # %if.end
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: PR38960_neq:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vcomiss %xmm1, %xmm0
 ; AVX-NEXT:    setp %al
 ; AVX-NEXT:    setne %cl
 ; AVX-NEXT:    orb %al, %cl
-; AVX-NEXT:    movzbl %cl, %eax
-; AVX-NEXT:    testl %eax, %eax
 ; AVX-NEXT:    je .LBB25_1
 ; AVX-NEXT:  # %bb.2: # %if.then
 ; AVX-NEXT:    jmp foo@PLT # TAILCALL
 ; AVX-NEXT:  .LBB25_1: # %if.end
 ; AVX-NEXT:    retq
 entry:
   %call = tail call i32 @llvm.x86.sse.comineq.ss(<4 x float> %A, <4 x float> %B) #3
   %cmp = icmp eq i32 %call, 0