[X86] convertIntLogicToFPLogic - enable fp-logic on pre-AVX targets for supported fp predicates (PR34563)

[RKSimon]

Summary

If the SETCC fp-condcode is supported on SSE as a single CMPPS/PD op then we can use convertIntLogicToFPLogic to reduce EFLAGS and XMM->GPR traffic like we do for AVX targets.

[pengfei]

llvm/lib/Target/X86/X86ISelLowering.cpp

46823–46825

What will we do if they are swapped? I don't see we use it else where.

46829–46830

Move the comments on line 46820 here?

[RKSimon]

move comment

[spatel]

llvm/lib/Target/X86/X86ISelLowering.cpp

46826

Make that a single "Unused" bool variable for readability? Or see next comment for an alternate change.

46829

Instead of an ambiguous "8", can we spell this out to make the limitation clear?

IIUC, this is what we want to avoid:

if (CC0 == ISD::SETONE || CC1 == ISD::SETONE ||
    CC0 == ISD::SETUEQ || CC1 == ISD::SETUEQ)

I see one other place in this file that uses this condition:

// In the two cases not handled by SSE compare predicates (SETUEQ/SETONE),
// emit two comparisons and a logic op to tie them together.

So we could create a small helper function to make both of these cases more obvious.

[RKSimon]

Avoid translateX86FSETCC call

[RKSimon]

Add cheapX86FSETCC_SSE helper - if we want to use this I'll pre-commit the helper

[spatel]

LGTM

llvm/lib/Target/X86/X86ISelLowering.cpp

   if (Src.getValueType() != BitNo.getValueType())
     BitNo = DAG.getNode(ISD::ANY_EXTEND, dl, Src.getValueType(), BitNo);
 
   X86CC = DAG.getTargetConstant(CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B,
                                 dl, MVT::i8);
   return DAG.getNode(X86ISD::BT, dl, MVT::i32, Src, BitNo);
 }
 
+// Check if pre-AVX condcode can be performed by a single FCMP op.
+static bool cheapX86FSETCC_SSE(ISD::CondCode SetCCOpcode) {
+  return (SetCCOpcode != ISD::SETONE) && (SetCCOpcode != ISD::SETUEQ);
+}
+
 /// Turns an ISD::CondCode into a value suitable for SSE floating-point mask
 /// CMPs.
 static unsigned translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
                                    SDValue &Op1, bool &IsAlwaysSignaling) {
   unsigned SSECC;
   bool Swap = false;
 
   // SSE Condition code mapping:

         // NoFPExcept = false by default. However, I didn't find it in other
         // patches.
         SignalCmp->setFlags(Op->getFlags());
         Chain = SignalCmp.getValue(1);
       }
 
       // In the two cases not handled by SSE compare predicates (SETUEQ/SETONE),
       // emit two comparisons and a logic op to tie them together.
-      if (SSECC >= 8) {
+      if (!cheapX86FSETCC_SSE(Cond)) {
         // LLVM predicate is SETUEQ or SETONE.
         unsigned CC0, CC1;
         unsigned CombineOpc;
         if (Cond == ISD::SETUEQ) {
           CC0 = 3; // UNORD
           CC1 = 0; // EQ
           CombineOpc = X86ISD::FOR;
         } else {

     return SDValue();
 
   if (N0.getOpcode() == ISD::BITCAST && !DCI.isBeforeLegalizeOps()) {
     unsigned FPOpcode = convertIntLogicToFPLogicOpcode(N->getOpcode());
     SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
     return DAG.getBitcast(VT, FPLogic);
   }
 
-  // The vector ISA for FP predicates is incomplete before AVX, so converting
-  // COMIS* to CMPS* may not be a win before AVX.
-  // TODO: Check types/predicates to see if they are available with SSE/SSE2.
-  if (!Subtarget.hasAVX() || VT != MVT::i1 || N0.getOpcode() != ISD::SETCC ||
-      !N0.hasOneUse() || !N1.hasOneUse())
+  if (VT != MVT::i1 || N0.getOpcode() != ISD::SETCC || !N0.hasOneUse() ||
+      !N1.hasOneUse())
     return SDValue();
 
   ISD::CondCode CC0 = cast<CondCodeSDNode>(N0.getOperand(2))->get();
   ISD::CondCode CC1 = cast<CondCodeSDNode>(N1.getOperand(2))->get();
 
+  // The vector ISA for FP predicates is incomplete before AVX, so converting
+  // COMIS* to CMPS* may not be a win before AVX.
+  if (!Subtarget.hasAVX() &&
+      !(cheapX86FSETCC_SSE(CC0) && cheapX86FSETCC_SSE(CC1)))
+    return SDValue();
+
   // Convert scalar FP compares and logic to vector compares (COMIS* to CMPS*)
   // and vector logic:
   // logic (setcc N00, N01), (setcc N10, N11) -->
   // extelt (logic (setcc (s2v N00), (s2v N01)), setcc (s2v N10), (s2v N11))), 0
   unsigned NumElts = 128 / N00Type.getSizeInBits();
   EVT VecVT = EVT::getVectorVT(*DAG.getContext(), N00Type, NumElts);
   EVT BoolVecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElts);
   SDValue ZeroIndex = DAG.getVectorIdxConstant(0, DL);
   SDValue N01 = N0.getOperand(1);
   SDValue N11 = N1.getOperand(1);

llvm/test/CodeGen/X86/fcmp-logic.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=sse2    | FileCheck %s --check-prefixes=SSE2
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=avx     | FileCheck %s --check-prefixes=AVX,AVX1
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=avx512f | FileCheck %s --check-prefixes=AVX,AVX512
 
 define i1 @olt_ole_and_f32(float %w, float %x, float %y, float %z) {
 ; SSE2-LABEL: olt_ole_and_f32:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    ucomiss %xmm0, %xmm1
-; SSE2-NEXT:    seta %cl
-; SSE2-NEXT:    ucomiss %xmm2, %xmm3
-; SSE2-NEXT:    setae %al
-; SSE2-NEXT:    andb %cl, %al
+; SSE2-NEXT:    cmpleps %xmm3, %xmm2
+; SSE2-NEXT:    cmpltps %xmm1, %xmm0
+; SSE2-NEXT:    andps %xmm2, %xmm0
+; SSE2-NEXT:    movd %xmm0, %eax
+; SSE2-NEXT:    # kill: def $al killed $al killed $eax
 ; SSE2-NEXT:    retq
 ;
 ; AVX1-LABEL: olt_ole_and_f32:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vcmpleps %xmm3, %xmm2, %xmm2
 ; AVX1-NEXT:    vcmpltps %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    vandps %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vmovd %xmm0, %eax
; AVX512-NEXT:    retq
   %f2 = fcmp ole float %y, %z
   %r = and i1 %f1, %f2
   ret i1 %r
 }
 
 define i1 @oge_oeq_or_f32(float %w, float %x, float %y, float %z) {
 ; SSE2-LABEL: oge_oeq_or_f32:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    ucomiss %xmm1, %xmm0
-; SSE2-NEXT:    setae %cl
-; SSE2-NEXT:    ucomiss %xmm3, %xmm2
-; SSE2-NEXT:    setnp %dl
-; SSE2-NEXT:    sete %al
-; SSE2-NEXT:    andb %dl, %al
-; SSE2-NEXT:    orb %cl, %al
+; SSE2-NEXT:    cmpeqps %xmm3, %xmm2
+; SSE2-NEXT:    cmpleps %xmm0, %xmm1
+; SSE2-NEXT:    orps %xmm2, %xmm1
+; SSE2-NEXT:    movd %xmm1, %eax
+; SSE2-NEXT:    # kill: def $al killed $al killed $eax
 ; SSE2-NEXT:    retq
 ;
 ; AVX1-LABEL: oge_oeq_or_f32:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vcmpeqps %xmm3, %xmm2, %xmm2
 ; AVX1-NEXT:    vcmpleps %xmm0, %xmm1, %xmm0
 ; AVX1-NEXT:    vorps %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vmovd %xmm0, %eax
; AVX512-NEXT:    retq
   %f2 = fcmp one float %y, %z
   %r = xor i1 %f1, %f2
   ret i1 %r
 }
 
 define i1 @une_ugt_and_f64(double %w, double %x, double %y, double %z) {
 ; SSE2-LABEL: une_ugt_and_f64:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    ucomisd %xmm1, %xmm0
-; SSE2-NEXT:    setp %al
-; SSE2-NEXT:    setne %cl
-; SSE2-NEXT:    orb %al, %cl
-; SSE2-NEXT:    ucomisd %xmm2, %xmm3
-; SSE2-NEXT:    setb %al
-; SSE2-NEXT:    andb %cl, %al
+; SSE2-NEXT:    cmpnlepd %xmm3, %xmm2
+; SSE2-NEXT:    cmpneqpd %xmm1, %xmm0
+; SSE2-NEXT:    andpd %xmm2, %xmm0
+; SSE2-NEXT:    movd %xmm0, %eax
+; SSE2-NEXT:    # kill: def $al killed $al killed $eax
 ; SSE2-NEXT:    retq
 ;
 ; AVX1-LABEL: une_ugt_and_f64:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vcmpnlepd %xmm3, %xmm2, %xmm2
 ; AVX1-NEXT:    vcmpneqpd %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    vandpd %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vmovd %xmm0, %eax
; AVX512-NEXT:    retq
   %f2 = fcmp ugt double %y, %z
   %r = and i1 %f1, %f2
   ret i1 %r
 }
 
 define i1 @ult_uge_or_f64(double %w, double %x, double %y, double %z) {
 ; SSE2-LABEL: ult_uge_or_f64:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    ucomisd %xmm1, %xmm0
-; SSE2-NEXT:    setb %cl
-; SSE2-NEXT:    ucomisd %xmm2, %xmm3
-; SSE2-NEXT:    setbe %al
-; SSE2-NEXT:    orb %cl, %al
+; SSE2-NEXT:    cmpnltpd %xmm3, %xmm2
+; SSE2-NEXT:    cmpnlepd %xmm0, %xmm1
+; SSE2-NEXT:    orpd %xmm2, %xmm1
+; SSE2-NEXT:    movd %xmm1, %eax
+; SSE2-NEXT:    # kill: def $al killed $al killed $eax
 ; SSE2-NEXT:    retq
 ;
 ; AVX1-LABEL: ult_uge_or_f64:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vcmpnltpd %xmm3, %xmm2, %xmm2
 ; AVX1-NEXT:    vcmpnlepd %xmm0, %xmm1, %xmm0
 ; AVX1-NEXT:    vorpd %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vmovd %xmm0, %eax
; AVX512-NEXT:    retq
   %f2 = fcmp uge double %y, %z
   %r = or i1 %f1, %f2
   ret i1 %r
 }
 
 define i1 @une_uno_xor_f64(double %w, double %x, double %y, double %z) {
 ; SSE2-LABEL: une_uno_xor_f64:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    ucomisd %xmm1, %xmm0
-; SSE2-NEXT:    setp %al
-; SSE2-NEXT:    setne %cl
-; SSE2-NEXT:    orb %al, %cl
-; SSE2-NEXT:    ucomisd %xmm3, %xmm2
-; SSE2-NEXT:    setp %al
-; SSE2-NEXT:    xorb %cl, %al
+; SSE2-NEXT:    cmpunordpd %xmm3, %xmm2
+; SSE2-NEXT:    cmpneqpd %xmm1, %xmm0
+; SSE2-NEXT:    xorpd %xmm2, %xmm0
+; SSE2-NEXT:    movd %xmm0, %eax
+; SSE2-NEXT:    # kill: def $al killed $al killed $eax
 ; SSE2-NEXT:    retq
 ;
 ; AVX1-LABEL: une_uno_xor_f64:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vcmpunordpd %xmm3, %xmm2, %xmm2
 ; AVX1-NEXT:    vcmpneqpd %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    vxorpd %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vmovd %xmm0, %eax

 ; bool f32cmp3(float x, float y, float z, float w) {
 ;     return ((x > 0) || (y > 0)) != (z < w);
 ; }
 
 define i1 @f32cmp3(float %x, float %y, float %z, float %w) {
 ; SSE2-LABEL: f32cmp3:
 ; SSE2:       # %bb.0:
 ; SSE2-NEXT:    xorps %xmm4, %xmm4
-; SSE2-NEXT:    ucomiss %xmm4, %xmm0
-; SSE2-NEXT:    seta %al
-; SSE2-NEXT:    ucomiss %xmm4, %xmm1
-; SSE2-NEXT:    seta %cl
-; SSE2-NEXT:    orb %al, %cl
+; SSE2-NEXT:    xorps %xmm5, %xmm5
+; SSE2-NEXT:    cmpltps %xmm1, %xmm5
+; SSE2-NEXT:    cmpltps %xmm0, %xmm4
+; SSE2-NEXT:    orps %xmm5, %xmm4
+; SSE2-NEXT:    movd %xmm4, %ecx
 ; SSE2-NEXT:    ucomiss %xmm2, %xmm3
 ; SSE2-NEXT:    seta %al
 ; SSE2-NEXT:    xorb %cl, %al
 ; SSE2-NEXT:    retq
 ;
 ; AVX1-LABEL: f32cmp3:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vxorps %xmm4, %xmm4, %xmm4

llvm/test/CodeGen/X86/pr40539.ll

 @fpi = external dso_local global float, align 4
 
 define zeroext i1 @_Z8test_cosv() {
 ; CHECK-LABEL: _Z8test_cosv:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    divss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
 ; CHECK-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    fcos
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    fstps (%esp)
-; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT:    ucomiss %xmm0, %xmm1
-; CHECK-NEXT:    setae %cl
-; CHECK-NEXT:    ucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
-; CHECK-NEXT:    setae %al
-; CHECK-NEXT:    andb %cl, %al
+; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT:    cmpleps %xmm1, %xmm0
+; CHECK-NEXT:    cmpleps %xmm2, %xmm1
+; CHECK-NEXT:    andps %xmm0, %xmm1
+; CHECK-NEXT:    movd %xmm1, %eax
+; CHECK-NEXT:    andb $1, %al
+; CHECK-NEXT:    # kill: def $al killed $al killed $eax
 ; CHECK-NEXT:    addl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-NEXT:    retl
 entry:
   %0 = load float, float* @fpi, align 4
   %div = fdiv float %0, 6.000000e+00
   %1 = fpext float %div to x86_fp80
   %2 = tail call x86_fp80 asm "fcos", "={st},0,~{dirflag},~{fpsr},~{flags}"(x86_fp80 %1)
   %conv = fptrunc x86_fp80 %2 to float
   %cmp = fcmp ole float %conv, 0x3FEBD70A40000000
   %cmp1 = fcmp oge float %conv, 0x3FEB851EC0000000
   %or.cond = and i1 %cmp, %cmp1
   ret i1 %or.cond
 }