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Differential D12118

[DAGCombiner] Added SMAX/SMIN/UMAX/UMIN constant folding
ClosedPublic

Authored by RKSimon on Aug 18 2015, 2:59 PM.

Details

Reviewers
spatel
andreadb
jmolloy
Commits
rG35f528262f47: [DAGCombiner] Added SMAX/SMIN/UMAX/UMIN constant folding
rL245503: [DAGCombiner] Added SMAX/SMIN/UMAX/UMIN constant folding
Summary

Added support for constant folding of SMAX/SMIN/UMAX/UMIN nodes

We still need to add constant folding of vector comparisons to fold the tests for targets that don't support the respective min/max nodes

I needed to update 2011-12-06-AVXVectorExtractCombine to load a vector instead of using a constant vector to prevent it folding

Diff Detail

Repository
rL LLVM

Event Timeline

RKSimon updated this revision to Diff 32458.Aug 18 2015, 2:59 PM
RKSimon retitled this revision from to [DAGCombiner] Added SMAX/SMIN/UMAX/UMIN constant folding.
RKSimon updated this object.
RKSimon added reviewers: jmolloy, spatel, andreadb.
RKSimon set the repository for this revision to rL LLVM.
RKSimon added a subscriber: llvm-commits.
arsenm added a subscriber: arsenm.Aug 18 2015, 3:46 PM

Where are these being produced in the first place? I would have expected these would have folded away before the min/max was created.

RKSimon added a comment.Aug 18 2015, 3:49 PM

Code using the llvm.x86.sse*.pmin* / llvm.x86.sse*.pmax* intrinsics has been the main source of them so far, but I wanted to create a general implementation if I could.

jmolloy accepted this revision.Aug 19 2015, 2:48 AM
jmolloy edited edge metadata.

This looks good from my point of view, but I haven't audited the X86 test changes!

James

This revision is now accepted and ready to land.Aug 19 2015, 2:48 AM
Closed by commit rL245503: [DAGCombiner] Added SMAX/SMIN/UMAX/UMIN constant folding (authored by RKSimon). · Explain WhyAug 19 2015, 2:12 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
include/
llvm/
CodeGen/
6 lines
lib/
CodeGen/
SelectionDAG/
29 lines
10 lines
test/
CodeGen/
X86/
13 lines
360 lines
384 lines

Diff 32617

llvm/trunk/include/llvm/CodeGen/SelectionDAG.h

Show First 20 Lines • Show All 681 Lines • ▼ Show 20 Lines#endif
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
const SDNodeFlags *Flags = nullptr); const SDNodeFlags *Flags = nullptr);
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
SDValue N3); SDValue N3);
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
SDValue N3, SDValue N4); SDValue N3, SDValue N4);
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
SDValue N3, SDValue N4, SDValue N5); SDValue N3, SDValue N4, SDValue N5);
// Specialize again based on number of operands for nodes with a VTList // Specialize again based on number of operands for nodes with a VTList
// rather than a single VT. // rather than a single VT.
SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs); SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs);
SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N); SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N);
SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1, SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,
SDValue N2); SDValue N2);
SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1, SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,
SDValue N2, SDValue N3); SDValue N2, SDValue N3);
▲ Show 20 Lines • Show All 368 Lines • ▼ Show 20 Lines#endif
} }
/// Returns true if the opcode is a commutative binary operation. /// Returns true if the opcode is a commutative binary operation.
static bool isCommutativeBinOp(unsigned Opcode) { static bool isCommutativeBinOp(unsigned Opcode) {
// FIXME: This should get its info from the td file, so that we can include // FIXME: This should get its info from the td file, so that we can include
// target info. // target info.
switch (Opcode) { switch (Opcode) {
case ISD::ADD: case ISD::ADD:
case ISD::SMIN:
case ISD::SMAX:
case ISD::UMIN:
case ISD::UMAX:
case ISD::MUL: case ISD::MUL:
case ISD::MULHU: case ISD::MULHU:
case ISD::MULHS: case ISD::MULHS:
case ISD::SMUL_LOHI: case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI: case ISD::UMUL_LOHI:
case ISD::FADD: case ISD::FADD:
case ISD::FMUL: case ISD::FMUL:
case ISD::AND: case ISD::AND:
▲ Show 20 Lines • Show All 227 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 239 Lines • ▼ Show 20 Lines private:
SDValue visitMULHU(SDNode *N); SDValue visitMULHU(SDNode *N);
SDValue visitMULHS(SDNode *N); SDValue visitMULHS(SDNode *N);
SDValue visitSMUL_LOHI(SDNode *N); SDValue visitSMUL_LOHI(SDNode *N);
SDValue visitUMUL_LOHI(SDNode *N); SDValue visitUMUL_LOHI(SDNode *N);
SDValue visitSMULO(SDNode *N); SDValue visitSMULO(SDNode *N);
SDValue visitUMULO(SDNode *N); SDValue visitUMULO(SDNode *N);
SDValue visitSDIVREM(SDNode *N); SDValue visitSDIVREM(SDNode *N);
SDValue visitUDIVREM(SDNode *N); SDValue visitUDIVREM(SDNode *N);
SDValue visitIMINMAX(SDNode *N);
SDValue visitAND(SDNode *N); SDValue visitAND(SDNode *N);
SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *LocReference); SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *LocReference);
SDValue visitOR(SDNode *N); SDValue visitOR(SDNode *N);
SDValue visitORLike(SDValue N0, SDValue N1, SDNode *LocReference); SDValue visitORLike(SDValue N0, SDValue N1, SDNode *LocReference);
SDValue visitXOR(SDNode *N); SDValue visitXOR(SDNode *N);
SDValue SimplifyVBinOp(SDNode *N); SDValue SimplifyVBinOp(SDNode *N);
SDValue visitSHL(SDNode *N); SDValue visitSHL(SDNode *N);
SDValue visitSRA(SDNode *N); SDValue visitSRA(SDNode *N);
▲ Show 20 Lines • Show All 1,080 Lines • ▼ Show 20 LinesSDValue DAGCombiner::visit(SDNode *N) {
case ISD::MULHU: return visitMULHU(N); case ISD::MULHU: return visitMULHU(N);
case ISD::MULHS: return visitMULHS(N); case ISD::MULHS: return visitMULHS(N);
case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
case ISD::SMULO: return visitSMULO(N); case ISD::SMULO: return visitSMULO(N);
case ISD::UMULO: return visitUMULO(N); case ISD::UMULO: return visitUMULO(N);
case ISD::SDIVREM: return visitSDIVREM(N); case ISD::SDIVREM: return visitSDIVREM(N);
case ISD::UDIVREM: return visitUDIVREM(N); case ISD::UDIVREM: return visitUDIVREM(N);
case ISD::SMIN:
case ISD::SMAX:
case ISD::UMIN:
case ISD::UMAX: return visitIMINMAX(N);
case ISD::AND: return visitAND(N); case ISD::AND: return visitAND(N);
case ISD::OR: return visitOR(N); case ISD::OR: return visitOR(N);
case ISD::XOR: return visitXOR(N); case ISD::XOR: return visitXOR(N);
case ISD::SHL: return visitSHL(N); case ISD::SHL: return visitSHL(N);
case ISD::SRA: return visitSRA(N); case ISD::SRA: return visitSRA(N);
case ISD::SRL: return visitSRL(N); case ISD::SRL: return visitSRL(N);
case ISD::ROTR: case ISD::ROTR:
case ISD::ROTL: return visitRotate(N); case ISD::ROTL: return visitRotate(N);
▲ Show 20 Lines • Show All 1,267 Lines • ▼ Show 20 Lines
SDValue DAGCombiner::visitUDIVREM(SDNode *N) { SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM)) if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM))
return Res; return Res;
return SDValue(); return SDValue();
} }
SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
// fold vector ops
if (VT.isVector())
if (SDValue FoldedVOp = SimplifyVBinOp(N))
return FoldedVOp;
// fold (add c1, c2) -> c1+c2
ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
if (N0C && N1C)
return DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, N0C, N1C);
// canonicalize constant to RHS
if (isConstantIntBuildVectorOrConstantInt(N0) &&
!isConstantIntBuildVectorOrConstantInt(N1))
return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
return SDValue();
}
/// If this is a binary operator with two operands of the same opcode, try to /// If this is a binary operator with two operands of the same opcode, try to
/// simplify it. /// simplify it.
SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
EVT VT = N0.getValueType(); EVT VT = N0.getValueType();
assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
// Bail early if none of these transforms apply. // Bail early if none of these transforms apply.
▲ Show 20 Lines • Show All 11,607 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,176 Lines • ▼ Show 20 Linesstatic std::pair<APInt, bool> FoldValue(unsigned Opcode, const APInt &C1,
case ISD::AND: return std::make_pair(C1 & C2, true); case ISD::AND: return std::make_pair(C1 & C2, true);
case ISD::OR: return std::make_pair(C1 | C2, true); case ISD::OR: return std::make_pair(C1 | C2, true);
case ISD::XOR: return std::make_pair(C1 ^ C2, true); case ISD::XOR: return std::make_pair(C1 ^ C2, true);
case ISD::SHL: return std::make_pair(C1 << C2, true); case ISD::SHL: return std::make_pair(C1 << C2, true);
case ISD::SRL: return std::make_pair(C1.lshr(C2), true); case ISD::SRL: return std::make_pair(C1.lshr(C2), true);
case ISD::SRA: return std::make_pair(C1.ashr(C2), true); case ISD::SRA: return std::make_pair(C1.ashr(C2), true);
case ISD::ROTL: return std::make_pair(C1.rotl(C2), true); case ISD::ROTL: return std::make_pair(C1.rotl(C2), true);
case ISD::ROTR: return std::make_pair(C1.rotr(C2), true); case ISD::ROTR: return std::make_pair(C1.rotr(C2), true);
case ISD::SMIN: return std::make_pair(C1.sle(C2) ? C1 : C2, true);
case ISD::SMAX: return std::make_pair(C1.sge(C2) ? C1 : C2, true);
case ISD::UMIN: return std::make_pair(C1.ule(C2) ? C1 : C2, true);
case ISD::UMAX: return std::make_pair(C1.uge(C2) ? C1 : C2, true);
case ISD::UDIV: case ISD::UDIV:
if (!C2.getBoolValue()) if (!C2.getBoolValue())
break; break;
return std::make_pair(C1.udiv(C2), true); return std::make_pair(C1.udiv(C2), true);
case ISD::UREM: case ISD::UREM:
if (!C2.getBoolValue()) if (!C2.getBoolValue())
break; break;
return std::make_pair(C1.urem(C2), true); return std::make_pair(C1.urem(C2), true);
▲ Show 20 Lines • Show All 158 Lines • ▼ Show 20 Lines case ISD::SUB:
break; break;
case ISD::UDIV: case ISD::UDIV:
case ISD::UREM: case ISD::UREM:
case ISD::MULHU: case ISD::MULHU:
case ISD::MULHS: case ISD::MULHS:
case ISD::MUL: case ISD::MUL:
case ISD::SDIV: case ISD::SDIV:
case ISD::SREM: case ISD::SREM:
case ISD::SMIN:
case ISD::SMAX:
case ISD::UMIN:
case ISD::UMAX:
assert(VT.isInteger() && "This operator does not apply to FP types!"); assert(VT.isInteger() && "This operator does not apply to FP types!");
assert(N1.getValueType() == N2.getValueType() && assert(N1.getValueType() == N2.getValueType() &&
N1.getValueType() == VT && "Binary operator types must match!"); N1.getValueType() == VT && "Binary operator types must match!");
break; break;
case ISD::FADD: case ISD::FADD:
case ISD::FSUB: case ISD::FSUB:
case ISD::FMUL: case ISD::FMUL:
case ISD::FDIV: case ISD::FDIV:
▲ Show 20 Lines • Show All 1,901 Lines • ▼ Show 20 Lines ID.AddInteger(encodeMemSDNodeFlags(ISD::NON_EXTLOAD, ISD::UNINDEXED,
MMO->isNonTemporal(), MMO->isNonTemporal(),
MMO->isInvariant())); MMO->isInvariant()));
ID.AddInteger(MMO->getPointerInfo().getAddrSpace()); ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
void *IP = nullptr; void *IP = nullptr;
if (SDNode *E = FindNodeOrInsertPos(ID, dl.getDebugLoc(), IP)) { if (SDNode *E = FindNodeOrInsertPos(ID, dl.getDebugLoc(), IP)) {
cast<MaskedGatherSDNode>(E)->refineAlignment(MMO); cast<MaskedGatherSDNode>(E)->refineAlignment(MMO);
return SDValue(E, 0); return SDValue(E, 0);
} }
MaskedGatherSDNode *N = MaskedGatherSDNode *N =
new (NodeAllocator) MaskedGatherSDNode(dl.getIROrder(), dl.getDebugLoc(), new (NodeAllocator) MaskedGatherSDNode(dl.getIROrder(), dl.getDebugLoc(),
Ops, VTs, VT, MMO); Ops, VTs, VT, MMO);
CSEMap.InsertNode(N, IP); CSEMap.InsertNode(N, IP);
InsertNode(N); InsertNode(N);
return SDValue(N, 0); return SDValue(N, 0);
} }
SDValue SelectionDAG::getMaskedScatter(SDVTList VTs, EVT VT, SDLoc dl, SDValue SelectionDAG::getMaskedScatter(SDVTList VTs, EVT VT, SDLoc dl,
▲ Show 20 Lines • Show All 1,903 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s
; PR11494 ; PR11494
define void @test(<4 x i32>* nocapture %p) nounwind { define void @test(<4 x i32>* nocapture %p) nounwind {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: vpxor %xmm0, %xmm0, %xmm0 ; CHECK: vpxor %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpmaxsd {{.*}}, %xmm0, %xmm0 ; CHECK-NEXT: vpmaxsd (%rdi), %xmm0, %xmm0
; CHECK-NEXT: vmovdqu %xmm0, (%rdi) ; CHECK-NEXT: vmovdqu %xmm0, (%rdi)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> <i32 -8, i32 -9, i32 -10, i32 -11>, <4 x i32> zeroinitializer) nounwind %a = load <4 x i32>, <4 x i32>* %p, align 1
%b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3> %b = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a, <4 x i32> zeroinitializer) nounwind
%c = shufflevector <8 x i32> %b, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %c = shufflevector <4 x i32> %b, <4 x i32> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3>
store <4 x i32> %c, <4 x i32>* %p, align 1 %d = shufflevector <8 x i32> %c, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
store <4 x i32> %d, <4 x i32>* %p, align 1
ret void ret void
} }
declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone

llvm/trunk/test/CodeGen/X86/vec_minmax_sint.ll

Show First 20 Lines • Show All 1,801 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pcmpgtd %xmm2, %xmm0 ; SSE2-NEXT: pcmpgtd %xmm2, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: max_gt_v4i32c: ; SSE41-LABEL: max_gt_v4i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE41-NEXT: pmaxsd {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: max_gt_v4i32c: ; SSE42-LABEL: max_gt_v4i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE42-NEXT: pmaxsd {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: max_gt_v4i32c: ; AVX-LABEL: max_gt_v4i32c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; AVX-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp sgt <4 x i32> %1, %2 %3 = icmp sgt <4 x i32> %1, %2
%4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
ret <4 x i32> %4 ret <4 x i32> %4
} }
Show All 13 Lines
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: pandn %xmm5, %xmm1 ; SSE2-NEXT: pandn %xmm5, %xmm1
; SSE2-NEXT: por %xmm3, %xmm1 ; SSE2-NEXT: por %xmm3, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: max_gt_v8i32c: ; SSE41-LABEL: max_gt_v8i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE41-NEXT: pmaxsd {{.*}}(%rip), %xmm0
; SSE41-NEXT: pmaxsd {{.*}}(%rip), %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: max_gt_v8i32c: ; SSE42-LABEL: max_gt_v8i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE42-NEXT: pmaxsd {{.*}}(%rip), %xmm0
; SSE42-NEXT: pmaxsd {{.*}}(%rip), %xmm1
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1-LABEL: max_gt_v8i32c: ; AVX-LABEL: max_gt_v8i32c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
; AVX1-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
; AVX1-NEXT: vpmaxsd {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: max_gt_v8i32c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX2-NEXT: vpmaxsd {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: max_gt_v8i32c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX512-NEXT: vpmaxsd {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp sgt <8 x i32> %1, %2 %3 = icmp sgt <8 x i32> %1, %2
%4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
ret <8 x i32> %4 ret <8 x i32> %4
} }
define <8 x i16> @max_gt_v8i16c() { define <8 x i16> @max_gt_v8i16c() {
; SSE-LABEL: max_gt_v8i16c: ; SSE-LABEL: max_gt_v8i16c:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; SSE-NEXT: pmaxsw {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: max_gt_v8i16c: ; AVX-LABEL: max_gt_v8i16c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; AVX-NEXT: vpmaxsw {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
%2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
%3 = icmp sgt <8 x i16> %1, %2 %3 = icmp sgt <8 x i16> %1, %2
%4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
ret <8 x i16> %4 ret <8 x i16> %4
} }
define <16 x i16> @max_gt_v16i16c() { define <16 x i16> @max_gt_v16i16c() {
; SSE-LABEL: max_gt_v16i16c: ; SSE-LABEL: max_gt_v16i16c:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8] ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
; SSE-NEXT: pmaxsw {{.*}}(%rip), %xmm0
; SSE-NEXT: pmaxsw {{.*}}(%rip), %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: max_gt_v16i16c: ; AVX-LABEL: max_gt_v16i16c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
; AVX1-NEXT: vpmaxsw {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
; AVX1-NEXT: vpmaxsw {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: max_gt_v16i16c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX2-NEXT: vpmaxsw {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: max_gt_v16i16c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX512-NEXT: vpmaxsw {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
%2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
%3 = icmp sgt <16 x i16> %1, %2 %3 = icmp sgt <16 x i16> %1, %2
%4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
ret <16 x i16> %4 ret <16 x i16> %4
} }
define <16 x i8> @max_gt_v16i8c() { define <16 x i8> @max_gt_v16i8c() {
; SSE2-LABEL: max_gt_v16i8c: ; SSE2-LABEL: max_gt_v16i8c:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,254,253,252,251,250,249,0,7,6,5,4,3,2,1,0] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,254,253,252,251,250,249,0,7,6,5,4,3,2,1,0]
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: pcmpgtb %xmm2, %xmm0 ; SSE2-NEXT: pcmpgtb %xmm2, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: max_gt_v16i8c: ; SSE41-LABEL: max_gt_v16i8c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
; SSE41-NEXT: pmaxsb {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: max_gt_v16i8c: ; SSE42-LABEL: max_gt_v16i8c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
; SSE42-NEXT: pmaxsb {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: max_gt_v16i8c: ; AVX-LABEL: max_gt_v16i8c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
; AVX-NEXT: vpmaxsb {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
%2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
%3 = icmp sgt <16 x i8> %1, %2 %3 = icmp sgt <16 x i8> %1, %2
%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
ret <16 x i8> %4 ret <16 x i8> %4
} }
▲ Show 20 Lines • Show All 223 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pxor %xmm3, %xmm0 ; SSE2-NEXT: pxor %xmm3, %xmm0
; SSE2-NEXT: pandn %xmm1, %xmm3 ; SSE2-NEXT: pandn %xmm1, %xmm3
; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: por %xmm3, %xmm0 ; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: max_ge_v4i32c: ; SSE41-LABEL: max_ge_v4i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE41-NEXT: pmaxsd {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: max_ge_v4i32c: ; SSE42-LABEL: max_ge_v4i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE42-NEXT: pmaxsd {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: max_ge_v4i32c: ; AVX-LABEL: max_ge_v4i32c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; AVX-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp sge <4 x i32> %1, %2 %3 = icmp sge <4 x i32> %1, %2
%4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
ret <4 x i32> %4 ret <4 x i32> %4
} }
Show All 17 Lines
; SSE2-NEXT: por %xmm7, %xmm0 ; SSE2-NEXT: por %xmm7, %xmm0
; SSE2-NEXT: pandn %xmm3, %xmm6 ; SSE2-NEXT: pandn %xmm3, %xmm6
; SSE2-NEXT: pandn %xmm5, %xmm1 ; SSE2-NEXT: pandn %xmm5, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1 ; SSE2-NEXT: por %xmm6, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: max_ge_v8i32c: ; SSE41-LABEL: max_ge_v8i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE41-NEXT: pmaxsd {{.*}}(%rip), %xmm0
; SSE41-NEXT: pmaxsd {{.*}}(%rip), %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: max_ge_v8i32c: ; SSE42-LABEL: max_ge_v8i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE42-NEXT: pmaxsd {{.*}}(%rip), %xmm0
; SSE42-NEXT: pmaxsd {{.*}}(%rip), %xmm1
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1-LABEL: max_ge_v8i32c: ; AVX-LABEL: max_ge_v8i32c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
; AVX1-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
; AVX1-NEXT: vpmaxsd {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: max_ge_v8i32c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX2-NEXT: vpmaxsd {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: max_ge_v8i32c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX512-NEXT: vpmaxsd {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp sge <8 x i32> %1, %2 %3 = icmp sge <8 x i32> %1, %2
%4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
ret <8 x i32> %4 ret <8 x i32> %4
} }
define <8 x i16> @max_ge_v8i16c() { define <8 x i16> @max_ge_v8i16c() {
; SSE-LABEL: max_ge_v8i16c: ; SSE-LABEL: max_ge_v8i16c:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; SSE-NEXT: pmaxsw {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: max_ge_v8i16c: ; AVX-LABEL: max_ge_v8i16c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; AVX-NEXT: vpmaxsw {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
%2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
%3 = icmp sge <8 x i16> %1, %2 %3 = icmp sge <8 x i16> %1, %2
%4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
ret <8 x i16> %4 ret <8 x i16> %4
} }
define <16 x i16> @max_ge_v16i16c() { define <16 x i16> @max_ge_v16i16c() {
; SSE-LABEL: max_ge_v16i16c: ; SSE-LABEL: max_ge_v16i16c:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8] ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
; SSE-NEXT: pmaxsw {{.*}}(%rip), %xmm0
; SSE-NEXT: pmaxsw {{.*}}(%rip), %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: max_ge_v16i16c: ; AVX-LABEL: max_ge_v16i16c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
; AVX1-NEXT: vpmaxsw {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
; AVX1-NEXT: vpmaxsw {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: max_ge_v16i16c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX2-NEXT: vpmaxsw {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: max_ge_v16i16c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX512-NEXT: vpmaxsw {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
%2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
%3 = icmp sge <16 x i16> %1, %2 %3 = icmp sge <16 x i16> %1, %2
%4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
ret <16 x i16> %4 ret <16 x i16> %4
} }
define <16 x i8> @max_ge_v16i8c() { define <16 x i8> @max_ge_v16i8c() {
; SSE2-LABEL: max_ge_v16i8c: ; SSE2-LABEL: max_ge_v16i8c:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,254,253,252,251,250,249,0,7,6,5,4,3,2,1,0] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,254,253,252,251,250,249,0,7,6,5,4,3,2,1,0]
; SSE2-NEXT: movdqa %xmm2, %xmm3 ; SSE2-NEXT: movdqa %xmm2, %xmm3
; SSE2-NEXT: pcmpgtb %xmm1, %xmm3 ; SSE2-NEXT: pcmpgtb %xmm1, %xmm3
; SSE2-NEXT: pcmpeqd %xmm0, %xmm0 ; SSE2-NEXT: pcmpeqd %xmm0, %xmm0
; SSE2-NEXT: pxor %xmm3, %xmm0 ; SSE2-NEXT: pxor %xmm3, %xmm0
; SSE2-NEXT: pandn %xmm1, %xmm3 ; SSE2-NEXT: pandn %xmm1, %xmm3
; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: por %xmm3, %xmm0 ; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: max_ge_v16i8c: ; SSE41-LABEL: max_ge_v16i8c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
; SSE41-NEXT: pmaxsb {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: max_ge_v16i8c: ; SSE42-LABEL: max_ge_v16i8c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
; SSE42-NEXT: pmaxsb {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: max_ge_v16i8c: ; AVX-LABEL: max_ge_v16i8c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
; AVX-NEXT: vpmaxsb {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
%2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
%3 = icmp sge <16 x i8> %1, %2 %3 = icmp sge <16 x i8> %1, %2
%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
ret <16 x i8> %4 ret <16 x i8> %4
} }
▲ Show 20 Lines • Show All 199 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: min_lt_v4i32c: ; SSE41-LABEL: min_lt_v4i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: min_lt_v4i32c: ; SSE42-LABEL: min_lt_v4i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: min_lt_v4i32c: ; AVX-LABEL: min_lt_v4i32c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; AVX-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp slt <4 x i32> %1, %2 %3 = icmp slt <4 x i32> %1, %2
%4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
ret <4 x i32> %4 ret <4 x i32> %4
} }
Show All 13 Lines
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: pandn %xmm5, %xmm1 ; SSE2-NEXT: pandn %xmm5, %xmm1
; SSE2-NEXT: por %xmm3, %xmm1 ; SSE2-NEXT: por %xmm3, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: min_lt_v8i32c: ; SSE41-LABEL: min_lt_v8i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm0
; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: min_lt_v8i32c: ; SSE42-LABEL: min_lt_v8i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm0
; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm1
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1-LABEL: min_lt_v8i32c: ; AVX-LABEL: min_lt_v8i32c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
; AVX1-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
; AVX1-NEXT: vpminsd {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: min_lt_v8i32c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX2-NEXT: vpminsd {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: min_lt_v8i32c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX512-NEXT: vpminsd {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp slt <8 x i32> %1, %2 %3 = icmp slt <8 x i32> %1, %2
%4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
ret <8 x i32> %4 ret <8 x i32> %4
} }
define <8 x i16> @min_lt_v8i16c() { define <8 x i16> @min_lt_v8i16c() {
; SSE-LABEL: min_lt_v8i16c: ; SSE-LABEL: min_lt_v8i16c:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
; SSE-NEXT: pminsw {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: min_lt_v8i16c: ; AVX-LABEL: min_lt_v8i16c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
; AVX-NEXT: vpminsw {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
%2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
%3 = icmp slt <8 x i16> %1, %2 %3 = icmp slt <8 x i16> %1, %2
%4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
ret <8 x i16> %4 ret <8 x i16> %4
} }
define <16 x i16> @min_lt_v16i16c() { define <16 x i16> @min_lt_v16i16c() {
; SSE-LABEL: min_lt_v16i16c: ; SSE-LABEL: min_lt_v16i16c:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8] ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
; SSE-NEXT: pminsw {{.*}}(%rip), %xmm0
; SSE-NEXT: pminsw {{.*}}(%rip), %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: min_lt_v16i16c: ; AVX-LABEL: min_lt_v16i16c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
; AVX1-NEXT: vpminsw {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
; AVX1-NEXT: vpminsw {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: min_lt_v16i16c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX2-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: min_lt_v16i16c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX512-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
%2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
%3 = icmp slt <16 x i16> %1, %2 %3 = icmp slt <16 x i16> %1, %2
%4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
ret <16 x i16> %4 ret <16 x i16> %4
} }
define <16 x i8> @min_lt_v16i8c() { define <16 x i8> @min_lt_v16i8c() {
; SSE2-LABEL: min_lt_v16i8c: ; SSE2-LABEL: min_lt_v16i8c:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,254,253,252,251,250,249,0,7,6,5,4,3,2,1,0] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,254,253,252,251,250,249,0,7,6,5,4,3,2,1,0]
; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: pcmpgtb %xmm1, %xmm0 ; SSE2-NEXT: pcmpgtb %xmm1, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: min_lt_v16i8c: ; SSE41-LABEL: min_lt_v16i8c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
; SSE41-NEXT: pminsb {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: min_lt_v16i8c: ; SSE42-LABEL: min_lt_v16i8c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
; SSE42-NEXT: pminsb {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: min_lt_v16i8c: ; AVX-LABEL: min_lt_v16i8c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
; AVX-NEXT: vpminsb {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
%2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
%3 = icmp slt <16 x i8> %1, %2 %3 = icmp slt <16 x i8> %1, %2
%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
ret <16 x i8> %4 ret <16 x i8> %4
} }
▲ Show 20 Lines • Show All 223 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pxor %xmm3, %xmm0 ; SSE2-NEXT: pxor %xmm3, %xmm0
; SSE2-NEXT: pandn %xmm1, %xmm3 ; SSE2-NEXT: pandn %xmm1, %xmm3
; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: por %xmm3, %xmm0 ; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: min_le_v4i32c: ; SSE41-LABEL: min_le_v4i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: min_le_v4i32c: ; SSE42-LABEL: min_le_v4i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: min_le_v4i32c: ; AVX-LABEL: min_le_v4i32c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; AVX-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp sle <4 x i32> %1, %2 %3 = icmp sle <4 x i32> %1, %2
%4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
ret <4 x i32> %4 ret <4 x i32> %4
} }
Show All 17 Lines
; SSE2-NEXT: por %xmm7, %xmm0 ; SSE2-NEXT: por %xmm7, %xmm0
; SSE2-NEXT: pandn %xmm3, %xmm6 ; SSE2-NEXT: pandn %xmm3, %xmm6
; SSE2-NEXT: pandn %xmm5, %xmm1 ; SSE2-NEXT: pandn %xmm5, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1 ; SSE2-NEXT: por %xmm6, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: min_le_v8i32c: ; SSE41-LABEL: min_le_v8i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm0
; SSE41-NEXT: pminsd {{.*}}(%rip), %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: min_le_v8i32c: ; SSE42-LABEL: min_le_v8i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm0
; SSE42-NEXT: pminsd {{.*}}(%rip), %xmm1
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1-LABEL: min_le_v8i32c: ; AVX-LABEL: min_le_v8i32c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
; AVX1-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
; AVX1-NEXT: vpminsd {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: min_le_v8i32c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX2-NEXT: vpminsd {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: min_le_v8i32c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX512-NEXT: vpminsd {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp sle <8 x i32> %1, %2 %3 = icmp sle <8 x i32> %1, %2
%4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
ret <8 x i32> %4 ret <8 x i32> %4
} }
define <8 x i16> @min_le_v8i16c() { define <8 x i16> @min_le_v8i16c() {
; SSE-LABEL: min_le_v8i16c: ; SSE-LABEL: min_le_v8i16c:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
; SSE-NEXT: pminsw {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: min_le_v8i16c: ; AVX-LABEL: min_le_v8i16c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
; AVX-NEXT: vpminsw {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
%2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
%3 = icmp sle <8 x i16> %1, %2 %3 = icmp sle <8 x i16> %1, %2
%4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
ret <8 x i16> %4 ret <8 x i16> %4
} }
define <16 x i16> @min_le_v16i16c() { define <16 x i16> @min_le_v16i16c() {
; SSE-LABEL: min_le_v16i16c: ; SSE-LABEL: min_le_v16i16c:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8] ; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
; SSE-NEXT: pminsw {{.*}}(%rip), %xmm0
; SSE-NEXT: pminsw {{.*}}(%rip), %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: min_le_v16i16c: ; AVX-LABEL: min_le_v16i16c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
; AVX1-NEXT: vpminsw {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
; AVX1-NEXT: vpminsw {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: min_le_v16i16c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX2-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: min_le_v16i16c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX512-NEXT: vpminsw {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
%2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
%3 = icmp sle <16 x i16> %1, %2 %3 = icmp sle <16 x i16> %1, %2
%4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
ret <16 x i16> %4 ret <16 x i16> %4
} }
define <16 x i8> @min_le_v16i8c() { define <16 x i8> @min_le_v16i8c() {
; SSE2-LABEL: min_le_v16i8c: ; SSE2-LABEL: min_le_v16i8c:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,254,253,252,251,250,249,0,7,6,5,4,3,2,1,0] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,254,253,252,251,250,249,0,7,6,5,4,3,2,1,0]
; SSE2-NEXT: movdqa %xmm1, %xmm3 ; SSE2-NEXT: movdqa %xmm1, %xmm3
; SSE2-NEXT: pcmpgtb %xmm2, %xmm3 ; SSE2-NEXT: pcmpgtb %xmm2, %xmm3
; SSE2-NEXT: pcmpeqd %xmm0, %xmm0 ; SSE2-NEXT: pcmpeqd %xmm0, %xmm0
; SSE2-NEXT: pxor %xmm3, %xmm0 ; SSE2-NEXT: pxor %xmm3, %xmm0
; SSE2-NEXT: pandn %xmm1, %xmm3 ; SSE2-NEXT: pandn %xmm1, %xmm3
; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: por %xmm3, %xmm0 ; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: min_le_v16i8c: ; SSE41-LABEL: min_le_v16i8c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
; SSE41-NEXT: pminsb {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: min_le_v16i8c: ; SSE42-LABEL: min_le_v16i8c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
; SSE42-NEXT: pminsb {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: min_le_v16i8c: ; AVX-LABEL: min_le_v16i8c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
; AVX-NEXT: vpminsb {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
%2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
%3 = icmp sle <16 x i8> %1, %2 %3 = icmp sle <16 x i8> %1, %2
%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
ret <16 x i8> %4 ret <16 x i8> %4
} }

llvm/trunk/test/CodeGen/X86/vec_minmax_uint.ll

Show First 20 Lines • Show All 1,936 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: max_gt_v4i32c: ; SSE41-LABEL: max_gt_v4i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: max_gt_v4i32c: ; SSE42-LABEL: max_gt_v4i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: max_gt_v4i32c: ; AVX-LABEL: max_gt_v4i32c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; AVX-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp ugt <4 x i32> %1, %2 %3 = icmp ugt <4 x i32> %1, %2
%4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
ret <4 x i32> %4 ret <4 x i32> %4
} }
Show All 11 Lines
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm2 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm2
; SSE2-NEXT: pand {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
; SSE2-NEXT: por %xmm2, %xmm1 ; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: max_gt_v8i32c: ; SSE41-LABEL: max_gt_v8i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm0
; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: max_gt_v8i32c: ; SSE42-LABEL: max_gt_v8i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm0
; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm1
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1-LABEL: max_gt_v8i32c: ; AVX-LABEL: max_gt_v8i32c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
; AVX1-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
; AVX1-NEXT: vpmaxud {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: max_gt_v8i32c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX2-NEXT: vpmaxud {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: max_gt_v8i32c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX512-NEXT: vpmaxud {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp ugt <8 x i32> %1, %2 %3 = icmp ugt <8 x i32> %1, %2
%4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
ret <8 x i32> %4 ret <8 x i32> %4
} }
define <8 x i16> @max_gt_v8i16c() { define <8 x i16> @max_gt_v8i16c() {
; SSE2-LABEL: max_gt_v8i16c: ; SSE2-LABEL: max_gt_v8i16c:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [32761,32763,32765,32767,32769,32771,32773,32775] ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [32761,32763,32765,32767,32769,32771,32773,32775]
; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: max_gt_v8i16c: ; SSE41-LABEL: max_gt_v8i16c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: max_gt_v8i16c: ; SSE42-LABEL: max_gt_v8i16c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: max_gt_v8i16c: ; AVX-LABEL: max_gt_v8i16c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; AVX-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
%2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
%3 = icmp ugt <8 x i16> %1, %2 %3 = icmp ugt <8 x i16> %1, %2
%4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
ret <8 x i16> %4 ret <8 x i16> %4
} }
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; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm2 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm2
; SSE2-NEXT: pand {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
; SSE2-NEXT: por %xmm2, %xmm1 ; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: max_gt_v16i16c: ; SSE41-LABEL: max_gt_v16i16c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm0
; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: max_gt_v16i16c: ; SSE42-LABEL: max_gt_v16i16c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm0
; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm1
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1-LABEL: max_gt_v16i16c: ; AVX-LABEL: max_gt_v16i16c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
; AVX1-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
; AVX1-NEXT: vpmaxuw {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: max_gt_v16i16c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX2-NEXT: vpmaxuw {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: max_gt_v16i16c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX512-NEXT: vpmaxuw {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
%2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
%3 = icmp ugt <16 x i16> %1, %2 %3 = icmp ugt <16 x i16> %1, %2
%4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
ret <16 x i16> %4 ret <16 x i16> %4
} }
define <16 x i8> @max_gt_v16i8c() { define <16 x i8> @max_gt_v16i8c() {
; SSE-LABEL: max_gt_v16i8c: ; SSE-LABEL: max_gt_v16i8c:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
; SSE-NEXT: pmaxub {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: max_gt_v16i8c: ; AVX-LABEL: max_gt_v16i8c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
; AVX-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
%2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
%3 = icmp ugt <16 x i8> %1, %2 %3 = icmp ugt <16 x i8> %1, %2
%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
ret <16 x i8> %4 ret <16 x i8> %4
} }
▲ Show 20 Lines • Show All 218 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pxor %xmm0, %xmm1 ; SSE2-NEXT: pxor %xmm0, %xmm1
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: max_ge_v4i32c: ; SSE41-LABEL: max_ge_v4i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: max_ge_v4i32c: ; SSE42-LABEL: max_ge_v4i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: max_ge_v4i32c: ; AVX-LABEL: max_ge_v4i32c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; AVX-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp uge <4 x i32> %1, %2 %3 = icmp uge <4 x i32> %1, %2
%4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
ret <4 x i32> %4 ret <4 x i32> %4
} }
Show All 13 Lines
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm3 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm3
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1
; SSE2-NEXT: por %xmm3, %xmm1 ; SSE2-NEXT: por %xmm3, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: max_ge_v8i32c: ; SSE41-LABEL: max_ge_v8i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm0
; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: max_ge_v8i32c: ; SSE42-LABEL: max_ge_v8i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm0
; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm1
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1-LABEL: max_ge_v8i32c: ; AVX-LABEL: max_ge_v8i32c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
; AVX1-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
; AVX1-NEXT: vpmaxud {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: max_ge_v8i32c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX2-NEXT: vpmaxud {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: max_ge_v8i32c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX512-NEXT: vpmaxud {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp uge <8 x i32> %1, %2 %3 = icmp uge <8 x i32> %1, %2
%4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
ret <8 x i32> %4 ret <8 x i32> %4
} }
define <8 x i16> @max_ge_v8i16c() { define <8 x i16> @max_ge_v8i16c() {
; SSE2-LABEL: max_ge_v8i16c: ; SSE2-LABEL: max_ge_v8i16c:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65529,65531,65533,65535,1,3,5,7] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65529,65531,65533,65535,1,3,5,7]
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,65533,65531,65529,7,5,3,1] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,65533,65531,65529,7,5,3,1]
; SSE2-NEXT: movdqa %xmm2, %xmm3 ; SSE2-NEXT: movdqa %xmm2, %xmm3
; SSE2-NEXT: psubusw %xmm1, %xmm3 ; SSE2-NEXT: psubusw %xmm1, %xmm3
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: pcmpeqw %xmm3, %xmm0 ; SSE2-NEXT: pcmpeqw %xmm3, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: max_ge_v8i16c: ; SSE41-LABEL: max_ge_v8i16c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: max_ge_v8i16c: ; SSE42-LABEL: max_ge_v8i16c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: max_ge_v8i16c: ; AVX-LABEL: max_ge_v8i16c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; AVX-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
%2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
%3 = icmp uge <8 x i16> %1, %2 %3 = icmp uge <8 x i16> %1, %2
%4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
ret <8 x i16> %4 ret <8 x i16> %4
} }
Show All 16 Lines
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: pandn %xmm5, %xmm1 ; SSE2-NEXT: pandn %xmm5, %xmm1
; SSE2-NEXT: por %xmm3, %xmm1 ; SSE2-NEXT: por %xmm3, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: max_ge_v16i16c: ; SSE41-LABEL: max_ge_v16i16c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm0
; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: max_ge_v16i16c: ; SSE42-LABEL: max_ge_v16i16c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm0
; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm1
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1-LABEL: max_ge_v16i16c: ; AVX-LABEL: max_ge_v16i16c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
; AVX1-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
; AVX1-NEXT: vpmaxuw {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: max_ge_v16i16c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX2-NEXT: vpmaxuw {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: max_ge_v16i16c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX512-NEXT: vpmaxuw {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
%2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
%3 = icmp uge <16 x i16> %1, %2 %3 = icmp uge <16 x i16> %1, %2
%4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
ret <16 x i16> %4 ret <16 x i16> %4
} }
define <16 x i8> @max_ge_v16i8c() { define <16 x i8> @max_ge_v16i8c() {
; SSE-LABEL: max_ge_v16i8c: ; SSE-LABEL: max_ge_v16i8c:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
; SSE-NEXT: pmaxub {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: max_ge_v16i8c: ; AVX-LABEL: max_ge_v16i8c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
; AVX-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
%2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
%3 = icmp uge <16 x i8> %1, %2 %3 = icmp uge <16 x i8> %1, %2
%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
ret <16 x i8> %4 ret <16 x i8> %4
} }
▲ Show 20 Lines • Show All 195 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: min_lt_v4i32c: ; SSE41-LABEL: min_lt_v4i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: min_lt_v4i32c: ; SSE42-LABEL: min_lt_v4i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE42-NEXT: pminud {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: min_lt_v4i32c: ; AVX-LABEL: min_lt_v4i32c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; AVX-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp ult <4 x i32> %1, %2 %3 = icmp ult <4 x i32> %1, %2
%4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
ret <4 x i32> %4 ret <4 x i32> %4
} }
Show All 11 Lines
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm2 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm2
; SSE2-NEXT: pand {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
; SSE2-NEXT: por %xmm2, %xmm1 ; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: min_lt_v8i32c: ; SSE41-LABEL: min_lt_v8i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0
; SSE41-NEXT: pminud {{.*}}(%rip), %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: min_lt_v8i32c: ; SSE42-LABEL: min_lt_v8i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE42-NEXT: pminud {{.*}}(%rip), %xmm0
; SSE42-NEXT: pminud {{.*}}(%rip), %xmm1
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1-LABEL: min_lt_v8i32c: ; AVX-LABEL: min_lt_v8i32c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: min_lt_v8i32c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX2-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: min_lt_v8i32c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX512-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp ult <8 x i32> %1, %2 %3 = icmp ult <8 x i32> %1, %2
%4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
ret <8 x i32> %4 ret <8 x i32> %4
} }
define <8 x i16> @min_lt_v8i16c() { define <8 x i16> @min_lt_v8i16c() {
; SSE2-LABEL: min_lt_v8i16c: ; SSE2-LABEL: min_lt_v8i16c:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65529,65531,65533,65535,1,3,5,7] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65529,65531,65533,65535,1,3,5,7]
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psubusw {{.*}}(%rip), %xmm2 ; SSE2-NEXT: psubusw {{.*}}(%rip), %xmm2
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: pcmpeqw %xmm2, %xmm0 ; SSE2-NEXT: pcmpeqw %xmm2, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: min_lt_v8i16c: ; SSE41-LABEL: min_lt_v8i16c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [1,65531,65531,65529,1,3,3,1]
; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: min_lt_v8i16c: ; SSE42-LABEL: min_lt_v8i16c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [1,65531,65531,65529,1,3,3,1]
; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: min_lt_v8i16c: ; AVX-LABEL: min_lt_v8i16c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,65531,65531,65529,1,3,3,1]
; AVX-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
%2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 1, i32 0 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 1, i32 0
%3 = icmp ult <8 x i16> %1, %2 %3 = icmp ult <8 x i16> %1, %2
%4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
ret <8 x i16> %4 ret <8 x i16> %4
} }
Show All 11 Lines
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm2 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm2
; SSE2-NEXT: pand {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
; SSE2-NEXT: por %xmm2, %xmm1 ; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: min_lt_v16i16c: ; SSE41-LABEL: min_lt_v16i16c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [1,65530,65531,65532,65531,65530,65529,0]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0
; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: min_lt_v16i16c: ; SSE42-LABEL: min_lt_v16i16c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [1,65530,65531,65532,65531,65530,65529,0]
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm0
; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm1
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1-LABEL: min_lt_v16i16c: ; AVX-LABEL: min_lt_v16i16c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [1,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
; AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
; AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: min_lt_v16i16c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX2-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: min_lt_v16i16c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX512-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
%2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 1, i32 0 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 1, i32 0
%3 = icmp ult <16 x i16> %1, %2 %3 = icmp ult <16 x i16> %1, %2
%4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
ret <16 x i16> %4 ret <16 x i16> %4
} }
define <16 x i8> @min_lt_v16i8c() { define <16 x i8> @min_lt_v16i8c() {
; SSE-LABEL: min_lt_v16i8c: ; SSE-LABEL: min_lt_v16i8c:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
; SSE-NEXT: pminub {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: min_lt_v16i8c: ; AVX-LABEL: min_lt_v16i8c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
; AVX-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
%2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 1, i32 0 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 1, i32 0
%3 = icmp ult <16 x i8> %1, %2 %3 = icmp ult <16 x i8> %1, %2
%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
ret <16 x i8> %4 ret <16 x i8> %4
} }
▲ Show 20 Lines • Show All 218 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pxor %xmm0, %xmm1 ; SSE2-NEXT: pxor %xmm0, %xmm1
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: min_le_v4i32c: ; SSE41-LABEL: min_le_v4i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: min_le_v4i32c: ; SSE42-LABEL: min_le_v4i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE42-NEXT: pminud {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: min_le_v4i32c: ; AVX-LABEL: min_le_v4i32c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; AVX-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp ule <4 x i32> %1, %2 %3 = icmp ule <4 x i32> %1, %2
%4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
ret <4 x i32> %4 ret <4 x i32> %4
} }
Show All 13 Lines
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm3 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm3
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1
; SSE2-NEXT: por %xmm3, %xmm1 ; SSE2-NEXT: por %xmm3, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: min_le_v8i32c: ; SSE41-LABEL: min_le_v8i32c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0
; SSE41-NEXT: pminud {{.*}}(%rip), %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: min_le_v8i32c: ; SSE42-LABEL: min_le_v8i32c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE42-NEXT: pminud {{.*}}(%rip), %xmm0
; SSE42-NEXT: pminud {{.*}}(%rip), %xmm1
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1-LABEL: min_le_v8i32c: ; AVX-LABEL: min_le_v8i32c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: min_le_v8i32c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX2-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: min_le_v8i32c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
; AVX512-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp ule <8 x i32> %1, %2 %3 = icmp ule <8 x i32> %1, %2
%4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
ret <8 x i32> %4 ret <8 x i32> %4
} }
define <8 x i16> @min_le_v8i16c() { define <8 x i16> @min_le_v8i16c() {
; SSE2-LABEL: min_le_v8i16c: ; SSE2-LABEL: min_le_v8i16c:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65529,65531,65533,65535,1,3,5,7] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65529,65531,65533,65535,1,3,5,7]
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,65533,65531,65529,7,5,3,1] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,65533,65531,65529,7,5,3,1]
; SSE2-NEXT: movdqa %xmm1, %xmm3 ; SSE2-NEXT: movdqa %xmm1, %xmm3
; SSE2-NEXT: psubusw %xmm2, %xmm3 ; SSE2-NEXT: psubusw %xmm2, %xmm3
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: pcmpeqw %xmm3, %xmm0 ; SSE2-NEXT: pcmpeqw %xmm3, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: min_le_v8i16c: ; SSE41-LABEL: min_le_v8i16c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: min_le_v8i16c: ; SSE42-LABEL: min_le_v8i16c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: min_le_v8i16c: ; AVX-LABEL: min_le_v8i16c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
; AVX-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
%2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
%3 = icmp ule <8 x i16> %1, %2 %3 = icmp ule <8 x i16> %1, %2
%4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
ret <8 x i16> %4 ret <8 x i16> %4
} }
Show All 16 Lines
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: pandn %xmm5, %xmm1 ; SSE2-NEXT: pandn %xmm5, %xmm1
; SSE2-NEXT: por %xmm3, %xmm1 ; SSE2-NEXT: por %xmm3, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: min_le_v16i16c: ; SSE41-LABEL: min_le_v16i16c:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0
; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: min_le_v16i16c: ; SSE42-LABEL: min_le_v16i16c:
; SSE42: # BB#0: ; SSE42: # BB#0:
; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8] ; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm0
; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm1
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1-LABEL: min_le_v16i16c: ; AVX-LABEL: min_le_v16i16c:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0] ; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
; AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
; AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: min_le_v16i16c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX2-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: min_le_v16i16c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
; AVX512-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
%2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
%3 = icmp ule <16 x i16> %1, %2 %3 = icmp ule <16 x i16> %1, %2
%4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
ret <16 x i16> %4 ret <16 x i16> %4
} }
define <16 x i8> @min_le_v16i8c() { define <16 x i8> @min_le_v16i8c() {
; SSE-LABEL: min_le_v16i8c: ; SSE-LABEL: min_le_v16i8c:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; SSE-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
; SSE-NEXT: pminub {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: min_le_v16i8c: ; AVX-LABEL: min_le_v16i8c:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
; AVX-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
%2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
%3 = icmp ule <16 x i8> %1, %2 %3 = icmp ule <16 x i8> %1, %2
%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
ret <16 x i8> %4 ret <16 x i8> %4
} }