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Differential D120991

[NVPTX] Correctly set regs for neg, abs intrinsics
ClosedPublic

Authored by jchlanda on Mar 4 2022, 5:35 AM.

Details

Reviewers
tra
Commits
rGdce6aa237a07: [NVPTX] Correctly set regs for neg, abs intrinsics
Summary

This patch fixes a bug introduced in D117887.

Diff Detail

Unit TestsFailed

TimeTest
60,090 msx64 debian > AddressSanitizer-x86_64-linux-dynamic.TestCases::scariness_score_test.cpp
60,150 msx64 debian > AddressSanitizer-x86_64-linux.TestCases::scariness_score_test.cpp
40 msx64 debian > LLVM.MC/WebAssembly::tables.s
60,030 msx64 debian > libFuzzer.libFuzzer::fuzzer-leak.test
60,120 msx64 debian > libFuzzer.libFuzzer::large.test
View Full Test Results (8 Failed)

Event Timeline

jchlanda created this revision.Mar 4 2022, 5:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 4 2022, 5:35 AM
Herald added subscribers: asavonic, hiraditya, jholewinski. · View Herald Transcript
jchlanda requested review of this revision.Mar 4 2022, 5:35 AM
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Harbormaster completed remote builds in B152576: Diff 412990.Mar 4 2022, 6:00 AM
tra accepted this revision.Mar 4 2022, 10:42 AM

Oops. LGTM.

This revision is now accepted and ready to land.Mar 4 2022, 10:42 AM
This revision was landed with ongoing or failed builds.Mar 4 2022, 11:07 AM
Closed by commit rGdce6aa237a07: [NVPTX] Correctly set regs for neg, abs intrinsics (authored by jchlanda, committed by tra). · Explain Why
This revision was automatically updated to reflect the committed changes.
tra added a commit: rGdce6aa237a07: [NVPTX] Correctly set regs for neg, abs intrinsics.

Revision Contents

PathSize
llvm/
lib/
Target/
NVPTX/
8 lines

Diff 412990

llvm/lib/Target/NVPTX/NVPTXIntrinsics.td

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def INT_NVVM_FABS_D : F_MATH_1<"abs.f64 \t$dst, $src0;", Float64Regs, def INT_NVVM_FABS_D : F_MATH_1<"abs.f64 \t$dst, $src0;", Float64Regs,
Float64Regs, int_nvvm_fabs_d>; Float64Regs, int_nvvm_fabs_d>;
// //
// Abs, Neg bf16, bf16x2 // Abs, Neg bf16, bf16x2
// //
def INT_NVVM_ABS_BF16 : F_MATH_1<"abs.bf16 \t$dst, $dst;", Int16Regs, def INT_NVVM_ABS_BF16 : F_MATH_1<"abs.bf16 \t$dst, $src0;", Int16Regs,
Int16Regs, int_nvvm_abs_bf16, [hasPTX70, hasSM80]>; Int16Regs, int_nvvm_abs_bf16, [hasPTX70, hasSM80]>;
def INT_NVVM_ABS_BF16X2 : F_MATH_1<"abs.bf16x2 \t$dst, $dst;", Int32Regs, def INT_NVVM_ABS_BF16X2 : F_MATH_1<"abs.bf16x2 \t$dst, $src0;", Int32Regs,
Int32Regs, int_nvvm_abs_bf16x2, [hasPTX70, hasSM80]>; Int32Regs, int_nvvm_abs_bf16x2, [hasPTX70, hasSM80]>;
def INT_NVVM_NEG_BF16 : F_MATH_1<"neg.bf16 \t$dst, $dst;", Int16Regs, def INT_NVVM_NEG_BF16 : F_MATH_1<"neg.bf16 \t$dst, $src0;", Int16Regs,
Int16Regs, int_nvvm_neg_bf16, [hasPTX70, hasSM80]>; Int16Regs, int_nvvm_neg_bf16, [hasPTX70, hasSM80]>;
def INT_NVVM_NEG_BF16X2 : F_MATH_1<"neg.bf16x2 \t$dst, $dst;", Int32Regs, def INT_NVVM_NEG_BF16X2 : F_MATH_1<"neg.bf16x2 \t$dst, $src0;", Int32Regs,
Int32Regs, int_nvvm_neg_bf16x2, [hasPTX70, hasSM80]>; Int32Regs, int_nvvm_neg_bf16x2, [hasPTX70, hasSM80]>;
// //
// Round // Round
// //
def : Pat<(int_nvvm_round_ftz_f Float32Regs:$a), def : Pat<(int_nvvm_round_ftz_f Float32Regs:$a),
(CVT_f32_f32 Float32Regs:$a, CvtRNI_FTZ)>; (CVT_f32_f32 Float32Regs:$a, CvtRNI_FTZ)>;
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