[AtomicExpand][PowerPC] Fix all-one mask value

[lkail]

Summary

When generating a all-one mask value whose bitwidth is larger than 64, signed extension should be used rather then zero extension.

[jsji]

LGTM. Thanks.

llvm/lib/CodeGen/AtomicExpandPass.cpp

static PartwordMaskValues createMaskInstrs(IRBuilder<> &Builder, Instruction *I,
 
   PMV.ValueType = ValueType;
   PMV.WordType = MinWordSize > ValueSize ? Type::getIntNTy(Ctx, MinWordSize * 8)
                                          : ValueType;
   if (PMV.ValueType == PMV.WordType) {
     PMV.AlignedAddr = Addr;
     PMV.AlignedAddrAlignment = AddrAlign;
     PMV.ShiftAmt = ConstantInt::get(PMV.ValueType, 0);
-    PMV.Mask = ConstantInt::get(PMV.ValueType, ~0);
+    PMV.Mask = ConstantInt::get(PMV.ValueType, ~0, /*isSigned*/ true);
     return PMV;
   }
 
   assert(ValueSize < MinWordSize);
 
   Type *WordPtrType =
       PMV.WordType->getPointerTo(Addr->getType()->getPointerAddressSpace());
 

llvm/test/CodeGen/PowerPC/atomics-i128.ll

 ; CHECK-NEXT:    mr r10, r6
 ; CHECK-NEXT:    stqcx. r10, 0, r3
 ; CHECK-NEXT:    bne cr0, .LBB11_1
 ; CHECK-NEXT:    b .LBB11_4
 ; CHECK-NEXT:  .LBB11_3: # %entry
 ; CHECK-NEXT:    stqcx. r8, 0, r3
 ; CHECK-NEXT:  .LBB11_4: # %entry
 ; CHECK-NEXT:    lwsync
-; CHECK-NEXT:    xor r3, r5, r9
-; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    xor r3, r4, r8
+; CHECK-NEXT:    xor r4, r5, r9
+; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 58, 63
 ; CHECK-NEXT:    blr
 ;
 ; PWR7-LABEL: cas_acqrel_acquire_check_succ:
 ; PWR7:       # %bb.0: # %entry
 ; PWR7-NEXT:    mflr r0
 ; PWR7-NEXT:    std r0, 16(r1)

llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll

 ; CHECK-NEXT:    call void @llvm.ppc.lwsync()
 ; CHECK-NEXT:    [[LO:%.*]] = extractvalue { i64, i64 } [[TMP3]], 0
 ; CHECK-NEXT:    [[HI:%.*]] = extractvalue { i64, i64 } [[TMP3]], 1
 ; CHECK-NEXT:    [[LO64:%.*]] = zext i64 [[LO]] to i128
 ; CHECK-NEXT:    [[HI64:%.*]] = zext i64 [[HI]] to i128
 ; CHECK-NEXT:    [[TMP4:%.*]] = shl i128 [[HI64]], 64
 ; CHECK-NEXT:    [[VAL64:%.*]] = or i128 [[LO64]], [[TMP4]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = insertvalue { i128, i1 } undef, i128 [[VAL64]], 0
-; CHECK-NEXT:    [[TMP6:%.*]] = and i128 [[VAL64]], 18446744073709551615
+; CHECK-NEXT:    [[TMP6:%.*]] = and i128 [[VAL64]], -1
 ; CHECK-NEXT:    [[SUCCESS:%.*]] = icmp eq i128 [[CMPVAL_SHIFTED]], [[TMP6]]
 ; CHECK-NEXT:    [[TMP7:%.*]] = insertvalue { i128, i1 } [[TMP5]], i1 [[SUCCESS]], 1
 ; CHECK-NEXT:    [[SUCC:%.*]] = extractvalue { i128, i1 } [[TMP7]], 1
 ; CHECK-NEXT:    ret i1 [[SUCC]]
 ;
 entry:
   %pair = cmpxchg weak i128* %addr, i128 %desire, i128 %new seq_cst seq_cst
   %succ = extractvalue {i128, i1} %pair, 1
   ret i1 %succ
 }