AMDGPU: Refactor exp instructions

[arsenm]

Summary

Structure the definitions a bit more like the other classes.

The main change here is to split EXP with the done bit set
to a separate opcode, so we can set hasSideEffects = 1
if the done bit is in use since this has the special constraint
that it should be the last exp in the shader.

Previously all exp instructions were inferred to have unmodeled
side effects.

[mareko]

DONE doesn't always mean it's the last EXP in the shader. It's only true for pixel shaders. For vertex shaders, it means it's the last Position export. Param vertex shader exports are unaffected and can be moved arbitrarily.

[axeldavy]

I think the DONE bit should be added at one of the last passes of compilation.

Especially we want to be free at Scheduling step to move around the exp instructions and have them the order we want.
I guess the export may take some time, so earlier the exp, the best.

We can also introduce in the SI scheduler some way to incitate to have the position exports first for vertex shaders.

[• tstellarAMD]

I'm see cannot select error for EXPORT_DONE with this test case:

define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
main_body:

call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
ret void

}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" }

[mareko]

Please ignore what I said. I've talked with a Catalyst guy and he said we should emit exports as late in the shader as possible. The export memory can be allocated in the first export instruction and it limits the number of waves that can be run from that point. It's okay to reorder exports, but please don't emit them too early.

[arsenm]

In D12067#269437, @mareko wrote:

Please ignore what I said. I've talked with a Catalyst guy and he said we should emit exports as late in the shader as possible. The export memory can be allocated in the first export instruction and it limits the number of waves that can be run from that point. It's okay to reorder exports, but please don't emit them too early.

This patch shouldn't effect the scheduling of exports much if any

[arsenm]

What needs to be done on this? The cannot select error is a frontend bug

[arsenm]

Update for trunk. Set mayLoad = 1 for EXP_DONE instead of hasSideEffects

[arsenm]

Change integer type

[mareko]

Could you briefly describe what effect this will have on behavior? (e.g. scheduling)

[axeldavy]

In D12067#484345, @arsenm wrote:

Update for trunk. Set mayLoad = 1 for EXP_DONE instead of hasSideEffects

Could you explain why ? To me it looks like hasSideEffects is the only way to guarantee the exp with the done bit is last.

Btw you forgot to update the comments in the part "Export opcodes" to reflect that change.

[arsenm]

In D12067#486407, @axeldavy wrote:

In D12067#484345, @arsenm wrote:

Update for trunk. Set mayLoad = 1 for EXP_DONE instead of hasSideEffects

Could you explain why ? To me it looks like hasSideEffects is the only way to guarantee the exp with the done bit is last.

Btw you forgot to update the comments in the part "Export opcodes" to reflect that change.

If exp_done is reading from unknown memory, it can't be reordered before the stores to unknown memory

[arsenm]

In D12067#486222, @mareko wrote:

Could you briefly describe what effect this will have on behavior? (e.g. scheduling)

I don't think it should have that much impact on scheduling, there might be some changes around the done part

[arsenm]

In D12067#486407, @axeldavy wrote:

In D12067#484345, @arsenm wrote:

Update for trunk. Set mayLoad = 1 for EXP_DONE instead of hasSideEffects

Could you explain why ? To me it looks like hasSideEffects is the only way to guarantee the exp with the done bit is last.

Btw you forgot to update the comments in the part "Export opcodes" to reflect that change.

I see some regressions with the mayLoad bit set for exp_done, but without it I see minimal changes: https://ghostbin.com/paste/b6ypo

I can drop the separate bit setting part of this patch for now and revisit it later

[arsenm]

Update for trunk

[arsenm]

Reorder operands

[nhaehnle]

The TODOs need to be addressed, and for the FIXMEs in the intrinsic definition, I'd say we're better off just adding a real llvm.amdgcn.export (+ .done?) intrinsic in the future. Some more inline comments, but overall I think this patch is fine.

lib/Target/AMDGPU/AMDGPUInstrInfo.td

264–266

SDNPMayLoad instead of SDNPSideEffect for consistency.

lib/Target/AMDGPU/SIInstrInfo.td

680–681

s/hasSideEffects/mayLoad/

[arsenm]

In D12067#599858, @nhaehnle wrote:

The TODOs need to be addressed, and for the FIXMEs in the intrinsic definition, I'd say we're better off just adding a real llvm.amdgcn.export (+ .done?) intrinsic in the future. Some more inline comments, but overall I think this patch is fine.

The only TODOs I see left are addressed in the D12068

[mareko]

FYI, I'm working on a pass that moves all EXP instructions to the end of shaders after the machine scheduler. We don't want any scheduling optimizations for those.

[arsenm]

Address comments, merge changes from other patch

[arsenm]

Attach right patch. Bit inputs are temporarily printed as -1 until the next patch which fixes the printing

[nhaehnle]

LGTM

[arsenm]

r288695 with waitcnt insert fix

lib/Target/AMDGPU/AMDGPUISelLowering.h

enum NodeType : unsigned {
   BFI, // (src0 & src1) | (~src0 & src2)
   BFM, // Insert a range of bits into a 32-bit word.
   FFBH_U32, // ctlz with -1 if input is zero.
   MUL_U24,
   MUL_I24,
   MAD_U24,
   MAD_I24,
   TEXTURE_FETCH,
-  EXPORT,
+  EXPORT, // exp on SI+
+  EXPORT_DONE, // exp on SI+ with done bit set
+  R600_EXPORT,
   CONST_ADDRESS,
   REGISTER_LOAD,
   REGISTER_STORE,
   LOAD_INPUT,
   SAMPLE,
   SAMPLEB,
   SAMPLED,
   SAMPLEL,

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
   NODE_NAME_CASE(BFM)
   NODE_NAME_CASE(FFBH_U32)
   NODE_NAME_CASE(MUL_U24)
   NODE_NAME_CASE(MUL_I24)
   NODE_NAME_CASE(MAD_U24)
   NODE_NAME_CASE(MAD_I24)
   NODE_NAME_CASE(TEXTURE_FETCH)
   NODE_NAME_CASE(EXPORT)
+  NODE_NAME_CASE(EXPORT_DONE)
+  NODE_NAME_CASE(R600_EXPORT)
   NODE_NAME_CASE(CONST_ADDRESS)
   NODE_NAME_CASE(REGISTER_LOAD)
   NODE_NAME_CASE(REGISTER_STORE)
   NODE_NAME_CASE(LOAD_INPUT)
   NODE_NAME_CASE(SAMPLE)
   NODE_NAME_CASE(SAMPLEB)
   NODE_NAME_CASE(SAMPLED)
   NODE_NAME_CASE(SAMPLEL)

lib/Target/AMDGPU/AMDGPUInstrInfo.td

 def AMDGPUinterp_p1 : SDNode<"AMDGPUISD::INTERP_P1",
                       SDTypeProfile<1, 3, [SDTCisFP<0>]>,
                       [SDNPInGlue, SDNPOutGlue]>;
 
 def AMDGPUinterp_p2 : SDNode<"AMDGPUISD::INTERP_P2",
                       SDTypeProfile<1, 4, [SDTCisFP<0>]>,
                       [SDNPInGlue]>;
 
+// SI+ export
+def AMDGPUExportOp : SDTypeProfile<0, 8, [
+  SDTCisInt<0>, // i32 en
+  SDTCisInt<1>, // i1 vm
+  // skip done
+  SDTCisSameAs<2, 0>, // i32 tgt
+  SDTCisSameAs<3, 1>, // i1 compr
+  SDTCisFP<4>,        // f32 src0
+  SDTCisSameAs<5, 4>, // f32 src1
+  SDTCisSameAs<6, 4>, // f32 src2
+  SDTCisSameAs<7, 4>  // f32 src3
+]>;
+
+def AMDGPUexport: SDNode<"AMDGPUISD::EXPORT", AMDGPUExportOp,
+  [SDNPHasChain, SDNPMayStore]>;
+
+def AMDGPUexport_done: SDNode<"AMDGPUISD::EXPORT_DONE", AMDGPUExportOp,
+  [SDNPHasChain, SDNPMayStore, SDNPSideEffect]>;
+
+
+def R600ExportOp : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
+
+def R600_EXPORT: SDNode<"AMDGPUISD::R600_EXPORT", R600ExportOp,
+  [SDNPHasChain, SDNPSideEffect]>;
+
 //===----------------------------------------------------------------------===//
 // Flow Control Profile Types
 //===----------------------------------------------------------------------===//
 // Branch instruction where second and third are basic blocks
 def SDTIL_BRCond : SDTypeProfile<0, 2, [
     SDTCisVT<0, OtherVT>
     ]>;
 

lib/Target/AMDGPU/R600ISelLowering.cpp

case AMDGPUIntrinsic::R600_store_swizzle: {
         Op.getOperand(2), // Export Value
         Op.getOperand(3), // ArrayBase
         Op.getOperand(4), // Type
         DAG.getConstant(0, DL, MVT::i32), // SWZ_X
         DAG.getConstant(1, DL, MVT::i32), // SWZ_Y
         DAG.getConstant(2, DL, MVT::i32), // SWZ_Z
         DAG.getConstant(3, DL, MVT::i32) // SWZ_W
       };
-      return DAG.getNode(AMDGPUISD::EXPORT, DL, Op.getValueType(), Args);
+      return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args);
     }
 
     // default for switch(IntrinsicID)
     default: break;
     }
     // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
     break;
   }
case ISD::SETEQ: {
                                LHS.getOperand(3),
                                LHSCC);
       break;
     }
     }
     return SDValue();
   }
 
-  case AMDGPUISD::EXPORT: {
+  case AMDGPUISD::R600_EXPORT: {
     SDValue Arg = N->getOperand(1);
     if (Arg.getOpcode() != ISD::BUILD_VECTOR)
       break;
 
     SDValue NewArgs[8] = {
       N->getOperand(0), // Chain
       SDValue(),
       N->getOperand(2), // ArrayBase
       N->getOperand(3), // Type
       N->getOperand(4), // SWZ_X
       N->getOperand(5), // SWZ_Y
       N->getOperand(6), // SWZ_Z
       N->getOperand(7) // SWZ_W
     };
     SDLoc DL(N);
     NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG, DL);
-    return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs);
+    return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, N->getVTList(), NewArgs);
   }
   case AMDGPUISD::TEXTURE_FETCH: {
     SDValue Arg = N->getOperand(1);
     if (Arg.getOpcode() != ISD::BUILD_VECTOR)
       break;
 
     SDValue NewArgs[19] = {
       N->getOperand(0),

lib/Target/AMDGPU/R600Instructions.td

 }
 
 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
 
 //===----------------------------------------------------------------------===//
 // Export Instructions
 //===----------------------------------------------------------------------===//
 
-def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
-
-def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
-  [SDNPHasChain, SDNPSideEffect]>;
-
 class ExportWord0 {
   field bits<32> Word0;
 
   bits<13> arraybase;
   bits<2> type;
   bits<7> gpr;
   bits<2> elem_size;
 
class ExportBufWord1 {
   bits<1> eop;
   bits<8> inst;
 
   let Word1{11-0} = arraySize;
   let Word1{15-12} = compMask;
 }
 
 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
-  def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
+  def : Pat<(R600_EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
     (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
         (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
         imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
   >;
 
 }
 
 multiclass SteamOutputExportPattern<Instruction ExportInst,

lib/Target/AMDGPU/SIISelLowering.cpp

case AMDGPUIntrinsic::SI_tbuffer_store: {
 
     MachineMemOperand *MMO = MF.getMachineMemOperand(
       MachinePointerInfo(),
       MachineMemOperand::MOStore,
       VT.getStoreSize(), 4);
     return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
                                    Op->getVTList(), Ops, VT, MMO);
   }
+
   case AMDGPUIntrinsic::AMDGPU_kill: {
     if (const ConstantFPSDNode *K = dyn_cast<ConstantFPSDNode>(Op.getOperand(2))) {
       if (!K->isNegative())
         return Chain;
     }
 
     return Op;
   }
+  case AMDGPUIntrinsic::SI_export: {
+    const ConstantSDNode *En = cast<ConstantSDNode>(Op.getOperand(2));
+    const ConstantSDNode *VM = cast<ConstantSDNode>(Op.getOperand(3));
+    const ConstantSDNode *Done = cast<ConstantSDNode>(Op.getOperand(4));
+    const ConstantSDNode *Tgt = cast<ConstantSDNode>(Op.getOperand(5));
+    const ConstantSDNode *Compr = cast<ConstantSDNode>(Op.getOperand(6));
+
+    const SDValue Ops[] = {
+      Chain,
+      DAG.getTargetConstant(En->getZExtValue(), DL, MVT::i32),
+      DAG.getTargetConstant(VM->getZExtValue(), DL, MVT::i32), // TODO: i1
+      DAG.getTargetConstant(Tgt->getZExtValue(), DL, MVT::i32),
+      DAG.getTargetConstant(Compr->getZExtValue(), DL, MVT::i32), // TODO: i1
+      Op.getOperand(7), // src0
+      Op.getOperand(8), // src1
+      Op.getOperand(9), // src2
+      Op.getOperand(10) // src3
+    };
+
+    unsigned Opc = Done->isNullValue() ?
+      AMDGPUISD::EXPORT : AMDGPUISD::EXPORT_DONE;
+    return DAG.getNode(Opc, DL, Op->getVTList(), Ops);
+  }
   default:
     return SDValue();
   }
 }
 
 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
   SDLoc DL(Op);
   LoadSDNode *Load = cast<LoadSDNode>(Op);

lib/Target/AMDGPU/SIInsertWaits.cpp

 
 Counters SIInsertWaits::getHwCounts(MachineInstr &MI) {
   uint64_t TSFlags = MI.getDesc().TSFlags;
   Counters Result = { { 0, 0, 0 } };
 
   Result.Named.VM = !!(TSFlags & SIInstrFlags::VM_CNT);
 
   // Only consider stores or EXP for EXP_CNT
-  Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT &&
-      (MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore()));
+  Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT) && MI.mayStore();
 
   // LGKM may uses larger values
   if (TSFlags & SIInstrFlags::LGKM_CNT) {
 
     if (TII->isSMRD(MI)) {
 
       if (MI.getNumOperands() != 0) {
         assert(MI.getOperand(0).isReg() &&

lib/Target/AMDGPU/SIInstrFormats.td

 
 class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
     InstSI <outs, ins, asm, pattern> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
 }
 
+class EXPCommon<dag outs, dag ins, string asm, list<dag> pattern> :
+  InstSI<outs, ins, asm, pattern> {
+  let EXP_CNT = 1;
+  let mayLoad = 0; // Set to 1 if done bit is set.
+  let mayStore = 1;
+  let UseNamedOperandTable = 1;
+  let Uses = [EXEC];
+  let SchedRW = [WriteExport];
+}
+
 } // End Uses = [EXEC]
 
 //===----------------------------------------------------------------------===//
 // Vector I/O operations
 //===----------------------------------------------------------------------===//
 
 class DS <dag outs, dag ins, string asm, list<dag> pattern> :
     InstSI <outs, ins, asm, pattern> {

lib/Target/AMDGPU/SIInstrInfo.td

 //
 //===----------------------------------------------------------------------===//
 
 class SIMCInstr <string pseudo, int subtarget> {
   string PseudoInstr = pseudo;
   int Subtarget = subtarget;
 }
 
 //===----------------------------------------------------------------------===//
-// EXP classes
-//===----------------------------------------------------------------------===//
-
-class EXPCommon : InstSI<
-  (outs),
-  (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
-       VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
-  "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
-  [] > {
-
-  let EXP_CNT = 1;
-  let Uses = [EXEC];
-  let SchedRW = [WriteExport];
-}
-
-multiclass EXP_m {
-
-  let isPseudo = 1, isCodeGenOnly = 1 in {
-    def "" : EXPCommon, SIMCInstr <"exp", SIEncodingFamily.NONE> ;
-  }
-
-  def _si : EXPCommon, SIMCInstr <"exp", SIEncodingFamily.SI>, EXPe {
-    let DecoderNamespace="SICI";
-    let DisableDecoder = DisableSIDecoder;
-  }
-
-  def _vi : EXPCommon, SIMCInstr <"exp", SIEncodingFamily.VI>, EXPe_vi {
-    let DecoderNamespace="VI";
-    let DisableDecoder = DisableVIDecoder;
-  }
-}
-
-//===----------------------------------------------------------------------===//
 // Scalar classes
 //===----------------------------------------------------------------------===//
 
 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
   SOP1 <outs, ins, "", pattern>,
   SIMCInstr<opName, SIEncodingFamily.NONE> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
   def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
 
   def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
 
   def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
 }
 
 //===----------------------------------------------------------------------===//
+// Export opcodes
+//===----------------------------------------------------------------------===//
+
+class EXP_Helper<bit done, SDPatternOperator node = null_frag> : EXPCommon<
+  (outs),
+  (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$vm,
+       VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
+  "exp $en, $tgt, $compr, "#!if(done, "1", "0")#", $vm, $src0, $src1, $src2, $src3",
+  [(node (i32 timm:$en), (i32 timm:$vm), (i32 timm:$tgt), (i32 timm:$compr),
+         f32:$src0, f32:$src1, f32:$src2, f32:$src3)]
+>;
+
+// Split EXP instruction into EXP and EXP_DONE so we can set
+// hasSideEffects for done=1.
+multiclass EXP_m<bit done, SDPatternOperator node> {
+  let mayLoad = done in {
+    let isPseudo = 1, isCodeGenOnly = 1 in {
+      def "" : EXP_Helper<done, node>,
+               SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.NONE>;
+    }
+
+    let done = done in {
+      def _si : EXP_Helper<done>,
+                SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.SI>,
+                EXPe {
+        let DecoderNamespace = "SICI";
+        let DisableDecoder = DisableSIDecoder;
+      }
+
+      def _vi : EXP_Helper<done>,
+                SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.VI>,
+                EXPe_vi {
+        let DecoderNamespace = "VI";
+        let DisableDecoder = DisableVIDecoder;
+      }
+    }
+  }
+}
+
+//===----------------------------------------------------------------------===//
 // Vector I/O classes
 //===----------------------------------------------------------------------===//
 
 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
   DS <outs, ins, "", pattern>,
   SIMCInstr <opName, SIEncodingFamily.NONE> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;

lib/Target/AMDGPU/SIInstructions.td

 def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
 
 let SubtargetPredicate = isGCN in {
 
 //===----------------------------------------------------------------------===//
 // EXP Instructions
 //===----------------------------------------------------------------------===//
 
-defm EXP : EXP_m;
+defm EXP : EXP_m<0, AMDGPUexport>;
+defm EXP_DONE : EXP_m<1, AMDGPUexport_done>;
 
 //===----------------------------------------------------------------------===//
 // SMRD Instructions
 //===----------------------------------------------------------------------===//
 
 // We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit
 // SMRD instructions, because the SReg_32_XM0 register class does not include M0
 // and writing to M0 from an SMRD instruction will hang the GPU.

 >;
 
 /* int_SI_vs_load_input */
 def : Pat<
   (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
   (BUFFER_LOAD_FORMAT_XYZW_IDXEN $buf_idx_vgpr, $tlst, 0, imm:$attr_offset, 0, 0, 0)
 >;
 
-def : Pat <
-  (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
-                 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
-  (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
-       $src0, $src1, $src2, $src3)
->;
-
 //===----------------------------------------------------------------------===//
 // buffer_load/store_format patterns
 //===----------------------------------------------------------------------===//
 
 multiclass MUBUF_LoadIntrinsicPat<SDPatternOperator name, ValueType vt,
                                   string opcode> {
   def : Pat<
     (vt (name v4i32:$rsrc, 0,

lib/Target/AMDGPU/SIIntrinsics.td

 //===-- SIIntrinsics.td - SI Intrinsic defs ----------------*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // SI Intrinsic Definitions
 //
 //===----------------------------------------------------------------------===//
 
 
 let TargetPrefix = "SI", isTarget = 1 in {
   def int_SI_packf16 : Intrinsic <[llvm_i32_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
-  def int_SI_export : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], []>;
+
+  def int_SI_export : Intrinsic <[],
+    [llvm_i32_ty,   // en
+    llvm_i32_ty,    // vm   (FIXME: should be i1)
+    llvm_i32_ty,    // done (FIXME: should be i1)
+    llvm_i32_ty,    // tgt
+    llvm_i32_ty,    // compr (FIXME: should be i1)
+    llvm_float_ty,  // src0
+    llvm_float_ty,  // src1
+    llvm_float_ty,  // src2
+    llvm_float_ty], // src3
+    []
+  >;
+
   def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
   def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_anyint_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ;
 
   // Fully-flexible TBUFFER_STORE_FORMAT_* except for the ADDR64 bit, which is not exposed
   def int_SI_tbuffer_store : Intrinsic <
     [],
     [llvm_anyint_ty, // rsrc(SGPR)
      llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32

lib/Target/AMDGPU/SILowerControlFlow.cpp

bool SILowerControlFlow::skipIfDead(MachineInstr &MI, MachineBasicBlock &NextBB) {
 
   // If the exec mask is non-zero, skip the next two instructions
   BuildMI(&MBB, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
     .addMBB(&NextBB);
 
   MachineBasicBlock::iterator Insert = SkipBB->begin();
 
   // Exec mask is zero: Export to NULL target...
-  BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::EXP))
+  BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::EXP_DONE))
     .addImm(0)
     .addImm(0x09) // V_008DFC_SQ_EXP_NULL
     .addImm(0)
     .addImm(1)
-    .addImm(1)
     .addReg(AMDGPU::VGPR0, RegState::Undef)
     .addReg(AMDGPU::VGPR0, RegState::Undef)
     .addReg(AMDGPU::VGPR0, RegState::Undef)
     .addReg(AMDGPU::VGPR0, RegState::Undef);
 
   // ... and terminate wavefront.
   BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
 

lib/Target/AMDGPU/SIWholeQuadMode.cpp

for (auto II = MBB.begin(), IE = MBB.end(); II != IE; ++II) {
       char Flags = 0;
 
       if (TII->isWQM(Opcode) || TII->isDS(Opcode)) {
         Flags = StateWQM;
       } else if (MI.mayStore() && TII->usesVM_CNT(MI)) {
         Flags = StateExact;
       } else {
         // Handle export instructions with the exec mask valid flag set
-        if (Opcode == AMDGPU::EXP) {
-          if (MI.getOperand(4).getImm() != 0)
+        if (Opcode == AMDGPU::EXP || Opcode == AMDGPU::EXP_DONE) {
+          if (TII->hasModifiersSet(MI, AMDGPU::OpName::vm))
             ExecExports.push_back(&MI);
         } else if (Opcode == AMDGPU::SI_PS_LIVE) {
           LiveMaskQueries.push_back(&MI);
         } else if (WQMOutputs) {
           // The function is in machine SSA form, which means that physical
           // VGPRs correspond to shader inputs and outputs. Inputs are
           // only used, outputs are only defined.
           for (const MachineOperand &MO : MI.defs()) {