Revert "[SystemZ][z/OS] Fix f32 variadic argument assertion"

[mubarizafzal]

Summary

This patch reverts the f32 vararg fix (https://reviews.llvm.org/D119868) which had a test case that failed on different buildbots (ex. Link)

[thakis]

No need to have reverts reviewed. If you land something and it breaks tests, just land the revert. That's better than keeping the tree red.

(lg – please land this quickly :) )

[thakis]

this landed in 1a5b881d4cf0

[mubarizafzal]

In D119906#3325175, @thakis wrote:

No need to have reverts reviewed. If you land something and it breaks tests, just land the revert. That's better than keeping the tree red.

(lg – please land this quickly :) )

Ah makes sense. Thanks for the help !

llvm/lib/Target/SystemZ/SystemZCallingConv.td

 // The XPLINK64 Calling Convention is fully specified in Chapter 22 of the z/OS
 // Language Environment Vendor Interfaces. Appendix B of the same document contains
 // examples.
 
 def CC_SystemZ_XPLINK64 : CallingConv<[
   // XPLINK64 ABI compliant code widens integral types smaller than i64
   // to i64 before placing the parameters either on the stack or in registers.
   CCIfType<[i32], CCIfExtend<CCPromoteToType<i64>>>,
-  // Promote f32 to f64 and bitcast to i64, if it needs to be passed in GPRs.
-  // Although we assign the f32 vararg to be bitcast, it will first be promoted
-  // to an f64 within convertValVTToLocVT().
-  CCIfType<[f32, f64], CCIfNotFixed<CCBitConvertToType<i64>>>,
+  // Promote f32 to f64 and bitcast to i64, if it needs to be passed in GPRS.
+  CCIfType<[f32], CCIfNotFixed<CCPromoteToType<f64>>>,
+  CCIfType<[f64], CCIfNotFixed<CCBitConvertToType<i64>>>,
   // long double, can only be passed in GPR2 and GPR3, if available,
   // hence R2Q
   CCIfType<[f128], CCIfNotFixed<CCCustom<"CC_XPLINK64_Allocate128BitVararg">>>,
   // Non fixed vector arguments are treated in the same way as long
   // doubles.
   CCIfSubtarget<"hasVector()",
     CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
       CCIfNotFixed<CCCustom<"CC_XPLINK64_Allocate128BitVararg">>>>,

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

static SDValue convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL,
   case CCValAssign::SExt:
     return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
   case CCValAssign::ZExt:
     return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
   case CCValAssign::AExt:
     return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
   case CCValAssign::BCvt: {
     assert(VA.getLocVT() == MVT::i64 || VA.getLocVT() == MVT::i128);
-    assert(VA.getValVT().isVector() || VA.getValVT() == MVT::f32 ||
-           VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::f128);
-    // For an f32 vararg we need to first promote it to an f64 and then
-    // bitcast it to an i64.
-    if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i64)
-      Value = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f64, Value);
+    assert(VA.getValVT().isVector() || VA.getValVT() == MVT::f64 ||
+           VA.getValVT() == MVT::f128);
     MVT BitCastToType = VA.getValVT().isVector() && VA.getLocVT() == MVT::i64
                             ? MVT::v2i64
                             : VA.getLocVT();
     Value = DAG.getNode(ISD::BITCAST, DL, BitCastToType, Value);
     // For ELF, this is a short vector argument to be stored to the stack,
     // bitcast to v2i64 and then extract first element.
     if (BitCastToType == MVT::v2i64)
       return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value,

llvm/test/CodeGen/SystemZ/call-zos-vararg.ll

 ; CHECK-NOT: lg  3
 ; CHECK-NOT: lgr  3
 define i64 @call_vararg_integral0(i32 signext %arg0, i16 signext %arg1, i64 signext %arg2, i8 signext %arg3) {
 entry:
   %retval = call i64(...) @pass_vararg3(i32 signext %arg0, i16 signext %arg1, i64 signext %arg2, i8 signext %arg3)
   ret i64 %retval
 }
 
-; CHECK-LABEL: call_vararg_float0
-; CHECK:       lghi  1, 1
-; CHECK:       llihf 2, 1073692672
-define i64 @call_vararg_float0() {
-entry:
-  %retval = call i64 (i64, ...) @pass_vararg2(i64 1, float 1.953125)
-  ret i64 %retval
-}
-
-; CHECK-LABEL: call_vararg_float1
-; CHECK:       llihf 0, 1073692672
-; CHECK-NEXT:  stg  0, 2200(4)
-; CHECK:       larl  1, @CPI21_0
-; CHECK-NEXT:  le  0, 0(1)
-; CHECK:       llihh 2, 16384
-; CHECK:       llihh 3, 16392
-define i64 @call_vararg_float1() {
-entry:
-  %retval = call i64 (float, ...) @pass_vararg4(float 1.0, float 2.0, float 3.0, float 1.953125)
-  ret i64 %retval
-}
-
 declare i64 @pass_vararg0(i64 %arg0, i64 %arg1, ...)
 declare i64 @pass_vararg1(fp128 %arg0, ...)
 declare i64 @pass_vararg2(i64 %arg0, ...)
 declare i64 @pass_vararg3(...)
-declare i64 @pass_vararg4(float, ...)