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Differential D119813

[LoongArch] Add missing dollar prefix to register name in InstPrinter
ClosedPublic

Authored by SixWeining on Feb 15 2022, 12:53 AM.

Details

Reviewers
rengolin
xen0n
myhsu
Commits
rG1d91537ce872: [LoongArch] Add missing dollar prefix to register name in InstPrinter
Summary

This patch adds a '$' prefix to register name in InstPrinter that I missed in initial patches.

Diff Detail

Event Timeline

SixWeining created this revision.Feb 15 2022, 12:53 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptFeb 15 2022, 12:53 AM
SixWeining requested review of this revision.Feb 15 2022, 12:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 15 2022, 12:53 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
SixWeining added a child revision: D119817: [LoongArch] Fix several instruction definition errors in initial patches.Feb 15 2022, 1:21 AM
Harbormaster completed remote builds in B149610: Diff 408746.Feb 15 2022, 1:40 AM
xen0n accepted this revision.Feb 15 2022, 1:47 AM

LGTM, that's a bit hard for me to catch!

(me being way too familiar with RISC-V assembly, where unprefixed register names are okay to use)

This revision is now accepted and ready to land.Feb 15 2022, 1:47 AM
This revision was landed with ongoing or failed builds.Feb 17 2022, 5:57 PM
Closed by commit rG1d91537ce872: [LoongArch] Add missing dollar prefix to register name in InstPrinter (authored by SixWeining). · Explain Why
This revision was automatically updated to reflect the committed changes.
SixWeining added a commit: rG1d91537ce872: [LoongArch] Add missing dollar prefix to register name in InstPrinter.

Revision Contents

PathSize
llvm/
lib/
Target/
LoongArch/
MCTargetDesc/
2 lines
test/
CodeGen/
LoongArch/
16 lines
48 lines
84 lines
218 lines
10 lines
16 lines

Diff 409827

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp

Show All 29 Linesvoid LoongArchInstPrinter::printInst(const MCInst *MI, uint64_t Address,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
if (!printAliasInstr(MI, Address, STI, O)) if (!printAliasInstr(MI, Address, STI, O))
printInstruction(MI, Address, STI, O); printInstruction(MI, Address, STI, O);
printAnnotation(O, Annot); printAnnotation(O, Annot);
} }
void LoongArchInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const { void LoongArchInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
O << getRegisterName(RegNo); O << '$' << getRegisterName(RegNo);
} }
void LoongArchInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, void LoongArchInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNo); const MCOperand &MO = MI->getOperand(OpNo);
if (MO.isReg()) { if (MO.isReg()) {
Show All 17 Lines

llvm/test/CodeGen/LoongArch/1ri.mir

Show All 10 Lines
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ---------------------+-----------------------------------------------------------+--------------- # ---------------------+-----------------------------------------------------------+---------------
# opcode | imm20 | rd # opcode | imm20 | rd
# ---------------------+-----------------------------------------------------------+--------------- # ---------------------+-----------------------------------------------------------+---------------
--- ---
# CHECK-LABEL: test_LU12I_W: # CHECK-LABEL: test_LU12I_W:
# CHECK-ENC: 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0
# CHECK-ASM: lu12i.w a0, 49 # CHECK-ASM: lu12i.w $a0, 49
name: test_LU12I_W name: test_LU12I_W
body: | body: |
bb.0: bb.0:
$r4 = LU12I_W 49 $r4 = LU12I_W 49
... ...
--- ---
# CHECK-LABEL: test_LU32I_D: # CHECK-LABEL: test_LU32I_D:
# CHECK-ENC: 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 # CHECK-ENC: 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0
# CHECK-ASM: lu32i.d a0, 196 # CHECK-ASM: lu32i.d $a0, 196
name: test_LU32I_D name: test_LU32I_D
body: | body: |
bb.0: bb.0:
$r4 = LU32I_D 196 $r4 = LU32I_D 196
... ...
--- ---
# CHECK-LABEL: test_PCADDI: # CHECK-LABEL: test_PCADDI:
# CHECK-ENC: 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0
# CHECK-ASM: pcaddi a0, 187 # CHECK-ASM: pcaddi $a0, 187
name: test_PCADDI name: test_PCADDI
body: | body: |
bb.0: bb.0:
$r4 = PCADDI 187 $r4 = PCADDI 187
... ...
--- ---
# CHECK-LABEL: test_PCALAU12I: # CHECK-LABEL: test_PCALAU12I:
# CHECK-ENC: 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0
# CHECK-ASM: pcalau12i a0, 89 # CHECK-ASM: pcalau12i $a0, 89
name: test_PCALAU12I name: test_PCALAU12I
body: | body: |
bb.0: bb.0:
$r4 = PCALAU12I 89 $r4 = PCALAU12I 89
... ...
--- ---
# CHECK-LABEL: test_PCADDU12I: # CHECK-LABEL: test_PCADDU12I:
# CHECK-ENC: 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: pcaddu12i a0, 37 # CHECK-ASM: pcaddu12i $a0, 37
name: test_PCADDU12I name: test_PCADDU12I
body: | body: |
bb.0: bb.0:
$r4 = PCADDU12I 37 $r4 = PCADDU12I 37
... ...
--- ---
# CHECK-LABEL: test_PCADDU18I: # CHECK-LABEL: test_PCADDU18I:
# CHECK-ENC: 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 # CHECK-ENC: 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0
# CHECK-ASM: pcaddu18i a0, 26 # CHECK-ASM: pcaddu18i $a0, 26
name: test_PCADDU18I name: test_PCADDU18I
body: | body: |
bb.0: bb.0:
$r4 = PCADDU18I 26 $r4 = PCADDU18I 26
... ...
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# Encoding format: 1RI21 # Encoding format: 1RI21
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# ------------------+-----------------------------------------------+--------------+--------------- # ------------------+-----------------------------------------------+--------------+---------------
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ------------------+-----------------------------------------------+--------------+--------------- # ------------------+-----------------------------------------------+--------------+---------------
# opcode | imm21{15-0} | rj | imm21{20-16} # opcode | imm21{15-0} | rj | imm21{20-16}
# ------------------+-----------------------------------------------+--------------+--------------- # ------------------+-----------------------------------------------+--------------+---------------
--- ---
# CHECK-LABEL: test_BEQZ: # CHECK-LABEL: test_BEQZ:
# CHECK-ENC: 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 # CHECK-ENC: 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0
# CHECK-ASM: beqz a0, 23 # CHECK-ASM: beqz $a0, 23
name: test_BEQZ name: test_BEQZ
body: | body: |
bb.0: bb.0:
BEQZ $r4, 23 BEQZ $r4, 23
... ...
--- ---
# CHECK-LABEL: test_BNEZ: # CHECK-LABEL: test_BNEZ:
# CHECK-ENC: 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 # CHECK-ENC: 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0
# CHECK-ASM: bnez a0, 21 # CHECK-ASM: bnez $a0, 21
name: test_BNEZ name: test_BNEZ
body: | body: |
bb.0: bb.0:
BNEZ $r4, 21 BNEZ $r4, 21

llvm/test/CodeGen/LoongArch/2r.mir

Show All 10 Lines
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ------------------------------------------------------------------+--------------+--------------- # ------------------------------------------------------------------+--------------+---------------
# opcode | rj | rd # opcode | rj | rd
# ------------------------------------------------------------------+--------------+--------------- # ------------------------------------------------------------------+--------------+---------------
--- ---
# CHECK-LABEL: test_CLO_W: # CHECK-LABEL: test_CLO_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: clo.w a0, a1 # CHECK-ASM: clo.w $a0, $a1
name: test_CLO_W name: test_CLO_W
body: | body: |
bb.0: bb.0:
$r4 = CLO_W $r5 $r4 = CLO_W $r5
... ...
--- ---
# CHECK-LABEL: test_CLZ_W: # CHECK-LABEL: test_CLZ_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: clz.w a0, a1 # CHECK-ASM: clz.w $a0, $a1
name: test_CLZ_W name: test_CLZ_W
body: | body: |
bb.0: bb.0:
$r4 = CLZ_W $r5 $r4 = CLZ_W $r5
... ...
--- ---
# CHECK-LABEL: test_CTO_W: # CHECK-LABEL: test_CTO_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: cto.w a0, a1 # CHECK-ASM: cto.w $a0, $a1
name: test_CTO_W name: test_CTO_W
body: | body: |
bb.0: bb.0:
$r4 = CTO_W $r5 $r4 = CTO_W $r5
... ...
--- ---
# CHECK-LABEL: test_CTZ_W: # CHECK-LABEL: test_CTZ_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ctz.w a0, a1 # CHECK-ASM: ctz.w $a0, $a1
name: test_CTZ_W name: test_CTZ_W
body: | body: |
bb.0: bb.0:
$r4 = CTZ_W $r5 $r4 = CTZ_W $r5
... ...
--- ---
# CHECK-LABEL: test_CLO_D: # CHECK-LABEL: test_CLO_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: clo.d a0, a1 # CHECK-ASM: clo.d $a0, $a1
name: test_CLO_D name: test_CLO_D
body: | body: |
bb.0: bb.0:
$r4 = CLO_D $r5 $r4 = CLO_D $r5
... ...
--- ---
# CHECK-LABEL: test_CLZ_D: # CHECK-LABEL: test_CLZ_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: clz.d a0, a1 # CHECK-ASM: clz.d $a0, $a1
name: test_CLZ_D name: test_CLZ_D
body: | body: |
bb.0: bb.0:
$r4 = CLZ_D $r5 $r4 = CLZ_D $r5
... ...
--- ---
# CHECK-LABEL: test_CTO_D: # CHECK-LABEL: test_CTO_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: cto.d a0, a1 # CHECK-ASM: cto.d $a0, $a1
name: test_CTO_D name: test_CTO_D
body: | body: |
bb.0: bb.0:
$r4 = CTO_D $r5 $r4 = CTO_D $r5
... ...
--- ---
# CHECK-LABEL: test_CTZ_D: # CHECK-LABEL: test_CTZ_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ctz.d a0, a1 # CHECK-ASM: ctz.d $a0, $a1
name: test_CTZ_D name: test_CTZ_D
body: | body: |
bb.0: bb.0:
$r4 = CTZ_D $r5 $r4 = CTZ_D $r5
... ...
--- ---
# CHECK-LABEL: test_REVB_2H: # CHECK-LABEL: test_REVB_2H:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: revb.2h a0, a1 # CHECK-ASM: revb.2h $a0, $a1
name: test_REVB_2H name: test_REVB_2H
body: | body: |
bb.0: bb.0:
$r4 = REVB_2H $r5 $r4 = REVB_2H $r5
... ...
--- ---
# CHECK-LABEL: test_REVB_4H: # CHECK-LABEL: test_REVB_4H:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: revb.4h a0, a1 # CHECK-ASM: revb.4h $a0, $a1
name: test_REVB_4H name: test_REVB_4H
body: | body: |
bb.0: bb.0:
$r4 = REVB_4H $r5 $r4 = REVB_4H $r5
... ...
--- ---
# CHECK-LABEL: test_REVB_2W: # CHECK-LABEL: test_REVB_2W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: revb.2w a0, a1 # CHECK-ASM: revb.2w $a0, $a1
name: test_REVB_2W name: test_REVB_2W
body: | body: |
bb.0: bb.0:
$r4 = REVB_2W $r5 $r4 = REVB_2W $r5
... ...
--- ---
# CHECK-LABEL: test_REVB_D: # CHECK-LABEL: test_REVB_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: revb.d a0, a1 # CHECK-ASM: revb.d $a0, $a1
name: test_REVB_D name: test_REVB_D
body: | body: |
bb.0: bb.0:
$r4 = REVB_D $r5 $r4 = REVB_D $r5
... ...
--- ---
# CHECK-LABEL: test_REVH_2W: # CHECK-LABEL: test_REVH_2W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: revh.2w a0, a1 # CHECK-ASM: revh.2w $a0, $a1
name: test_REVH_2W name: test_REVH_2W
body: | body: |
bb.0: bb.0:
$r4 = REVH_2W $r5 $r4 = REVH_2W $r5
... ...
--- ---
# CHECK-LABEL: test_REVH_D: # CHECK-LABEL: test_REVH_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: revh.d a0, a1 # CHECK-ASM: revh.d $a0, $a1
name: test_REVH_D name: test_REVH_D
body: | body: |
bb.0: bb.0:
$r4 = REVH_D $r5 $r4 = REVH_D $r5
... ...
--- ---
# CHECK-LABEL: test_BITREV_4B: # CHECK-LABEL: test_BITREV_4B:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: bitrev.4b a0, a1 # CHECK-ASM: bitrev.4b $a0, $a1
name: test_BITREV_4B name: test_BITREV_4B
body: | body: |
bb.0: bb.0:
$r4 = BITREV_4B $r5 $r4 = BITREV_4B $r5
... ...
--- ---
# CHECK-LABEL: test_BITREV_8B: # CHECK-LABEL: test_BITREV_8B:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: bitrev.8b a0, a1 # CHECK-ASM: bitrev.8b $a0, $a1
name: test_BITREV_8B name: test_BITREV_8B
body: | body: |
bb.0: bb.0:
$r4 = BITREV_8B $r5 $r4 = BITREV_8B $r5
... ...
--- ---
# CHECK-LABEL: test_BITREV_W: # CHECK-LABEL: test_BITREV_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: bitrev.w a0, a1 # CHECK-ASM: bitrev.w $a0, $a1
name: test_BITREV_W name: test_BITREV_W
body: | body: |
bb.0: bb.0:
$r4 = BITREV_W $r5 $r4 = BITREV_W $r5
... ...
--- ---
# CHECK-LABEL: test_BITREV_D: # CHECK-LABEL: test_BITREV_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: bitrev.d a0, a1 # CHECK-ASM: bitrev.d $a0, $a1
name: test_BITREV_D name: test_BITREV_D
body: | body: |
bb.0: bb.0:
$r4 = BITREV_D $r5 $r4 = BITREV_D $r5
... ...
--- ---
# CHECK-LABEL: test_EXT_W_H: # CHECK-LABEL: test_EXT_W_H:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ext.w.h a0, a1 # CHECK-ASM: ext.w.h $a0, $a1
name: test_EXT_W_H name: test_EXT_W_H
body: | body: |
bb.0: bb.0:
$r4 = EXT_W_H $r5 $r4 = EXT_W_H $r5
... ...
--- ---
# CHECK-LABEL: test_EXT_W_B: # CHECK-LABEL: test_EXT_W_B:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ext.w.b a0, a1 # CHECK-ASM: ext.w.b $a0, $a1
name: test_EXT_W_B name: test_EXT_W_B
body: | body: |
bb.0: bb.0:
$r4 = EXT_W_B $r5 $r4 = EXT_W_B $r5
... ...
--- ---
# CHECK-LABEL: test_CPUCFG: # CHECK-LABEL: test_CPUCFG:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: cpucfg a0, a1 # CHECK-ASM: cpucfg $a0, $a1
name: test_CPUCFG name: test_CPUCFG
body: | body: |
bb.0: bb.0:
$r4 = CPUCFG $r5 $r4 = CPUCFG $r5
... ...
--- ---
# CHECK-LABEL: test_RDTIMEL_W: # CHECK-LABEL: test_RDTIMEL_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: rdtimel.w a0, a1 # CHECK-ASM: rdtimel.w $a0, $a1
name: test_RDTIMEL_W name: test_RDTIMEL_W
body: | body: |
bb.0: bb.0:
$r4, $r5 = RDTIMEL_W $r4, $r5 = RDTIMEL_W
... ...
--- ---
# CHECK-LABEL: test_RDTIMEH_W: # CHECK-LABEL: test_RDTIMEH_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: rdtimeh.w a0, a1 # CHECK-ASM: rdtimeh.w $a0, $a1
name: test_RDTIMEH_W name: test_RDTIMEH_W
body: | body: |
bb.0: bb.0:
$r4, $r5 = RDTIMEH_W $r4, $r5 = RDTIMEH_W
... ...
--- ---
# CHECK-LABEL: test_RDTIME_D: # CHECK-LABEL: test_RDTIME_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: rdtime.d a0, a1 # CHECK-ASM: rdtime.d $a0, $a1
name: test_RDTIME_D name: test_RDTIME_D
body: | body: |
bb.0: bb.0:
$r4, $r5 = RDTIME_D $r4, $r5 = RDTIME_D

llvm/test/CodeGen/LoongArch/2ri.mir

Show All 10 Lines
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ---------------------------------------------------+--------------+--------------+--------------- # ---------------------------------------------------+--------------+--------------+---------------
# opcode | imm5 | rj | rd # opcode | imm5 | rj | rd
# ---------------------------------------------------+--------------+--------------+--------------- # ---------------------------------------------------+--------------+--------------+---------------
--- ---
# CHECK-LABEL: test_SLLI_W: # CHECK-LABEL: test_SLLI_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: slli.w a0, a1, 0 # CHECK-ASM: slli.w $a0, $a1, 0
name: test_SLLI_W name: test_SLLI_W
body: | body: |
bb.0: bb.0:
$r4 = SLLI_W $r5, 0 $r4 = SLLI_W $r5, 0
... ...
--- ---
# CHECK-LABEL: test_SRLI_W: # CHECK-LABEL: test_SRLI_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: srli.w a0, a1, 30 # CHECK-ASM: srli.w $a0, $a1, 30
name: test_SRLI_W name: test_SRLI_W
body: | body: |
bb.0: bb.0:
$r4 = SRLI_W $r5, 30 $r4 = SRLI_W $r5, 30
... ...
--- ---
# CHECK-LABEL: test_SRAI_W: # CHECK-LABEL: test_SRAI_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: srai.w a0, a1, 24 # CHECK-ASM: srai.w $a0, $a1, 24
name: test_SRAI_W name: test_SRAI_W
body: | body: |
bb.0: bb.0:
$r4 = SRAI_W $r5, 24 $r4 = SRAI_W $r5, 24
... ...
--- ---
# CHECK-LABEL: test_ROTRI_W: # CHECK-LABEL: test_ROTRI_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: rotri.w a0, a1, 23 # CHECK-ASM: rotri.w $a0, $a1, 23
name: test_ROTRI_W name: test_ROTRI_W
body: | body: |
bb.0: bb.0:
$r4 = ROTRI_W $r5, 23 $r4 = ROTRI_W $r5, 23
... ...
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# Encoding format: 2RI6 # Encoding format: 2RI6
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# ------------------------------------------------+-----------------+--------------+--------------- # ------------------------------------------------+-----------------+--------------+---------------
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ------------------------------------------------+-----------------+--------------+--------------- # ------------------------------------------------+-----------------+--------------+---------------
# opcode | imm6 | rj | rd # opcode | imm6 | rj | rd
# ------------------------------------------------+-----------------+--------------+--------------- # ------------------------------------------------+-----------------+--------------+---------------
--- ---
# CHECK-LABEL: test_SLLI_D: # CHECK-LABEL: test_SLLI_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: slli.d a0, a1, 39 # CHECK-ASM: slli.d $a0, $a1, 39
name: test_SLLI_D name: test_SLLI_D
body: | body: |
bb.0: bb.0:
$r4 = SLLI_D $r5, 39 $r4 = SLLI_D $r5, 39
... ...
--- ---
# CHECK-LABEL: test_SRLI_D: # CHECK-LABEL: test_SRLI_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: srli.d a0, a1, 38 # CHECK-ASM: srli.d $a0, $a1, 38
name: test_SRLI_D name: test_SRLI_D
body: | body: |
bb.0: bb.0:
$r4 = SRLI_D $r5, 38 $r4 = SRLI_D $r5, 38
... ...
--- ---
# CHECK-LABEL: test_SRAI_D: # CHECK-LABEL: test_SRAI_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: srai.d a0, a1, 27 # CHECK-ASM: srai.d $a0, $a1, 27
name: test_SRAI_D name: test_SRAI_D
body: | body: |
bb.0: bb.0:
$r4 = SRAI_D $r5, 27 $r4 = SRAI_D $r5, 27
... ...
--- ---
# CHECK-LABEL: test_ROTRI_D: # CHECK-LABEL: test_ROTRI_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: rotri.d a0, a1, 7 # CHECK-ASM: rotri.d $a0, $a1, 7
name: test_ROTRI_D name: test_ROTRI_D
body: | body: |
bb.0: bb.0:
$r4 = ROTRI_D $r5, 7 $r4 = ROTRI_D $r5, 7
... ...
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# Encoding format: 2RI12 # Encoding format: 2RI12
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# ------------------------------+-----------------------------------+--------------+--------------- # ------------------------------+-----------------------------------+--------------+---------------
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ------------------------------+-----------------------------------+--------------+--------------- # ------------------------------+-----------------------------------+--------------+---------------
# opcode | imm12 | rj | rd # opcode | imm12 | rj | rd
# ------------------------------+-----------------------------------+--------------+--------------- # ------------------------------+-----------------------------------+--------------+---------------
--- ---
# CHECK-LABEL: test_SLTI: # CHECK-LABEL: test_SLTI:
# CHECK-ENC: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: slti a0, a1, 235 # CHECK-ASM: slti $a0, $a1, 235
name: test_SLTI name: test_SLTI
body: | body: |
bb.0: bb.0:
$r4 = SLTI $r5, 235 $r4 = SLTI $r5, 235
... ...
--- ---
# CHECK-LABEL: test_SLTUI: # CHECK-LABEL: test_SLTUI:
# CHECK-ENC: 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: sltui a0, a1, 162 # CHECK-ASM: sltui $a0, $a1, 162
name: test_SLTUI name: test_SLTUI
body: | body: |
bb.0: bb.0:
$r4 = SLTUI $r5, 162 $r4 = SLTUI $r5, 162
... ...
--- ---
# CHECK-LABEL: test_ADDI_W: # CHECK-LABEL: test_ADDI_W:
# CHECK-ENC: 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: addi.w a0, a1, 246 # CHECK-ASM: addi.w $a0, $a1, 246
name: test_ADDI_W name: test_ADDI_W
body: | body: |
bb.0: bb.0:
$r4 = ADDI_W $r5, 246 $r4 = ADDI_W $r5, 246
... ...
--- ---
# CHECK-LABEL: test_ADDI_D: # CHECK-LABEL: test_ADDI_D:
# CHECK-ENC: 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: addi.d a0, a1, 75 # CHECK-ASM: addi.d $a0, $a1, 75
name: test_ADDI_D name: test_ADDI_D
body: | body: |
bb.0: bb.0:
$r4 = ADDI_D $r5, 75 $r4 = ADDI_D $r5, 75
... ...
--- ---
# CHECK-LABEL: test_LU52I_D: # CHECK-LABEL: test_LU52I_D:
# CHECK-ENC: 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: lu52i.d a0, a1, 195 # CHECK-ASM: lu52i.d $a0, $a1, 195
name: test_LU52I_D name: test_LU52I_D
body: | body: |
bb.0: bb.0:
$r4 = LU52I_D $r5, 195 $r4 = LU52I_D $r5, 195
... ...
--- ---
# CHECK-LABEL: test_ANDI: # CHECK-LABEL: test_ANDI:
# CHECK-ENC: 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: andi a0, a1, 106 # CHECK-ASM: andi $a0, $a1, 106
name: test_ANDI name: test_ANDI
body: | body: |
bb.0: bb.0:
$r4 = ANDI $r5, 106 $r4 = ANDI $r5, 106
... ...
--- ---
# CHECK-LABEL: test_ORI: # CHECK-LABEL: test_ORI:
# CHECK-ENC: 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ori a0, a1, 47 # CHECK-ASM: ori $a0, $a1, 47
name: test_ORI name: test_ORI
body: | body: |
bb.0: bb.0:
$r4 = ORI $r5, 47 $r4 = ORI $r5, 47
... ...
--- ---
# CHECK-LABEL: test_XORI: # CHECK-LABEL: test_XORI:
# CHECK-ENC: 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: xori a0, a1, 99 # CHECK-ASM: xori $a0, $a1, 99
name: test_XORI name: test_XORI
body: | body: |
bb.0: bb.0:
$r4 = XORI $r5, 99 $r4 = XORI $r5, 99
... ...
--- ---
# CHECK-LABEL: test_LD_B: # CHECK-LABEL: test_LD_B:
# CHECK-ENC: 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ld.b a0, a1, 21 # CHECK-ASM: ld.b $a0, $a1, 21
name: test_LD_B name: test_LD_B
body: | body: |
bb.0: bb.0:
$r4 = LD_B $r5, 21 $r4 = LD_B $r5, 21
... ...
--- ---
# CHECK-LABEL: test_LD_H: # CHECK-LABEL: test_LD_H:
# CHECK-ENC: 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ld.h a0, a1, 80 # CHECK-ASM: ld.h $a0, $a1, 80
name: test_LD_H name: test_LD_H
body: | body: |
bb.0: bb.0:
$r4 = LD_H $r5, 80 $r4 = LD_H $r5, 80
... ...
--- ---
# CHECK-LABEL: test_LD_W: # CHECK-LABEL: test_LD_W:
# CHECK-ENC: 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ld.w a0, a1, 92 # CHECK-ASM: ld.w $a0, $a1, 92
name: test_LD_W name: test_LD_W
body: | body: |
bb.0: bb.0:
$r4 = LD_W $r5, 92 $r4 = LD_W $r5, 92
... ...
--- ---
# CHECK-LABEL: test_LD_BU: # CHECK-LABEL: test_LD_BU:
# CHECK-ENC: 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ld.bu a0, a1, 150 # CHECK-ASM: ld.bu $a0, $a1, 150
name: test_LD_BU name: test_LD_BU
body: | body: |
bb.0: bb.0:
$r4 = LD_BU $r5, 150 $r4 = LD_BU $r5, 150
... ...
--- ---
# CHECK-LABEL: test_LD_HU: # CHECK-LABEL: test_LD_HU:
# CHECK-ENC: 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ld.hu a0, a1, 198 # CHECK-ASM: ld.hu $a0, $a1, 198
name: test_LD_HU name: test_LD_HU
body: | body: |
bb.0: bb.0:
$r4 = LD_HU $r5, 198 $r4 = LD_HU $r5, 198
... ...
--- ---
# CHECK-LABEL: test_LD_WU: # CHECK-LABEL: test_LD_WU:
# CHECK-ENC: 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ld.wu a0, a1, 31 # CHECK-ASM: ld.wu $a0, $a1, 31
name: test_LD_WU name: test_LD_WU
body: | body: |
bb.0: bb.0:
$r4 = LD_WU $r5, 31 $r4 = LD_WU $r5, 31
... ...
--- ---
# CHECK-LABEL: test_ST_B: # CHECK-LABEL: test_ST_B:
# CHECK-ENC: 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: st.b a0, a1, 95 # CHECK-ASM: st.b $a0, $a1, 95
name: test_ST_B name: test_ST_B
body: | body: |
bb.0: bb.0:
ST_B $r4, $r5, 95 ST_B $r4, $r5, 95
... ...
--- ---
# CHECK-LABEL: test_ST_H: # CHECK-LABEL: test_ST_H:
# CHECK-ENC: 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: st.h a0, a1, 122 # CHECK-ASM: st.h $a0, $a1, 122
name: test_ST_H name: test_ST_H
body: | body: |
bb.0: bb.0:
ST_H $r4, $r5, 122 ST_H $r4, $r5, 122
... ...
--- ---
# CHECK-LABEL: test_ST_W: # CHECK-LABEL: test_ST_W:
# CHECK-ENC: 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: st.w a0, a1, 175 # CHECK-ASM: st.w $a0, $a1, 175
name: test_ST_W name: test_ST_W
body: | body: |
bb.0: bb.0:
ST_W $r4, $r5, 175 ST_W $r4, $r5, 175
... ...
--- ---
# CHECK-LABEL: test_ST_D: # CHECK-LABEL: test_ST_D:
# CHECK-ENC: 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: st.d a0, a1, 60 # CHECK-ASM: st.d $a0, $a1, 60
name: test_ST_D name: test_ST_D
body: | body: |
bb.0: bb.0:
ST_D $r4, $r5, 60 ST_D $r4, $r5, 60
... ...
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# Encoding format: 2RI14 # Encoding format: 2RI14
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# ------------------------+-----------------------------------------+--------------+--------------- # ------------------------+-----------------------------------------+--------------+---------------
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ------------------------+-----------------------------------------+--------------+--------------- # ------------------------+-----------------------------------------+--------------+---------------
# opcode | imm14 | rj | rd # opcode | imm14 | rj | rd
# ------------------------+-----------------------------------------+--------------+--------------- # ------------------------+-----------------------------------------+--------------+---------------
--- ---
# CHECK-LABEL: test_LDPTR_W: # CHECK-LABEL: test_LDPTR_W:
# CHECK-ENC: 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldptr.w a0, a1, 66 # CHECK-ASM: ldptr.w $a0, $a1, 66
name: test_LDPTR_W name: test_LDPTR_W
body: | body: |
bb.0: bb.0:
$r4 = LDPTR_W $r5, 66 $r4 = LDPTR_W $r5, 66
... ...
--- ---
# CHECK-LABEL: test_LDPTR_D: # CHECK-LABEL: test_LDPTR_D:
# CHECK-ENC: 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldptr.d a0, a1, 56 # CHECK-ASM: ldptr.d $a0, $a1, 56
name: test_LDPTR_D name: test_LDPTR_D
body: | body: |
bb.0: bb.0:
$r4 = LDPTR_D $r5, 56 $r4 = LDPTR_D $r5, 56
... ...
--- ---
# CHECK-LABEL: test_STPTR_W: # CHECK-LABEL: test_STPTR_W:
# CHECK-ENC: 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: stptr.w a0, a1, 87 # CHECK-ASM: stptr.w $a0, $a1, 87
name: test_STPTR_W name: test_STPTR_W
body: | body: |
bb.0: bb.0:
STPTR_W $r4, $r5, 87 STPTR_W $r4, $r5, 87
... ...
--- ---
# CHECK-LABEL: test_STPTR_D: # CHECK-LABEL: test_STPTR_D:
# CHECK-ENC: 0 0 1 0 0 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 0 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: stptr.d a0, a1, 145 # CHECK-ASM: stptr.d $a0, $a1, 145
name: test_STPTR_D name: test_STPTR_D
body: | body: |
bb.0: bb.0:
STPTR_D $r4, $r5, 145 STPTR_D $r4, $r5, 145
... ...
--- ---
# CHECK-LABEL: test_LL_W: # CHECK-LABEL: test_LL_W:
# CHECK-ENC: 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ll.w a0, a1, 243 # CHECK-ASM: ll.w $a0, $a1, 243
name: test_LL_W name: test_LL_W
body: | body: |
bb.0: bb.0:
$r4 = LL_W $r5, 243 $r4 = LL_W $r5, 243
... ...
--- ---
# CHECK-LABEL: test_LL_D: # CHECK-LABEL: test_LL_D:
# CHECK-ENC: 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ll.d a0, a1, 74 # CHECK-ASM: ll.d $a0, $a1, 74
name: test_LL_D name: test_LL_D
body: | body: |
bb.0: bb.0:
$r4 = LL_D $r5, 74 $r4 = LL_D $r5, 74
... ...
--- ---
# CHECK-LABEL: test_SC_W: # CHECK-LABEL: test_SC_W:
# CHECK-ENC: 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: sc.w a0, a1, 96 # CHECK-ASM: sc.w $a0, $a1, 96
name: test_SC_W name: test_SC_W
body: | body: |
bb.0: bb.0:
$r4 = SC_W $r4, $r5, 96 $r4 = SC_W $r4, $r5, 96
... ...
--- ---
# CHECK-LABEL: test_SC_D: # CHECK-LABEL: test_SC_D:
# CHECK-ENC: 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: sc.d a0, a1, 105 # CHECK-ASM: sc.d $a0, $a1, 105
name: test_SC_D name: test_SC_D
body: | body: |
bb.0: bb.0:
$r4 = SC_D $r4, $r5, 105 $r4 = SC_D $r4, $r5, 105
... ...
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# Encoding format: 2RI16 # Encoding format: 2RI16
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# ------------------+-----------------------------------------------+--------------+--------------- # ------------------+-----------------------------------------------+--------------+---------------
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ------------------+-----------------------------------------------+--------------+--------------- # ------------------+-----------------------------------------------+--------------+---------------
# opcode | imm16 | rj | rd # opcode | imm16 | rj | rd
# ------------------+-----------------------------------------------+--------------+--------------- # ------------------+-----------------------------------------------+--------------+---------------
--- ---
# CHECK-LABEL: test_ADDU16I_D: # CHECK-LABEL: test_ADDU16I_D:
# CHECK-ENC: 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: addu16i.d a0, a1, 23 # CHECK-ASM: addu16i.d $a0, $a1, 23
name: test_ADDU16I_D name: test_ADDU16I_D
body: | body: |
bb.0: bb.0:
$r4 = ADDU16I_D $r5, 23 $r4 = ADDU16I_D $r5, 23
... ...
--- ---
# CHECK-LABEL: test_JIRL: # CHECK-LABEL: test_JIRL:
# CHECK-ENC: 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: jirl a0, a1, 49 # CHECK-ASM: jirl $a0, $a1, 49
name: test_JIRL name: test_JIRL
body: | body: |
bb.0: bb.0:
$r4 = JIRL $r5, 49 $r4 = JIRL $r5, 49
... ...
--- ---
# CHECK-LABEL: test_BEQ: # CHECK-LABEL: test_BEQ:
# CHECK-ENC: 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 # CHECK-ENC: 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1
# CHECK-ASM: beq a0, a1, 196 # CHECK-ASM: beq $a0, $a1, 196
name: test_BEQ name: test_BEQ
body: | body: |
bb.0: bb.0:
BEQ $r4, $r5, 196 BEQ $r4, $r5, 196
... ...
--- ---
# CHECK-LABEL: test_BNE: # CHECK-LABEL: test_BNE:
# CHECK-ENC: 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 # CHECK-ENC: 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1
# CHECK-ASM: bne a0, a1, 19 # CHECK-ASM: bne $a0, $a1, 19
name: test_BNE name: test_BNE
body: | body: |
bb.0: bb.0:
BNE $r4, $r5, 19 BNE $r4, $r5, 19
... ...
--- ---
# CHECK-LABEL: test_BLT: # CHECK-LABEL: test_BLT:
# CHECK-ENC: 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 0 0 0 0 1 0 1 # CHECK-ENC: 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 0 0 0 0 1 0 1
# CHECK-ASM: blt a0, a1, 123 # CHECK-ASM: blt $a0, $a1, 123
name: test_BLT name: test_BLT
body: | body: |
bb.0: bb.0:
BLT $r4, $r5, 123 BLT $r4, $r5, 123
... ...
--- ---
# CHECK-LABEL: test_BGE: # CHECK-LABEL: test_BGE:
# CHECK-ENC: 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1 # CHECK-ENC: 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1
# CHECK-ASM: bge a0, a1, 12 # CHECK-ASM: bge $a0, $a1, 12
name: test_BGE name: test_BGE
body: | body: |
bb.0: bb.0:
BGE $r4, $r5, 12 BGE $r4, $r5, 12
... ...
--- ---
# CHECK-LABEL: test_BLTU: # CHECK-LABEL: test_BLTU:
# CHECK-ENC: 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 1 # CHECK-ENC: 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 1
# CHECK-ASM: bltu a0, a1, 17 # CHECK-ASM: bltu $a0, $a1, 17
name: test_BLTU name: test_BLTU
body: | body: |
bb.0: bb.0:
BLTU $r4, $r5, 17 BLTU $r4, $r5, 17
... ...
--- ---
# CHECK-LABEL: test_BGEU: # CHECK-LABEL: test_BGEU:
# CHECK-ENC: 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 # CHECK-ENC: 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1
# CHECK-ASM: bgeu a0, a1, 88 # CHECK-ASM: bgeu $a0, $a1, 88
name: test_BGEU name: test_BGEU
body: | body: |
bb.0: bb.0:
BGEU $r4, $r5, 88 BGEU $r4, $r5, 88

llvm/test/CodeGen/LoongArch/3r.mir

Show All 10 Lines
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ---------------------------------------------------+--------------+--------------+--------------- # ---------------------------------------------------+--------------+--------------+---------------
# opcode | rk | rj | rd # opcode | rk | rj | rd
# ---------------------------------------------------+--------------+--------------+--------------- # ---------------------------------------------------+--------------+--------------+---------------
--- ---
# CHECK-LABEL: test_ADD_W: # CHECK-LABEL: test_ADD_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: add.w a0, a1, a0 # CHECK-ASM: add.w $a0, $a1, $a0
name: test_ADD_W name: test_ADD_W
body: | body: |
bb.0: bb.0:
$r4 = ADD_W $r5, $r4 $r4 = ADD_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_ADD_D: # CHECK-LABEL: test_ADD_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: add.d a0, a1, a0 # CHECK-ASM: add.d $a0, $a1, $a0
name: test_ADD_D name: test_ADD_D
body: | body: |
bb.0: bb.0:
$r4 = ADD_D $r5, $r4 $r4 = ADD_D $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_SUB_W: # CHECK-LABEL: test_SUB_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: sub.w a0, a1, a0 # CHECK-ASM: sub.w $a0, $a1, $a0
name: test_SUB_W name: test_SUB_W
body: | body: |
bb.0: bb.0:
$r4 = SUB_W $r5, $r4 $r4 = SUB_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_SUB_D: # CHECK-LABEL: test_SUB_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: sub.d a0, a1, a0 # CHECK-ASM: sub.d $a0, $a1, $a0
name: test_SUB_D name: test_SUB_D
body: | body: |
bb.0: bb.0:
$r4 = SUB_D $r5, $r4 $r4 = SUB_D $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_SLT: # CHECK-LABEL: test_SLT:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: slt a0, a1, a0 # CHECK-ASM: slt $a0, $a1, $a0
name: test_SLT name: test_SLT
body: | body: |
bb.0: bb.0:
$r4 = SLT $r5, $r4 $r4 = SLT $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_SLTU: # CHECK-LABEL: test_SLTU:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: sltu a0, a1, a0 # CHECK-ASM: sltu $a0, $a1, $a0
name: test_SLTU name: test_SLTU
body: | body: |
bb.0: bb.0:
$r4 = SLTU $r5, $r4 $r4 = SLTU $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_MASKEQZ: # CHECK-LABEL: test_MASKEQZ:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: maskeqz a0, a1, a0 # CHECK-ASM: maskeqz $a0, $a1, $a0
name: test_MASKEQZ name: test_MASKEQZ
body: | body: |
bb.0: bb.0:
$r4 = MASKEQZ $r5, $r4 $r4 = MASKEQZ $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_MASKNEZ: # CHECK-LABEL: test_MASKNEZ:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: masknez a0, a1, a0 # CHECK-ASM: masknez $a0, $a1, $a0
name: test_MASKNEZ name: test_MASKNEZ
body: | body: |
bb.0: bb.0:
$r4 = MASKNEZ $r5, $r4 $r4 = MASKNEZ $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_NOR: # CHECK-LABEL: test_NOR:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: nor a0, a1, a0 # CHECK-ASM: nor $a0, $a1, $a0
name: test_NOR name: test_NOR
body: | body: |
bb.0: bb.0:
$r4 = NOR $r5, $r4 $r4 = NOR $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_AND: # CHECK-LABEL: test_AND:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: and a0, a1, a0 # CHECK-ASM: and $a0, $a1, $a0
name: test_AND name: test_AND
body: | body: |
bb.0: bb.0:
$r4 = AND $r5, $r4 $r4 = AND $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_OR: # CHECK-LABEL: test_OR:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: or a0, a1, a0 # CHECK-ASM: or $a0, $a1, $a0
name: test_OR name: test_OR
body: | body: |
bb.0: bb.0:
$r4 = OR $r5, $r4 $r4 = OR $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_XOR: # CHECK-LABEL: test_XOR:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: xor a0, a1, a0 # CHECK-ASM: xor $a0, $a1, $a0
name: test_XOR name: test_XOR
body: | body: |
bb.0: bb.0:
$r4 = XOR $r5, $r4 $r4 = XOR $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_ORN: # CHECK-LABEL: test_ORN:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: orn a0, a1, a0 # CHECK-ASM: orn $a0, $a1, $a0
name: test_ORN name: test_ORN
body: | body: |
bb.0: bb.0:
$r4 = ORN $r5, $r4 $r4 = ORN $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_ANDN: # CHECK-LABEL: test_ANDN:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: andn a0, a1, a0 # CHECK-ASM: andn $a0, $a1, $a0
name: test_ANDN name: test_ANDN
body: | body: |
bb.0: bb.0:
$r4 = ANDN $r5, $r4 $r4 = ANDN $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_SLL_W: # CHECK-LABEL: test_SLL_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: sll.w a0, a1, a0 # CHECK-ASM: sll.w $a0, $a1, $a0
name: test_SLL_W name: test_SLL_W
body: | body: |
bb.0: bb.0:
$r4 = SLL_W $r5, $r4 $r4 = SLL_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_SRL_W: # CHECK-LABEL: test_SRL_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: srl.w a0, a1, a0 # CHECK-ASM: srl.w $a0, $a1, $a0
name: test_SRL_W name: test_SRL_W
body: | body: |
bb.0: bb.0:
$r4 = SRL_W $r5, $r4 $r4 = SRL_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_SRA_W: # CHECK-LABEL: test_SRA_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: sra.w a0, a1, a0 # CHECK-ASM: sra.w $a0, $a1, $a0
name: test_SRA_W name: test_SRA_W
body: | body: |
bb.0: bb.0:
$r4 = SRA_W $r5, $r4 $r4 = SRA_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_SLL_D: # CHECK-LABEL: test_SLL_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: sll.d a0, a1, a0 # CHECK-ASM: sll.d $a0, $a1, $a0
name: test_SLL_D name: test_SLL_D
body: | body: |
bb.0: bb.0:
$r4 = SLL_D $r5, $r4 $r4 = SLL_D $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_SRL_D: # CHECK-LABEL: test_SRL_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: srl.d a0, a1, a0 # CHECK-ASM: srl.d $a0, $a1, $a0
name: test_SRL_D name: test_SRL_D
body: | body: |
bb.0: bb.0:
$r4 = SRL_D $r5, $r4 $r4 = SRL_D $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_SRA_D: # CHECK-LABEL: test_SRA_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: sra.d a0, a1, a0 # CHECK-ASM: sra.d $a0, $a1, $a0
name: test_SRA_D name: test_SRA_D
body: | body: |
bb.0: bb.0:
$r4 = SRA_D $r5, $r4 $r4 = SRA_D $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_ROTR_W: # CHECK-LABEL: test_ROTR_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: rotr.w a0, a1, a0 # CHECK-ASM: rotr.w $a0, $a1, $a0
name: test_ROTR_W name: test_ROTR_W
body: | body: |
bb.0: bb.0:
$r4 = ROTR_W $r5, $r4 $r4 = ROTR_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_ROTR_D: # CHECK-LABEL: test_ROTR_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: rotr.d a0, a1, a0 # CHECK-ASM: rotr.d $a0, $a1, $a0
name: test_ROTR_D name: test_ROTR_D
body: | body: |
bb.0: bb.0:
$r4 = ROTR_D $r5, $r4 $r4 = ROTR_D $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_MUL_W: # CHECK-LABEL: test_MUL_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: mul.w a0, a1, a0 # CHECK-ASM: mul.w $a0, $a1, $a0
name: test_MUL_W name: test_MUL_W
body: | body: |
bb.0: bb.0:
$r4 = MUL_W $r5, $r4 $r4 = MUL_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_MULH_W: # CHECK-LABEL: test_MULH_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: mulh.w a0, a1, a0 # CHECK-ASM: mulh.w $a0, $a1, $a0
name: test_MULH_W name: test_MULH_W
body: | body: |
bb.0: bb.0:
$r4 = MULH_W $r5, $r4 $r4 = MULH_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_MULH_WU: # CHECK-LABEL: test_MULH_WU:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: mulh.wu a0, a1, a0 # CHECK-ASM: mulh.wu $a0, $a1, $a0
name: test_MULH_WU name: test_MULH_WU
body: | body: |
bb.0: bb.0:
$r4 = MULH_WU $r5, $r4 $r4 = MULH_WU $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_MUL_D: # CHECK-LABEL: test_MUL_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: mul.d a0, a1, a0 # CHECK-ASM: mul.d $a0, $a1, $a0
name: test_MUL_D name: test_MUL_D
body: | body: |
bb.0: bb.0:
$r4 = MUL_D $r5, $r4 $r4 = MUL_D $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_MULH_D: # CHECK-LABEL: test_MULH_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: mulh.d a0, a1, a0 # CHECK-ASM: mulh.d $a0, $a1, $a0
name: test_MULH_D name: test_MULH_D
body: | body: |
bb.0: bb.0:
$r4 = MULH_D $r5, $r4 $r4 = MULH_D $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_MULH_DU: # CHECK-LABEL: test_MULH_DU:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: mulh.du a0, a1, a0 # CHECK-ASM: mulh.du $a0, $a1, $a0
name: test_MULH_DU name: test_MULH_DU
body: | body: |
bb.0: bb.0:
$r4 = MULH_DU $r5, $r4 $r4 = MULH_DU $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_MULW_D_W: # CHECK-LABEL: test_MULW_D_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: mulw.d.w a0, a1, a0 # CHECK-ASM: mulw.d.w $a0, $a1, $a0
name: test_MULW_D_W name: test_MULW_D_W
body: | body: |
bb.0: bb.0:
$r4 = MULW_D_W $r5, $r4 $r4 = MULW_D_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_MULW_D_WU: # CHECK-LABEL: test_MULW_D_WU:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: mulw.d.wu a0, a1, a0 # CHECK-ASM: mulw.d.wu $a0, $a1, $a0
name: test_MULW_D_WU name: test_MULW_D_WU
body: | body: |
bb.0: bb.0:
$r4 = MULW_D_WU $r5, $r4 $r4 = MULW_D_WU $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_DIV_W: # CHECK-LABEL: test_DIV_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: div.w a0, a1, a0 # CHECK-ASM: div.w $a0, $a1, $a0
name: test_DIV_W name: test_DIV_W
body: | body: |
bb.0: bb.0:
$r4 = DIV_W $r5, $r4 $r4 = DIV_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_MOD_W: # CHECK-LABEL: test_MOD_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: mod.w a0, a1, a0 # CHECK-ASM: mod.w $a0, $a1, $a0
name: test_MOD_W name: test_MOD_W
body: | body: |
bb.0: bb.0:
$r4 = MOD_W $r5, $r4 $r4 = MOD_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_DIV_WU: # CHECK-LABEL: test_DIV_WU:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: div.wu a0, a1, a0 # CHECK-ASM: div.wu $a0, $a1, $a0
name: test_DIV_WU name: test_DIV_WU
body: | body: |
bb.0: bb.0:
$r4 = DIV_WU $r5, $r4 $r4 = DIV_WU $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_MOD_WU: # CHECK-LABEL: test_MOD_WU:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: mod.wu a0, a1, a0 # CHECK-ASM: mod.wu $a0, $a1, $a0
name: test_MOD_WU name: test_MOD_WU
body: | body: |
bb.0: bb.0:
$r4 = MOD_WU $r5, $r4 $r4 = MOD_WU $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_DIV_D: # CHECK-LABEL: test_DIV_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: div.d a0, a1, a0 # CHECK-ASM: div.d $a0, $a1, $a0
name: test_DIV_D name: test_DIV_D
body: | body: |
bb.0: bb.0:
$r4 = DIV_D $r5, $r4 $r4 = DIV_D $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_MOD_D: # CHECK-LABEL: test_MOD_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: mod.d a0, a1, a0 # CHECK-ASM: mod.d $a0, $a1, $a0
name: test_MOD_D name: test_MOD_D
body: | body: |
bb.0: bb.0:
$r4 = MOD_D $r5, $r4 $r4 = MOD_D $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_DIV_DU: # CHECK-LABEL: test_DIV_DU:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: div.du a0, a1, a0 # CHECK-ASM: div.du $a0, $a1, $a0
name: test_DIV_DU name: test_DIV_DU
body: | body: |
bb.0: bb.0:
$r4 = DIV_DU $r5, $r4 $r4 = DIV_DU $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_MOD_DU: # CHECK-LABEL: test_MOD_DU:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: mod.du a0, a1, a0 # CHECK-ASM: mod.du $a0, $a1, $a0
name: test_MOD_DU name: test_MOD_DU
body: | body: |
bb.0: bb.0:
$r4 = MOD_DU $r5, $r4 $r4 = MOD_DU $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_CRC_W_B_W: # CHECK-LABEL: test_CRC_W_B_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: crc.w.b.w a0, a1, a0 # CHECK-ASM: crc.w.b.w $a0, $a1, $a0
name: test_CRC_W_B_W name: test_CRC_W_B_W
body: | body: |
bb.0: bb.0:
$r4 = CRC_W_B_W $r5, $r4 $r4 = CRC_W_B_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_CRC_W_H_W: # CHECK-LABEL: test_CRC_W_H_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: crc.w.h.w a0, a1, a0 # CHECK-ASM: crc.w.h.w $a0, $a1, $a0
name: test_CRC_W_H_W name: test_CRC_W_H_W
body: | body: |
bb.0: bb.0:
$r4 = CRC_W_H_W $r5, $r4 $r4 = CRC_W_H_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_CRC_W_W_W: # CHECK-LABEL: test_CRC_W_W_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: crc.w.w.w a0, a1, a0 # CHECK-ASM: crc.w.w.w $a0, $a1, $a0
name: test_CRC_W_W_W name: test_CRC_W_W_W
body: | body: |
bb.0: bb.0:
$r4 = CRC_W_W_W $r5, $r4 $r4 = CRC_W_W_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_CRC_W_D_W: # CHECK-LABEL: test_CRC_W_D_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: crc.w.d.w a0, a1, a0 # CHECK-ASM: crc.w.d.w $a0, $a1, $a0
name: test_CRC_W_D_W name: test_CRC_W_D_W
body: | body: |
bb.0: bb.0:
$r4 = CRC_W_D_W $r5, $r4 $r4 = CRC_W_D_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_CRCC_W_B_W: # CHECK-LABEL: test_CRCC_W_B_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: crcc.w.b.w a0, a1, a0 # CHECK-ASM: crcc.w.b.w $a0, $a1, $a0
name: test_CRCC_W_B_W name: test_CRCC_W_B_W
body: | body: |
bb.0: bb.0:
$r4 = CRCC_W_B_W $r5, $r4 $r4 = CRCC_W_B_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_CRCC_W_H_W: # CHECK-LABEL: test_CRCC_W_H_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: crcc.w.h.w a0, a1, a0 # CHECK-ASM: crcc.w.h.w $a0, $a1, $a0
name: test_CRCC_W_H_W name: test_CRCC_W_H_W
body: | body: |
bb.0: bb.0:
$r4 = CRCC_W_H_W $r5, $r4 $r4 = CRCC_W_H_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_CRCC_W_W_W: # CHECK-LABEL: test_CRCC_W_W_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: crcc.w.w.w a0, a1, a0 # CHECK-ASM: crcc.w.w.w $a0, $a1, $a0
name: test_CRCC_W_W_W name: test_CRCC_W_W_W
body: | body: |
bb.0: bb.0:
$r4 = CRCC_W_W_W $r5, $r4 $r4 = CRCC_W_W_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_CRCC_W_D_W: # CHECK-LABEL: test_CRCC_W_D_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: crcc.w.d.w a0, a1, a0 # CHECK-ASM: crcc.w.d.w $a0, $a1, $a0
name: test_CRCC_W_D_W name: test_CRCC_W_D_W
body: | body: |
bb.0: bb.0:
$r4 = CRCC_W_D_W $r5, $r4 $r4 = CRCC_W_D_W $r5, $r4
... ...
--- ---
# CHECK-LABEL: test_AMSWAP_DB_W: # CHECK-LABEL: test_AMSWAP_DB_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amswap_db.w a0, a1, a2 # CHECK-ASM: amswap_db.w $a0, $a1, $a2
name: test_AMSWAP_DB_W name: test_AMSWAP_DB_W
body: | body: |
bb.0: bb.0:
$r4 = AMSWAP_DB_W $r5, $r6 $r4 = AMSWAP_DB_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMSWAP_DB_D: # CHECK-LABEL: test_AMSWAP_DB_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amswap_db.d a0, a1, a2 # CHECK-ASM: amswap_db.d $a0, $a1, $a2
name: test_AMSWAP_DB_D name: test_AMSWAP_DB_D
body: | body: |
bb.0: bb.0:
$r4 = AMSWAP_DB_D $r5, $r6 $r4 = AMSWAP_DB_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMADD_DB_W: # CHECK-LABEL: test_AMADD_DB_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amadd_db.w a0, a1, a2 # CHECK-ASM: amadd_db.w $a0, $a1, $a2
name: test_AMADD_DB_W name: test_AMADD_DB_W
body: | body: |
bb.0: bb.0:
$r4 = AMADD_DB_W $r5, $r6 $r4 = AMADD_DB_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMADD_DB_D: # CHECK-LABEL: test_AMADD_DB_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amadd_db.d a0, a1, a2 # CHECK-ASM: amadd_db.d $a0, $a1, $a2
name: test_AMADD_DB_D name: test_AMADD_DB_D
body: | body: |
bb.0: bb.0:
$r4 = AMADD_DB_D $r5, $r6 $r4 = AMADD_DB_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMAND_DB_W: # CHECK-LABEL: test_AMAND_DB_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amand_db.w a0, a1, a2 # CHECK-ASM: amand_db.w $a0, $a1, $a2
name: test_AMAND_DB_W name: test_AMAND_DB_W
body: | body: |
bb.0: bb.0:
$r4 = AMAND_DB_W $r5, $r6 $r4 = AMAND_DB_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMAND_DB_D: # CHECK-LABEL: test_AMAND_DB_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amand_db.d a0, a1, a2 # CHECK-ASM: amand_db.d $a0, $a1, $a2
name: test_AMAND_DB_D name: test_AMAND_DB_D
body: | body: |
bb.0: bb.0:
$r4 = AMAND_DB_D $r5, $r6 $r4 = AMAND_DB_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMOR_DB_W: # CHECK-LABEL: test_AMOR_DB_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amor_db.w a0, a1, a2 # CHECK-ASM: amor_db.w $a0, $a1, $a2
name: test_AMOR_DB_W name: test_AMOR_DB_W
body: | body: |
bb.0: bb.0:
$r4 = AMOR_DB_W $r5, $r6 $r4 = AMOR_DB_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMOR_DB_D: # CHECK-LABEL: test_AMOR_DB_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amor_db.d a0, a1, a2 # CHECK-ASM: amor_db.d $a0, $a1, $a2
name: test_AMOR_DB_D name: test_AMOR_DB_D
body: | body: |
bb.0: bb.0:
$r4 = AMOR_DB_D $r5, $r6 $r4 = AMOR_DB_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMXOR_DB_W: # CHECK-LABEL: test_AMXOR_DB_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amxor_db.w a0, a1, a2 # CHECK-ASM: amxor_db.w $a0, $a1, $a2
name: test_AMXOR_DB_W name: test_AMXOR_DB_W
body: | body: |
bb.0: bb.0:
$r4 = AMXOR_DB_W $r5, $r6 $r4 = AMXOR_DB_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMXOR_DB_D: # CHECK-LABEL: test_AMXOR_DB_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amxor_db.d a0, a1, a2 # CHECK-ASM: amxor_db.d $a0, $a1, $a2
name: test_AMXOR_DB_D name: test_AMXOR_DB_D
body: | body: |
bb.0: bb.0:
$r4 = AMXOR_DB_D $r5, $r6 $r4 = AMXOR_DB_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMAX_DB_W: # CHECK-LABEL: test_AMMAX_DB_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammax_db.w a0, a1, a2 # CHECK-ASM: ammax_db.w $a0, $a1, $a2
name: test_AMMAX_DB_W name: test_AMMAX_DB_W
body: | body: |
bb.0: bb.0:
$r4 = AMMAX_DB_W $r5, $r6 $r4 = AMMAX_DB_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMAX_DB_D: # CHECK-LABEL: test_AMMAX_DB_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammax_db.d a0, a1, a2 # CHECK-ASM: ammax_db.d $a0, $a1, $a2
name: test_AMMAX_DB_D name: test_AMMAX_DB_D
body: | body: |
bb.0: bb.0:
$r4 = AMMAX_DB_D $r5, $r6 $r4 = AMMAX_DB_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMIN_DB_W: # CHECK-LABEL: test_AMMIN_DB_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammin_db.w a0, a1, a2 # CHECK-ASM: ammin_db.w $a0, $a1, $a2
name: test_AMMIN_DB_W name: test_AMMIN_DB_W
body: | body: |
bb.0: bb.0:
$r4 = AMMIN_DB_W $r5, $r6 $r4 = AMMIN_DB_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMIN_DB_D: # CHECK-LABEL: test_AMMIN_DB_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammin_db.d a0, a1, a2 # CHECK-ASM: ammin_db.d $a0, $a1, $a2
name: test_AMMIN_DB_D name: test_AMMIN_DB_D
body: | body: |
bb.0: bb.0:
$r4 = AMMIN_DB_D $r5, $r6 $r4 = AMMIN_DB_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMAX_DB_WU: # CHECK-LABEL: test_AMMAX_DB_WU:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammax_db.wu a0, a1, a2 # CHECK-ASM: ammax_db.wu $a0, $a1, $a2
name: test_AMMAX_DB_WU name: test_AMMAX_DB_WU
body: | body: |
bb.0: bb.0:
$r4 = AMMAX_DB_WU $r5, $r6 $r4 = AMMAX_DB_WU $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMAX_DB_DU: # CHECK-LABEL: test_AMMAX_DB_DU:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammax_db.du a0, a1, a2 # CHECK-ASM: ammax_db.du $a0, $a1, $a2
name: test_AMMAX_DB_DU name: test_AMMAX_DB_DU
body: | body: |
bb.0: bb.0:
$r4 = AMMAX_DB_DU $r5, $r6 $r4 = AMMAX_DB_DU $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMIN_DB_WU: # CHECK-LABEL: test_AMMIN_DB_WU:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammin_db.wu a0, a1, a2 # CHECK-ASM: ammin_db.wu $a0, $a1, $a2
name: test_AMMIN_DB_WU name: test_AMMIN_DB_WU
body: | body: |
bb.0: bb.0:
$r4 = AMMIN_DB_WU $r5, $r6 $r4 = AMMIN_DB_WU $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMIN_DB_DU: # CHECK-LABEL: test_AMMIN_DB_DU:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammin_db.du a0, a1, a2 # CHECK-ASM: ammin_db.du $a0, $a1, $a2
name: test_AMMIN_DB_DU name: test_AMMIN_DB_DU
body: | body: |
bb.0: bb.0:
$r4 = AMMIN_DB_DU $r5, $r6 $r4 = AMMIN_DB_DU $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMSWAP_W: # CHECK-LABEL: test_AMSWAP_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amswap.w a0, a1, a2 # CHECK-ASM: amswap.w $a0, $a1, $a2
name: test_AMSWAP_W name: test_AMSWAP_W
body: | body: |
bb.0: bb.0:
$r4 = AMSWAP_W $r5, $r6 $r4 = AMSWAP_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMSWAP_D: # CHECK-LABEL: test_AMSWAP_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amswap.d a0, a1, a2 # CHECK-ASM: amswap.d $a0, $a1, $a2
name: test_AMSWAP_D name: test_AMSWAP_D
body: | body: |
bb.0: bb.0:
$r4 = AMSWAP_D $r5, $r6 $r4 = AMSWAP_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMADD_W: # CHECK-LABEL: test_AMADD_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amadd.w a0, a1, a2 # CHECK-ASM: amadd.w $a0, $a1, $a2
name: test_AMADD_W name: test_AMADD_W
body: | body: |
bb.0: bb.0:
$r4 = AMADD_W $r5, $r6 $r4 = AMADD_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMADD_D: # CHECK-LABEL: test_AMADD_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amadd.d a0, a1, a2 # CHECK-ASM: amadd.d $a0, $a1, $a2
name: test_AMADD_D name: test_AMADD_D
body: | body: |
bb.0: bb.0:
$r4 = AMADD_D $r5, $r6 $r4 = AMADD_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMAND_W: # CHECK-LABEL: test_AMAND_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amand.w a0, a1, a2 # CHECK-ASM: amand.w $a0, $a1, $a2
name: test_AMAND_W name: test_AMAND_W
body: | body: |
bb.0: bb.0:
$r4 = AMAND_W $r5, $r6 $r4 = AMAND_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMAND_D: # CHECK-LABEL: test_AMAND_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amand.d a0, a1, a2 # CHECK-ASM: amand.d $a0, $a1, $a2
name: test_AMAND_D name: test_AMAND_D
body: | body: |
bb.0: bb.0:
$r4 = AMAND_D $r5, $r6 $r4 = AMAND_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMOR_W: # CHECK-LABEL: test_AMOR_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amor.w a0, a1, a2 # CHECK-ASM: amor.w $a0, $a1, $a2
name: test_AMOR_W name: test_AMOR_W
body: | body: |
bb.0: bb.0:
$r4 = AMOR_W $r5, $r6 $r4 = AMOR_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMOR_D: # CHECK-LABEL: test_AMOR_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amor.d a0, a1, a2 # CHECK-ASM: amor.d $a0, $a1, $a2
name: test_AMOR_D name: test_AMOR_D
body: | body: |
bb.0: bb.0:
$r4 = AMOR_D $r5, $r6 $r4 = AMOR_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMXOR_W: # CHECK-LABEL: test_AMXOR_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amxor.w a0, a1, a2 # CHECK-ASM: amxor.w $a0, $a1, $a2
name: test_AMXOR_W name: test_AMXOR_W
body: | body: |
bb.0: bb.0:
$r4 = AMXOR_W $r5, $r6 $r4 = AMXOR_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMXOR_D: # CHECK-LABEL: test_AMXOR_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: amxor.d a0, a1, a2 # CHECK-ASM: amxor.d $a0, $a1, $a2
name: test_AMXOR_D name: test_AMXOR_D
body: | body: |
bb.0: bb.0:
$r4 = AMXOR_D $r5, $r6 $r4 = AMXOR_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMAX_W: # CHECK-LABEL: test_AMMAX_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammax.w a0, a1, a2 # CHECK-ASM: ammax.w $a0, $a1, $a2
name: test_AMMAX_W name: test_AMMAX_W
body: | body: |
bb.0: bb.0:
$r4 = AMMAX_W $r5, $r6 $r4 = AMMAX_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMAX_D: # CHECK-LABEL: test_AMMAX_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammax.d a0, a1, a2 # CHECK-ASM: ammax.d $a0, $a1, $a2
name: test_AMMAX_D name: test_AMMAX_D
body: | body: |
bb.0: bb.0:
$r4 = AMMAX_D $r5, $r6 $r4 = AMMAX_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMIN_W: # CHECK-LABEL: test_AMMIN_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammin.w a0, a1, a2 # CHECK-ASM: ammin.w $a0, $a1, $a2
name: test_AMMIN_W name: test_AMMIN_W
body: | body: |
bb.0: bb.0:
$r4 = AMMIN_W $r5, $r6 $r4 = AMMIN_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMIN_D: # CHECK-LABEL: test_AMMIN_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammin.d a0, a1, a2 # CHECK-ASM: ammin.d $a0, $a1, $a2
name: test_AMMIN_D name: test_AMMIN_D
body: | body: |
bb.0: bb.0:
$r4 = AMMIN_D $r5, $r6 $r4 = AMMIN_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMAX_WU: # CHECK-LABEL: test_AMMAX_WU:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammax.wu a0, a1, a2 # CHECK-ASM: ammax.wu $a0, $a1, $a2
name: test_AMMAX_WU name: test_AMMAX_WU
body: | body: |
bb.0: bb.0:
$r4 = AMMAX_WU $r5, $r6 $r4 = AMMAX_WU $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMAX_DU: # CHECK-LABEL: test_AMMAX_DU:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammax.du a0, a1, a2 # CHECK-ASM: ammax.du $a0, $a1, $a2
name: test_AMMAX_DU name: test_AMMAX_DU
body: | body: |
bb.0: bb.0:
$r4 = AMMAX_DU $r5, $r6 $r4 = AMMAX_DU $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMIN_WU: # CHECK-LABEL: test_AMMIN_WU:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammin.wu a0, a1, a2 # CHECK-ASM: ammin.wu $a0, $a1, $a2
name: test_AMMIN_WU name: test_AMMIN_WU
body: | body: |
bb.0: bb.0:
$r4 = AMMIN_WU $r5, $r6 $r4 = AMMIN_WU $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_AMMIN_DU: # CHECK-LABEL: test_AMMIN_DU:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ammin.du a0, a1, a2 # CHECK-ASM: ammin.du $a0, $a1, $a2
name: test_AMMIN_DU name: test_AMMIN_DU
body: | body: |
bb.0: bb.0:
$r4 = AMMIN_DU $r5, $r6 $r4 = AMMIN_DU $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDX_B: # CHECK-LABEL: test_LDX_B:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldx.b a0, a1, a2 # CHECK-ASM: ldx.b $a0, $a1, $a2
name: test_LDX_B name: test_LDX_B
body: | body: |
bb.0: bb.0:
$r4 = LDX_B $r5, $r6 $r4 = LDX_B $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDX_H: # CHECK-LABEL: test_LDX_H:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldx.h a0, a1, a2 # CHECK-ASM: ldx.h $a0, $a1, $a2
name: test_LDX_H name: test_LDX_H
body: | body: |
bb.0: bb.0:
$r4 = LDX_H $r5, $r6 $r4 = LDX_H $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDX_W: # CHECK-LABEL: test_LDX_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldx.w a0, a1, a2 # CHECK-ASM: ldx.w $a0, $a1, $a2
name: test_LDX_W name: test_LDX_W
body: | body: |
bb.0: bb.0:
$r4 = LDX_W $r5, $r6 $r4 = LDX_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDX_D: # CHECK-LABEL: test_LDX_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldx.d a0, a1, a2 # CHECK-ASM: ldx.d $a0, $a1, $a2
name: test_LDX_D name: test_LDX_D
body: | body: |
bb.0: bb.0:
$r4 = LDX_D $r5, $r6 $r4 = LDX_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDX_BU: # CHECK-LABEL: test_LDX_BU:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldx.bu a0, a1, a2 # CHECK-ASM: ldx.bu $a0, $a1, $a2
name: test_LDX_BU name: test_LDX_BU
body: | body: |
bb.0: bb.0:
$r4 = LDX_BU $r5, $r6 $r4 = LDX_BU $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDX_HU: # CHECK-LABEL: test_LDX_HU:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldx.hu a0, a1, a2 # CHECK-ASM: ldx.hu $a0, $a1, $a2
name: test_LDX_HU name: test_LDX_HU
body: | body: |
bb.0: bb.0:
$r4 = LDX_HU $r5, $r6 $r4 = LDX_HU $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDX_WU: # CHECK-LABEL: test_LDX_WU:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldx.wu a0, a1, a2 # CHECK-ASM: ldx.wu $a0, $a1, $a2
name: test_LDX_WU name: test_LDX_WU
body: | body: |
bb.0: bb.0:
$r4 = LDX_WU $r5, $r6 $r4 = LDX_WU $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDGT_B: # CHECK-LABEL: test_LDGT_B:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldgt.b a0, a1, a2 # CHECK-ASM: ldgt.b $a0, $a1, $a2
name: test_LDGT_B name: test_LDGT_B
body: | body: |
bb.0: bb.0:
$r4 = LDGT_B $r5, $r6 $r4 = LDGT_B $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDGT_H: # CHECK-LABEL: test_LDGT_H:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldgt.h a0, a1, a2 # CHECK-ASM: ldgt.h $a0, $a1, $a2
name: test_LDGT_H name: test_LDGT_H
body: | body: |
bb.0: bb.0:
$r4 = LDGT_H $r5, $r6 $r4 = LDGT_H $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDGT_W: # CHECK-LABEL: test_LDGT_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldgt.w a0, a1, a2 # CHECK-ASM: ldgt.w $a0, $a1, $a2
name: test_LDGT_W name: test_LDGT_W
body: | body: |
bb.0: bb.0:
$r4 = LDGT_W $r5, $r6 $r4 = LDGT_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDGT_D: # CHECK-LABEL: test_LDGT_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldgt.d a0, a1, a2 # CHECK-ASM: ldgt.d $a0, $a1, $a2
name: test_LDGT_D name: test_LDGT_D
body: | body: |
bb.0: bb.0:
$r4 = LDGT_D $r5, $r6 $r4 = LDGT_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDLE_B: # CHECK-LABEL: test_LDLE_B:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldle.b a0, a1, a2 # CHECK-ASM: ldle.b $a0, $a1, $a2
name: test_LDLE_B name: test_LDLE_B
body: | body: |
bb.0: bb.0:
$r4 = LDLE_B $r5, $r6 $r4 = LDLE_B $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDLE_H: # CHECK-LABEL: test_LDLE_H:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldle.h a0, a1, a2 # CHECK-ASM: ldle.h $a0, $a1, $a2
name: test_LDLE_H name: test_LDLE_H
body: | body: |
bb.0: bb.0:
$r4 = LDLE_H $r5, $r6 $r4 = LDLE_H $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDLE_W: # CHECK-LABEL: test_LDLE_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldle.w a0, a1, a2 # CHECK-ASM: ldle.w $a0, $a1, $a2
name: test_LDLE_W name: test_LDLE_W
body: | body: |
bb.0: bb.0:
$r4 = LDLE_W $r5, $r6 $r4 = LDLE_W $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_LDLE_D: # CHECK-LABEL: test_LDLE_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: ldle.d a0, a1, a2 # CHECK-ASM: ldle.d $a0, $a1, $a2
name: test_LDLE_D name: test_LDLE_D
body: | body: |
bb.0: bb.0:
$r4 = LDLE_D $r5, $r6 $r4 = LDLE_D $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_STX_B: # CHECK-LABEL: test_STX_B:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: stx.b a0, a1, a2 # CHECK-ASM: stx.b $a0, $a1, $a2
name: test_STX_B name: test_STX_B
body: | body: |
bb.0: bb.0:
STX_B $r4, $r5, $r6 STX_B $r4, $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_STX_H: # CHECK-LABEL: test_STX_H:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: stx.h a0, a1, a2 # CHECK-ASM: stx.h $a0, $a1, $a2
name: test_STX_H name: test_STX_H
body: | body: |
bb.0: bb.0:
STX_H $r4, $r5, $r6 STX_H $r4, $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_STX_W: # CHECK-LABEL: test_STX_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: stx.w a0, a1, a2 # CHECK-ASM: stx.w $a0, $a1, $a2
name: test_STX_W name: test_STX_W
body: | body: |
bb.0: bb.0:
STX_W $r4, $r5, $r6 STX_W $r4, $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_STX_D: # CHECK-LABEL: test_STX_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: stx.d a0, a1, a2 # CHECK-ASM: stx.d $a0, $a1, $a2
name: test_STX_D name: test_STX_D
body: | body: |
bb.0: bb.0:
STX_D $r4, $r5, $r6 STX_D $r4, $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_STGT_B: # CHECK-LABEL: test_STGT_B:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: stgt.b a0, a1, a2 # CHECK-ASM: stgt.b $a0, $a1, $a2
name: test_STGT_B name: test_STGT_B
body: | body: |
bb.0: bb.0:
STGT_B $r4, $r5, $r6 STGT_B $r4, $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_STGT_H: # CHECK-LABEL: test_STGT_H:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: stgt.h a0, a1, a2 # CHECK-ASM: stgt.h $a0, $a1, $a2
name: test_STGT_H name: test_STGT_H
body: | body: |
bb.0: bb.0:
STGT_H $r4, $r5, $r6 STGT_H $r4, $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_STGT_W: # CHECK-LABEL: test_STGT_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: stgt.w a0, a1, a2 # CHECK-ASM: stgt.w $a0, $a1, $a2
name: test_STGT_W name: test_STGT_W
body: | body: |
bb.0: bb.0:
STGT_W $r4, $r5, $r6 STGT_W $r4, $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_STGT_D: # CHECK-LABEL: test_STGT_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: stgt.d a0, a1, a2 # CHECK-ASM: stgt.d $a0, $a1, $a2
name: test_STGT_D name: test_STGT_D
body: | body: |
bb.0: bb.0:
STGT_D $r4, $r5, $r6 STGT_D $r4, $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_STLE_B: # CHECK-LABEL: test_STLE_B:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: stle.b a0, a1, a2 # CHECK-ASM: stle.b $a0, $a1, $a2
name: test_STLE_B name: test_STLE_B
body: | body: |
bb.0: bb.0:
STLE_B $r4, $r5, $r6 STLE_B $r4, $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_STLE_H: # CHECK-LABEL: test_STLE_H:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: stle.h a0, a1, a2 # CHECK-ASM: stle.h $a0, $a1, $a2
name: test_STLE_H name: test_STLE_H
body: | body: |
bb.0: bb.0:
STLE_H $r4, $r5, $r6 STLE_H $r4, $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_STLE_W: # CHECK-LABEL: test_STLE_W:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: stle.w a0, a1, a2 # CHECK-ASM: stle.w $a0, $a1, $a2
name: test_STLE_W name: test_STLE_W
body: | body: |
bb.0: bb.0:
STLE_W $r4, $r5, $r6 STLE_W $r4, $r5, $r6
... ...
--- ---
# CHECK-LABEL: test_STLE_D: # CHECK-LABEL: test_STLE_D:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: stle.d a0, a1, a2 # CHECK-ASM: stle.d $a0, $a1, $a2
name: test_STLE_D name: test_STLE_D
body: | body: |
bb.0: bb.0:
STLE_D $r4, $r5, $r6 STLE_D $r4, $r5, $r6

llvm/test/CodeGen/LoongArch/3ri.mir

Show All 10 Lines
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ---------------------------------------------+-----+--------------+--------------+--------------- # ---------------------------------------------+-----+--------------+--------------+---------------
# opcode |imm2 | rk | rj | rd # opcode |imm2 | rk | rj | rd
# ---------------------------------------------+-----+--------------+--------------+--------------- # ---------------------------------------------+-----+--------------+--------------+---------------
--- ---
# CHECK-LABEL: test_ALSL_W: # CHECK-LABEL: test_ALSL_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: alsl.w a0, a1, a2, 3 # CHECK-ASM: alsl.w $a0, $a1, $a2, 3
name: test_ALSL_W name: test_ALSL_W
body: | body: |
bb.0: bb.0:
$r4 = ALSL_W $r5, $r6, 3 $r4 = ALSL_W $r5, $r6, 3
... ...
--- ---
# CHECK-LABEL: test_ALSL_WU: # CHECK-LABEL: test_ALSL_WU:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: alsl.wu a0, a1, a2, 1 # CHECK-ASM: alsl.wu $a0, $a1, $a2, 1
name: test_ALSL_WU name: test_ALSL_WU
body: | body: |
bb.0: bb.0:
$r4 = ALSL_WU $r5, $r6, 1 $r4 = ALSL_WU $r5, $r6, 1
... ...
--- ---
# CHECK-LABEL: test_ALSL_D: # CHECK-LABEL: test_ALSL_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: alsl.d a0, a1, a2, 3 # CHECK-ASM: alsl.d $a0, $a1, $a2, 3
name: test_ALSL_D name: test_ALSL_D
body: | body: |
bb.0: bb.0:
$r4 = ALSL_D $r5, $r6, 3 $r4 = ALSL_D $r5, $r6, 3
... ...
--- ---
# CHECK-LABEL: test_BYTEPICK_W: # CHECK-LABEL: test_BYTEPICK_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: bytepick.w a0, a1, a2, 0 # CHECK-ASM: bytepick.w $a0, $a1, $a2, 0
name: test_BYTEPICK_W name: test_BYTEPICK_W
body: | body: |
bb.0: bb.0:
$r4 = BYTEPICK_W $r5, $r6, 0 $r4 = BYTEPICK_W $r5, $r6, 0
... ...
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# Encoding format: 3RI3 # Encoding format: 3RI3
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# ------------------------------------------+--------+--------------+--------------+--------------- # ------------------------------------------+--------+--------------+--------------+---------------
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ------------------------------------------+--------+--------------+--------------+--------------- # ------------------------------------------+--------+--------------+--------------+---------------
# opcode | imm3 | rk | rj | rd # opcode | imm3 | rk | rj | rd
# ------------------------------------------+--------+--------------+--------------+--------------- # ------------------------------------------+--------+--------------+--------------+---------------
--- ---
# CHECK-LABEL: test_BYTEPICK_D: # CHECK-LABEL: test_BYTEPICK_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: bytepick.d a0, a1, a2, 4 # CHECK-ASM: bytepick.d $a0, $a1, $a2, 4
name: test_BYTEPICK_D name: test_BYTEPICK_D
body: | body: |
bb.0: bb.0:
$r4 = BYTEPICK_D $r5, $r6, 4 $r4 = BYTEPICK_D $r5, $r6, 4

llvm/test/CodeGen/LoongArch/misc.mir

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ---------------------------------+--------------+---------+--------------+--------------+--------------- # ---------------------------------+--------------+---------+--------------+--------------+---------------
# opcode{11-1} | msb |opcode{0}| lsb | rj | rd # opcode{11-1} | msb |opcode{0}| lsb | rj | rd
# ---------------------------------+--------------+---------+--------------+--------------+--------------- # ---------------------------------+--------------+---------+--------------+--------------+---------------
--- ---
# CHECK-LABEL: test_BSTRINS_W: # CHECK-LABEL: test_BSTRINS_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: bstrins.w a0, a1, 7, 2 # CHECK-ASM: bstrins.w $a0, $a1, 7, 2
name: test_BSTRINS_W name: test_BSTRINS_W
body: | body: |
bb.0: bb.0:
$r4 = BSTRINS_W $r5, 7, 2 $r4 = BSTRINS_W $r5, 7, 2
... ...
--- ---
# CHECK-LABEL: test_BSTRPICK_W: # CHECK-LABEL: test_BSTRPICK_W:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: bstrpick.w a0, a1, 10, 4 # CHECK-ASM: bstrpick.w $a0, $a1, 10, 4
name: test_BSTRPICK_W name: test_BSTRPICK_W
body: | body: |
bb.0: bb.0:
$r4 = BSTRPICK_W $r5, 10, 4 $r4 = BSTRPICK_W $r5, 10, 4
... ...
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# Encoding format: BSTR_D # Encoding format: BSTR_D
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# ------------------------------+-----------------+-----------------+--------------+--------------- # ------------------------------+-----------------+-----------------+--------------+---------------
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ------------------------------+-----------------+-----------------+--------------+--------------- # ------------------------------+-----------------+-----------------+--------------+---------------
# opcode | msb | lsb | rj | rd # opcode | msb | lsb | rj | rd
# ------------------------------+-----------------+-----------------+--------------+--------------- # ------------------------------+-----------------+-----------------+--------------+---------------
--- ---
# CHECK-LABEL: test_BSTRINS_D: # CHECK-LABEL: test_BSTRINS_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: bstrins.d a0, a1, 7, 2 # CHECK-ASM: bstrins.d $a0, $a1, 7, 2
name: test_BSTRINS_D name: test_BSTRINS_D
body: | body: |
bb.0: bb.0:
$r4 = BSTRINS_D $r5, 7, 2 $r4 = BSTRINS_D $r5, 7, 2
... ...
--- ---
# CHECK-LABEL: test_BSTRPICK_D: # CHECK-LABEL: test_BSTRPICK_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0
# CHECK-ASM: bstrpick.d a0, a1, 39, 22 # CHECK-ASM: bstrpick.d $a0, $a1, 39, 22
name: test_BSTRPICK_D name: test_BSTRPICK_D
body: | body: |
bb.0: bb.0:
$r4 = BSTRPICK_D $r5, 39, 22 $r4 = BSTRPICK_D $r5, 39, 22
... ...
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# Encoding format: ASRT # Encoding format: ASRT
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# ---------------------------------------------------+--------------+--------------+--------------- # ---------------------------------------------------+--------------+--------------+---------------
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ---------------------------------------------------+--------------+--------------+--------------- # ---------------------------------------------------+--------------+--------------+---------------
# opcode | rk | rj | 0x0 # opcode | rk | rj | 0x0
# ---------------------------------------------------+--------------+--------------+--------------- # ---------------------------------------------------+--------------+--------------+---------------
--- ---
# CHECK-LABEL: test_ASRTLE_D: # CHECK-LABEL: test_ASRTLE_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0
# CHECK-ASM: asrtle.d a0, a1 # CHECK-ASM: asrtle.d $a0, $a1
name: test_ASRTLE_D name: test_ASRTLE_D
body: | body: |
bb.0: bb.0:
ASRTLE_D $r4, $r5 ASRTLE_D $r4, $r5
... ...
--- ---
# CHECK-LABEL: test_ASRTGT_D: # CHECK-LABEL: test_ASRTGT_D:
# CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0
# CHECK-ASM: asrtgt.d a0, a1 # CHECK-ASM: asrtgt.d $a0, $a1
name: test_ASRTGT_D name: test_ASRTGT_D
body: | body: |
bb.0: bb.0:
ASRTGT_D $r4, $r5 ASRTGT_D $r4, $r5
... ...
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# Encoding format: PRELD # Encoding format: PRELD
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# ------------------------------+-----------------------------------+--------------+--------------- # ------------------------------+-----------------------------------+--------------+---------------
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ------------------------------+-----------------------------------+--------------+--------------- # ------------------------------+-----------------------------------+--------------+---------------
# opcode | imm12 | rj | imm5 # opcode | imm12 | rj | imm5
# ------------------------------+-----------------------------------+--------------+--------------- # ------------------------------+-----------------------------------+--------------+---------------
--- ---
# CHECK-LABEL: test_PRELD: # CHECK-LABEL: test_PRELD:
# CHECK-ENC: 0 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 1 1 1 1 # CHECK-ENC: 0 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 1 1 1 1
# CHECK-ASM: preld 15, a0, 21 # CHECK-ASM: preld 15, $a0, 21
name: test_PRELD name: test_PRELD
body: | body: |
bb.0: bb.0:
PRELD 15, $r4, 21 PRELD 15, $r4, 21
... ...
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# Encoding format: PRELDX # Encoding format: PRELDX
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# ---------------------------------------------------+--------------+--------------+--------------- # ---------------------------------------------------+--------------+--------------+---------------
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
# ---------------------------------------------------+--------------+--------------+--------------- # ---------------------------------------------------+--------------+--------------+---------------
# opcode | rk | rj | imm5 # opcode | rk | rj | imm5
# ---------------------------------------------------+--------------+--------------+--------------- # ---------------------------------------------------+--------------+--------------+---------------
--- ---
# CHECK-LABEL: test_PRELDX: # CHECK-LABEL: test_PRELDX:
# CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 # CHECK-ENC: 0 0 1 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1
# CHECK-ASM: preldx 11, a0, a1 # CHECK-ASM: preldx 11, $a0, $a1
name: test_PRELDX name: test_PRELDX
body: | body: |
bb.0: bb.0:
PRELDX 11, $r4, $r5 PRELDX 11, $r4, $r5