[ARM] Patterns for vector conversion between half and float

[ostannard]

Summary

These patterns were omitted because clang only allows converting between these types using intrinsics, but other front-ends or optimisation passes may want to use them.

[srhines]

Thanks for getting this fixed quickly!

[SjoerdMeijer]

llvm/test/CodeGen/ARM/fp16-vector-cvt.ll

13

These scalar variants are not related to the added vector patterns, and also seem to be tested in existing tests (which is what I was hoping). Do we need this? I only quickly grep'ed for this variant, not the other scalar variants below, but same question for those.

[dmgreen]

The change here LGTM too. Remember to upload with context :)

llvm/test/CodeGen/ARM/fp16-vector-cvt.ll

5

I think you can remove this, and the "hidden"s below too.

llvm/lib/Target/ARM/ARMInstrNEON.td

def  VCVTf2h  : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
                         IIC_VUNAQ, "vcvt", "f16.f32",
                         v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
                 Requires<[HasNEON, HasFP16]>;
 def  VCVTh2f  : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
                         IIC_VUNAQ, "vcvt", "f32.f16",
                         v4f32, v4i16, int_arm_neon_vcvthf2fp>,
                 Requires<[HasNEON, HasFP16]>;
 
+def : Pat<(v4f16 (fpround (v4f32 QPR:$src))), (VCVTf2h QPR:$src)>;
+def : Pat<(v4f32 (fpextend (v4f16 DPR:$src))), (VCVTh2f DPR:$src)>;
+
 // Vector Reverse.
 
 //   VREV64   : Vector Reverse elements within 64-bit doublewords
 
 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
   : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
         (ins DPR:$Vm), IIC_VMOVD,
         OpcodeStr, Dt, "$Vd, $Vm", "",

llvm/test/CodeGen/ARM/fp16-vector-cvt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple armv8a-none-none-eabihf -mattr=fullfp16 < %s | FileCheck %s
+
+define <4 x half> @fptrunc_vector_f32_f16(<4 x float> %a) {
+; CHECK-LABEL: fptrunc_vector_f32_f16:
+; CHECK:       @ %bb.0: @ %bb
+; CHECK-NEXT:    vcvt.f16.f32 d0, q0
+; CHECK-NEXT:    bx lr
+bb:
+  %z = fptrunc <4 x float> %a to <4 x half>
+  ret <4 x half> %z
+}
+
+define <4 x half> @fptrunc_vector_f64_f16(<4 x double> %a) {
+; CHECK-LABEL: fptrunc_vector_f64_f16:
+; CHECK:       @ %bb.0: @ %bb
+; CHECK-NEXT:    vcvtb.f16.f64 s0, d0
+; CHECK-NEXT:    vcvtb.f16.f64 s8, d1
+; CHECK-NEXT:    vmov r1, s0
+; CHECK-NEXT:    vcvtb.f16.f64 s2, d2
+; CHECK-NEXT:    vmov r0, s8
+; CHECK-NEXT:    vmov.16 d0[0], r1
+; CHECK-NEXT:    vmov.16 d0[1], r0
+; CHECK-NEXT:    vmov r0, s2
+; CHECK-NEXT:    vcvtb.f16.f64 s2, d3
+; CHECK-NEXT:    vmov.16 d0[2], r0
+; CHECK-NEXT:    vmov r0, s2
+; CHECK-NEXT:    vmov.16 d0[3], r0
+; CHECK-NEXT:    bx lr
+bb:
+  %z = fptrunc <4 x double> %a to <4 x half>
+  ret <4 x half> %z
+}
+
+define <4 x float> @fpext_vector_f16_f32(<4 x half> %a) {
+; CHECK-LABEL: fpext_vector_f16_f32:
+; CHECK:       @ %bb.0: @ %bb
+; CHECK-NEXT:    vcvt.f32.f16 q0, d0
+; CHECK-NEXT:    bx lr
+bb:
+  %z = fpext <4 x half> %a to <4 x float>
+  ret <4 x float> %z
+}
+
+define <4 x double> @fpext_vector_f16_f64(<4 x half> %a) {
+; CHECK-LABEL: fpext_vector_f16_f64:
+; CHECK:       @ %bb.0: @ %bb
+; CHECK-NEXT:    vmovx.f16 s4, s0
+; CHECK-NEXT:    vmovx.f16 s2, s1
+; CHECK-NEXT:    vcvtb.f64.f16 d17, s4
+; CHECK-NEXT:    vcvtb.f64.f16 d3, s2
+; CHECK-NEXT:    vcvtb.f64.f16 d16, s0
+; CHECK-NEXT:    vcvtb.f64.f16 d2, s1
+; CHECK-NEXT:    vorr q0, q8, q8
+; CHECK-NEXT:    bx lr
+bb:
+  %z = fpext <4 x half> %a to <4 x double>
+  ret <4 x double> %z
+}