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Differential D118335

[VE] Packed v512f32 binop isel and tests
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Authored by simoll on Jan 27 2022, 1:35 AM.

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Reviewers
kaz7
Commits
rG31cca9e6ba99: [VE] Packed v512f32 binop isel and tests

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Event Timeline

simoll created this revision.Jan 27 2022, 1:35 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptJan 27 2022, 1:35 AM
simoll requested review of this revision.Jan 27 2022, 1:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 27 2022, 1:35 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
simoll added a parent revision: D118321: [VE] LEGALAVL and staged VVP legalization.Jan 27 2022, 1:36 AM
Harbormaster completed remote builds in B145952: Diff 403546.Jan 27 2022, 9:20 AM
kaz7 accepted this revision.Jan 31 2022, 4:46 PM

LGTM

This revision is now accepted and ready to land.Jan 31 2022, 4:46 PM
kaz7 mentioned this in D118332: [VE] Packed v512i32 isel and tests.Jan 31 2022, 4:52 PM
This revision was landed with ongoing or failed builds.Feb 2 2022, 1:10 AM
Closed by commit rG31cca9e6ba99: [VE] Packed v512f32 binop isel and tests (authored by simoll). · Explain Why
This revision was automatically updated to reflect the committed changes.
simoll added a commit: rG31cca9e6ba99: [VE] Packed v512f32 binop isel and tests.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
7 lines
test/
CodeGen/
VE/
Packed/
53 lines
53 lines
56 lines

Diff 405168

llvm/lib/Target/VE/VVPInstrPatternsVec.td

Show First 20 Lines • Show All 231 Lines • ▼ Show 20 Linesdefm : Binary_rv_vv_ShortLong<c_vvp_fmul,
f32, v256f32, "PVFMULUP">; f32, v256f32, "PVFMULUP">;
defm : Binary_rv_vv_ShortLong<vvp_fsub, defm : Binary_rv_vv_ShortLong<vvp_fsub,
f64, v256f64, "VFSUBD", f64, v256f64, "VFSUBD",
f32, v256f32, "PVFSUBUP">; f32, v256f32, "PVFSUBUP">;
defm : Binary_rv_vr_vv_ShortLong<vvp_fdiv, defm : Binary_rv_vr_vv_ShortLong<vvp_fdiv,
f64, v256f64, "VFDIVD", f64, v256f64, "VFDIVD",
f32, v256f32, "VFDIVS">; f32, v256f32, "VFDIVS">;
defm : Binary_rv_vv<c_vvp_fadd,
i64, v512f32, v512i1, "PVFADD">;
defm : Binary_rv_vv<c_vvp_fmul,
i64, v512f32, v512i1, "PVFMUL">;
defm : Binary_rv_vv<vvp_fsub,
i64, v512f32, v512i1, "PVFSUB">;
multiclass Merge_mvv< multiclass Merge_mvv<
SDPatternOperator OpNode, SDPatternOperator OpNode,
ValueType DataVT, ValueType MaskVT, ValueType DataVT, ValueType MaskVT,
string OpBaseName> { string OpBaseName> {
// Masked. // Masked.
def : Pat<(OpNode def : Pat<(OpNode
DataVT:$vtrue, DataVT:$vfalse, DataVT:$vtrue, DataVT:$vfalse,
MaskVT:$vm, MaskVT:$vm,
Show All 23 Lines

llvm/test/CodeGen/VE/Packed/vp_fadd.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <512 x float> @llvm.vp.fadd.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
define fastcc <512 x float> @test_vp_fadd_v512f32_vv(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fadd_v512f32_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvfadd %v0, %v0, %v1, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <512 x float> @llvm.vp.fadd.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
ret <512 x float> %r0
}
define fastcc <512 x float> @test_vp_fadd_v512f32_rv(float %s0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fadd_v512f32_rv:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s2, %s0, (32)1
; CHECK-NEXT: srl %s0, %s0, 32
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvfadd %v0, %s0, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <512 x float> undef, float %s0, i32 0
%i0 = shufflevector <512 x float> %xins, <512 x float> undef, <512 x i32> zeroinitializer
%r0 = call <512 x float> @llvm.vp.fadd.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
ret <512 x float> %r0
}
define fastcc <512 x float> @test_vp_fadd_v512f32_vr(<512 x float> %i0, float %s1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fadd_v512f32_vr:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s2, %s0, (32)1
; CHECK-NEXT: srl %s0, %s0, 32
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvfadd %v0, %s0, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <512 x float> undef, float %s1, i32 0
%i1 = shufflevector <512 x float> %yins, <512 x float> undef, <512 x i32> zeroinitializer
%r0 = call <512 x float> @llvm.vp.fadd.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
ret <512 x float> %r0
}

llvm/test/CodeGen/VE/Packed/vp_fmul.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <512 x float> @llvm.vp.fmul.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
define fastcc <512 x float> @test_vp_fmul_v512f32_vv(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fmul_v512f32_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvfmul %v0, %v0, %v1, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
ret <512 x float> %r0
}
define fastcc <512 x float> @test_vp_fmul_v512f32_rv(float %s0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fmul_v512f32_rv:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s2, %s0, (32)1
; CHECK-NEXT: srl %s0, %s0, 32
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvfmul %v0, %s0, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <512 x float> undef, float %s0, i32 0
%i0 = shufflevector <512 x float> %xins, <512 x float> undef, <512 x i32> zeroinitializer
%r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
ret <512 x float> %r0
}
define fastcc <512 x float> @test_vp_fmul_v512f32_vr(<512 x float> %i0, float %s1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fmul_v512f32_vr:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s2, %s0, (32)1
; CHECK-NEXT: srl %s0, %s0, 32
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvfmul %v0, %s0, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <512 x float> undef, float %s1, i32 0
%i1 = shufflevector <512 x float> %yins, <512 x float> undef, <512 x i32> zeroinitializer
%r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
ret <512 x float> %r0
}

llvm/test/CodeGen/VE/Packed/vp_fsub.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <512 x float> @llvm.vp.fsub.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
define fastcc <512 x float> @test_vp_fsub_v512f32_vv(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fsub_v512f32_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvfsub %v0, %v0, %v1, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <512 x float> @llvm.vp.fsub.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
ret <512 x float> %r0
}
define fastcc <512 x float> @test_vp_fsub_v512f32_rv(float %s0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fsub_v512f32_rv:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s2, %s0, (32)1
; CHECK-NEXT: srl %s0, %s0, 32
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvfsub %v0, %s0, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <512 x float> undef, float %s0, i32 0
%i0 = shufflevector <512 x float> %xins, <512 x float> undef, <512 x i32> zeroinitializer
%r0 = call <512 x float> @llvm.vp.fsub.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
ret <512 x float> %r0
}
define fastcc <512 x float> @test_vp_fsub_v512f32_vr(<512 x float> %i0, float %s1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fsub_v512f32_vr:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s2, %s0, (32)1
; CHECK-NEXT: srl %s0, %s0, 32
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: adds.w.sx %s0, 1, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvfsub %v0, %v0, %v1, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <512 x float> undef, float %s1, i32 0
%i1 = shufflevector <512 x float> %yins, <512 x float> undef, <512 x i32> zeroinitializer
%r0 = call <512 x float> @llvm.vp.fsub.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
ret <512 x float> %r0
}