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Differential D118332

[VE] Packed v512i32 isel and tests
ClosedPublic

Authored by simoll on Jan 27 2022, 1:07 AM.

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Reviewers
kaz7
Commits
rG73ac3b137101: [VE] Packed v512i32 isel and tests

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Event Timeline

simoll created this revision.Jan 27 2022, 1:07 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptJan 27 2022, 1:07 AM
simoll requested review of this revision.Jan 27 2022, 1:07 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 27 2022, 1:07 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
simoll added a parent revision: D118321: [VE] LEGALAVL and staged VVP legalization.Jan 27 2022, 1:08 AM
Harbormaster completed remote builds in B145949: Diff 403542.Jan 27 2022, 9:13 AM
kaz7 added a comment.Jan 31 2022, 4:52 PM

Is it possible to add "vr" and "rv" test cases similar to D118335?

simoll updated this revision to Diff 405221.Feb 2 2022, 4:51 AM

Add rv and vr operand tests

Harbormaster completed remote builds in B147101: Diff 405221.Feb 2 2022, 5:54 AM
kaz7 accepted this revision.Feb 2 2022, 7:36 PM

Thanks. LGTM.

This revision is now accepted and ready to land.Feb 2 2022, 7:36 PM
This revision was landed with ongoing or failed builds.Feb 3 2022, 2:03 AM
Closed by commit rG73ac3b137101: [VE] Packed v512i32 isel and tests (authored by simoll). · Explain Why
This revision was automatically updated to reflect the committed changes.
simoll added a commit: rG73ac3b137101: [VE] Packed v512i32 isel and tests.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
18 lines
test/
CodeGen/
VE/
Packed/
55 lines
55 lines
55 lines
58 lines
58 lines
58 lines
58 lines
55 lines

Diff 405549

llvm/lib/Target/VE/VVPInstrPatternsVec.td

Show First 20 Lines • Show All 231 Lines • ▼ Show 20 Linesdefm : Binary_rv_vv_ShortLong<c_vvp_fmul,
f32, v256f32, "PVFMULUP">; f32, v256f32, "PVFMULUP">;
defm : Binary_rv_vv_ShortLong<vvp_fsub, defm : Binary_rv_vv_ShortLong<vvp_fsub,
f64, v256f64, "VFSUBD", f64, v256f64, "VFSUBD",
f32, v256f32, "PVFSUBUP">; f32, v256f32, "PVFSUBUP">;
defm : Binary_rv_vr_vv_ShortLong<vvp_fdiv, defm : Binary_rv_vr_vv_ShortLong<vvp_fdiv,
f64, v256f64, "VFDIVD", f64, v256f64, "VFDIVD",
f32, v256f32, "VFDIVS">; f32, v256f32, "VFDIVS">;
defm : Binary_rv_vv<c_vvp_and,
i64, v512i32, v512i1, "PVAND">;
defm : Binary_rv_vv<c_vvp_or,
i64, v512i32, v512i1, "PVOR">;
defm : Binary_rv_vv<c_vvp_xor,
i64, v512i32, v512i1, "PVXOR">;
defm : Binary_rv_vv<c_vvp_add,
i64, v512i32, v512i1, "PVADDU">;
defm : Binary_rv_vv<vvp_sub,
i64, v512i32, v512i1, "PVSUBU">;
defm : Binary_vr_vv<vvp_srl,
i64, v512i32, v512i1, "PVSRL">;
defm : Binary_vr_vv<vvp_sra,
i64, v512i32, v512i1, "PVSRA">;
defm : Binary_vr_vv<vvp_shl,
i64, v512i32, v512i1, "PVSLL">;
defm : Binary_rv_vv<c_vvp_fadd, defm : Binary_rv_vv<c_vvp_fadd,
i64, v512f32, v512i1, "PVFADD">; i64, v512f32, v512i1, "PVFADD">;
defm : Binary_rv_vv<c_vvp_fmul, defm : Binary_rv_vv<c_vvp_fmul,
i64, v512f32, v512i1, "PVFMUL">; i64, v512f32, v512i1, "PVFMUL">;
defm : Binary_rv_vv<vvp_fsub, defm : Binary_rv_vv<vvp_fsub,
i64, v512f32, v512i1, "PVFSUB">; i64, v512f32, v512i1, "PVFSUB">;
multiclass Merge_mvv< multiclass Merge_mvv<
Show All 30 Lines

llvm/test/CodeGen/VE/Packed/vp_add.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.add.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
define fastcc <512 x i32> @test_vp_add_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_add_v512i32_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvaddu %v0, %v0, %v1, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <512 x i32> @llvm.vp.add.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_add_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_add_v512i32_rv:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvaddu %v0, %s0, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <512 x i32> undef, i32 %s0, i32 0
%i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.add.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_add_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_add_v512i32_vr:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvaddu %v0, %s0, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <512 x i32> undef, i32 %s1, i32 0
%i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.add.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}

llvm/test/CodeGen/VE/Packed/vp_and.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.and.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
define fastcc <512 x i32> @test_vp_and_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_and_v512i32_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvand %v0, %v0, %v1, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <512 x i32> @llvm.vp.and.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_and_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_and_v512i32_rv:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvand %v0, %s0, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <512 x i32> undef, i32 %s0, i32 0
%i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.and.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_and_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_and_v512i32_vr:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvand %v0, %s0, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <512 x i32> undef, i32 %s1, i32 0
%i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.and.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}

llvm/test/CodeGen/VE/Packed/vp_or.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.or.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
define fastcc <512 x i32> @test_vp_or_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_or_v512i32_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvor %v0, %v0, %v1, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <512 x i32> @llvm.vp.or.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_or_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_or_v512i32_rv:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvor %v0, %s0, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <512 x i32> undef, i32 %s0, i32 0
%i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.or.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_or_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_or_v512i32_vr:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvor %v0, %s0, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <512 x i32> undef, i32 %s1, i32 0
%i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.or.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}

llvm/test/CodeGen/VE/Packed/vp_shl.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.shl.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
define fastcc <512 x i32> @test_vp_shl_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_shl_v512i32_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvsll %v0, %v0, %v1, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <512 x i32> @llvm.vp.shl.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_shl_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_shl_v512i32_rv:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: adds.w.sx %s0, 1, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvsll %v0, %v1, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <512 x i32> undef, i32 %s0, i32 0
%i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.shl.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_shl_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_shl_v512i32_vr:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvsll %v0, %v0, %s0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <512 x i32> undef, i32 %s1, i32 0
%i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.shl.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}

llvm/test/CodeGen/VE/Packed/vp_sra.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.ashr.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
define fastcc <512 x i32> @test_vp_ashr_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_ashr_v512i32_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvsra %v0, %v0, %v1, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <512 x i32> @llvm.vp.ashr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_ashr_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_ashr_v512i32_rv:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: adds.w.sx %s0, 1, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvsra %v0, %v1, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <512 x i32> undef, i32 %s0, i32 0
%i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.ashr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_ashr_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_ashr_v512i32_vr:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvsra %v0, %v0, %s0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <512 x i32> undef, i32 %s1, i32 0
%i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.ashr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}

llvm/test/CodeGen/VE/Packed/vp_srl.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
define fastcc <512 x i32> @test_vp_lshr_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_lshr_v512i32_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvsrl %v0, %v0, %v1, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_lshr_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_lshr_v512i32_rv:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: adds.w.sx %s0, 1, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvsrl %v0, %v1, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <512 x i32> undef, i32 %s0, i32 0
%i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_lshr_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_lshr_v512i32_vr:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvsrl %v0, %v0, %s0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <512 x i32> undef, i32 %s1, i32 0
%i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}

llvm/test/CodeGen/VE/Packed/vp_sub.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.sub.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
define fastcc <512 x i32> @test_vp_sub_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_sub_v512i32_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvsubu %v0, %v0, %v1, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <512 x i32> @llvm.vp.sub.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_sub_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_sub_v512i32_rv:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvsubu %v0, %s0, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <512 x i32> undef, i32 %s0, i32 0
%i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.sub.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_sub_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_sub_v512i32_vr:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: adds.w.sx %s0, 1, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvsubu %v0, %v0, %v1, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <512 x i32> undef, i32 %s1, i32 0
%i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.sub.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}

llvm/test/CodeGen/VE/Packed/vp_xor.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.xor.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
define fastcc <512 x i32> @test_vp_xor_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_xor_v512i32_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 1, %s0
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvxor %v0, %v0, %v1, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <512 x i32> @llvm.vp.xor.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_xor_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_xor_v512i32_rv:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvxor %v0, %s0, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <512 x i32> undef, i32 %s0, i32 0
%i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.xor.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}
define fastcc <512 x i32> @test_vp_xor_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_xor_v512i32_vr:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: sll %s2, %s0, 32
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: adds.w.sx %s1, 1, %s1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: srl %s1, %s1, 1
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvxor %v0, %s0, %v0, %vm2
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <512 x i32> undef, i32 %s1, i32 0
%i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
%r0 = call <512 x i32> @llvm.vp.xor.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
ret <512 x i32> %r0
}