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Differential D118115

[AVR][NFC] Improve CodeGen tests
AbandonedPublic

Authored by benshi001 on Jan 25 2022, 2:16 AM.

Details

Reviewers
aykevl
MaskRay
dylanmckay
Summary

Add '-verify-machineinstrs' to all CodeGen tests.

Diff Detail

Event Timeline

benshi001 created this revision.Jan 25 2022, 2:16 AM
Herald added subscribers: Jim, qcolombet, MatzeB. · View Herald TranscriptJan 25 2022, 2:16 AM
benshi001 requested review of this revision.Jan 25 2022, 2:16 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 25 2022, 2:16 AM
Herald added subscribers: llvm-commits, jacquesguan. · View Herald Transcript
benshi001 added a comment.Jan 25 2022, 2:18 AM

Most AVR CodeGen tests lack -verify-machineinstrs options, so there are potential failures even make check-all passes.

So I add -verify-machineinstrs to all AVR CodeGen tests.

MaskRay added a comment.Jan 25 2022, 1:05 PM

I don't think we should clutter up tests. -DLLVM_ENABLE_EXPENSIVE_CHECKS=on implies -verify-machineinstrs. There may be a proposal to enable -verify-machineinstrs automatically.

The problem may be to ensure isMachineVerifierClean returning false for AVR is correct.

MaskRay requested changes to this revision.Jan 25 2022, 1:06 PM
This revision now requires changes to proceed.Jan 25 2022, 1:06 PM
benshi001 added a comment.Jan 25 2022, 7:08 PM
In D118115#3270522, @MaskRay wrote:

I don't think we should clutter up tests. -DLLVM_ENABLE_EXPENSIVE_CHECKS=on implies -verify-machineinstrs. There may be a proposal to enable -verify-machineinstrs automatically.

The problem may be to ensure isMachineVerifierClean returning false for AVR is correct.

Thanks. The AVRTargetMachine does not inherit the virtual base isMachineVerifierClean and always get true with -DLLVM_ENABLE_EXPENSIVE_CHECKS=on.

benshi001 abandoned this revision.Jan 25 2022, 7:10 PM
MatzeB added a comment.EditedJan 25 2022, 7:11 PM

See also https://llvm.org/PR32146 where we keep track which targets are not "clean" yet.

MatzeB added a comment.Jan 25 2022, 7:25 PM

There apparently was https://reviews.llvm.org/D107853 though. Maybe people didn't actually test with an expensive checks enabled build (or with llvm-lit -Dllc="llc -verify-machineinstr")

Harbormaster completed remote builds in B145432: Diff 402806.Jan 26 2022, 2:02 PM

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Diff 402806

llvm/test/CodeGen/AVR/PR31344.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; Unit test for: PR 31344 ; Unit test for: PR 31344
define i16 @or16_reg_imm_0xff00(i16 %a) { define i16 @or16_reg_imm_0xff00(i16 %a) {
; CHECK-LABEL: or16_reg_imm_0xff00 ; CHECK-LABEL: or16_reg_imm_0xff00
; CHECK-NOT: ori {{r[0-9]+}}, 0 ; CHECK-NOT: ori {{r[0-9]+}}, 0
; CHECK: ori {{r[0-9]+}}, 255 ; CHECK: ori {{r[0-9]+}}, 255
%result = or i16 %a, 65280 %result = or i16 %a, 65280
Show All 26 Lines

llvm/test/CodeGen/AVR/PR31345.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; Unit test for: PR 31345 ; Unit test for: PR 31345
define i16 @and16_reg_imm_0xff00(i16 %a) { define i16 @and16_reg_imm_0xff00(i16 %a) {
; CHECK-LABEL: and16_reg_imm_0xff00 ; CHECK-LABEL: and16_reg_imm_0xff00
; CHECK: andi {{r[0-9]+}}, 0 ; CHECK: andi {{r[0-9]+}}, 0
; CHECK-NOT: andi {{r[0-9]+}}, 255 ; CHECK-NOT: andi {{r[0-9]+}}, 255
%result = and i16 %a, 65280 %result = and i16 %a, 65280
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines

llvm/test/CodeGen/AVR/add.ll

; RUN: llc -mattr=addsubiw < %s -march=avr | FileCheck %s ; RUN: llc -mattr=addsubiw < %s -march=avr -verify-machineinstrs | FileCheck %s
define i8 @add8_reg_reg(i8 %a, i8 %b) { define i8 @add8_reg_reg(i8 %a, i8 %b) {
; CHECK-LABEL: add8_reg_reg: ; CHECK-LABEL: add8_reg_reg:
; CHECK: add r24, r22 ; CHECK: add r24, r22
%result = add i8 %a, %b %result = add i8 %a, %b
ret i8 %result ret i8 %result
} }
▲ Show 20 Lines • Show All 129 Lines • Show Last 20 Lines

llvm/test/CodeGen/AVR/alloca.ll

; RUN: llc < %s -march=avr -mattr=avr6 | FileCheck %s ; RUN: llc < %s -march=avr -mattr=avr6 -verify-machineinstrs | FileCheck %s
declare i16 @allocate(i16*, i16*) declare i16 @allocate(i16*, i16*)
; Test taking an address of an alloca with a small offset (adiw) ; Test taking an address of an alloca with a small offset (adiw)
define i16 @alloca_addressof_small() { define i16 @alloca_addressof_small() {
entry: entry:
; CHECK-LABEL: alloca_addressof_small: ; CHECK-LABEL: alloca_addressof_small:
; Test that Y is saved ; Test that Y is saved
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines

llvm/test/CodeGen/AVR/and.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
define i8 @and8_reg_reg(i8 %a, i8 %b) { define i8 @and8_reg_reg(i8 %a, i8 %b) {
; CHECK-LABEL: and8_reg_reg: ; CHECK-LABEL: and8_reg_reg:
; CHECK: and r24, r22 ; CHECK: and r24, r22
%result = and i8 %a, %b %result = and i8 %a, %b
ret i8 %result ret i8 %result
} }
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

llvm/test/CodeGen/AVR/atomics/fence.ll

; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
; Checks that atomic fences are simply removed from IR. ; Checks that atomic fences are simply removed from IR.
; AVR is always singlethreaded so fences do nothing. ; AVR is always singlethreaded so fences do nothing.
; CHECK_LABEL: atomic_fence8 ; CHECK_LABEL: atomic_fence8
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @atomic_fence8() { define void @atomic_fence8() {
fence acquire fence acquire
ret void ret void
} }

llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; At one point, the 16-vit atomic load/store operations we defined in TableGen ; At one point, the 16-vit atomic load/store operations we defined in TableGen
; to use 'PTRREGS', but the pseudo expander would generate LDDW/STDW instructions. ; to use 'PTRREGS', but the pseudo expander would generate LDDW/STDW instructions.
; ;
; This would sometimes cause codegen to fail because LDDW requires 'PTRDISPREGS', and ; This would sometimes cause codegen to fail because LDDW requires 'PTRDISPREGS', and
; so if we attempted to generate an atomic operation on the X register, it would hit ; so if we attempted to generate an atomic operation on the X register, it would hit
; an assertion; ; an assertion;
Show All 14 Lines

llvm/test/CodeGen/AVR/atomics/load16.ll

; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: atomic_load16 ; CHECK-LABEL: atomic_load16
; CHECK: in r0, 63 ; CHECK: in r0, 63
; CHECK-NEXT: cli ; CHECK-NEXT: cli
; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]] ; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]
; CHECK-NEXT: ldd [[RR:r[0-9]+]], [[RD]]+1 ; CHECK-NEXT: ldd [[RR:r[0-9]+]], [[RD]]+1
; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: out 63, r0
define i16 @atomic_load16(i16* %foo) { define i16 @atomic_load16(i16* %foo) {
▲ Show 20 Lines • Show All 128 Lines • Show Last 20 Lines

llvm/test/CodeGen/AVR/atomics/load32.ll

; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: atomic_load32 ; CHECK-LABEL: atomic_load32
; CHECK: call __sync_val_compare_and_swap_4 ; CHECK: call __sync_val_compare_and_swap_4
define i32 @atomic_load32(i32* %foo) { define i32 @atomic_load32(i32* %foo) {
%val = load atomic i32, i32* %foo unordered, align 4 %val = load atomic i32, i32* %foo unordered, align 4
ret i32 %val ret i32 %val
} }
; CHECK-LABEL: atomic_load_sub32 ; CHECK-LABEL: atomic_load_sub32
; CHECK: call __sync_fetch_and_sub_4 ; CHECK: call __sync_fetch_and_sub_4
define i32 @atomic_load_sub32(i32* %foo) { define i32 @atomic_load_sub32(i32* %foo) {
%val = atomicrmw sub i32* %foo, i32 13 seq_cst %val = atomicrmw sub i32* %foo, i32 13 seq_cst
ret i32 %val ret i32 %val
} }

llvm/test/CodeGen/AVR/atomics/load64.ll

; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: atomic_load64 ; CHECK-LABEL: atomic_load64
; CHECK: call __sync_val_compare_and_swap_8 ; CHECK: call __sync_val_compare_and_swap_8
define i64 @atomic_load64(i64* %foo) { define i64 @atomic_load64(i64* %foo) {
%val = load atomic i64, i64* %foo unordered, align 8 %val = load atomic i64, i64* %foo unordered, align 8
ret i64 %val ret i64 %val
} }
; CHECK-LABEL: atomic_load_sub64 ; CHECK-LABEL: atomic_load_sub64
; CHECK: call __sync_fetch_and_sub_8 ; CHECK: call __sync_fetch_and_sub_8
define i64 @atomic_load_sub64(i64* %foo) { define i64 @atomic_load_sub64(i64* %foo) {
%val = atomicrmw sub i64* %foo, i64 13 seq_cst %val = atomicrmw sub i64* %foo, i64 13 seq_cst
ret i64 %val ret i64 %val
} }

llvm/test/CodeGen/AVR/atomics/load8.ll

; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
; Tests atomic operations on AVR ; Tests atomic operations on AVR
; CHECK-LABEL: atomic_load8 ; CHECK-LABEL: atomic_load8
; CHECK: in r0, 63 ; CHECK: in r0, 63
; CHECK-NEXT: cli ; CHECK-NEXT: cli
; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]] ; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]
; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: out 63, r0
▲ Show 20 Lines • Show All 115 Lines • Show Last 20 Lines

llvm/test/CodeGen/AVR/atomics/store.ll

; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: atomic_store8 ; CHECK-LABEL: atomic_store8
; CHECK: in r0, 63 ; CHECK: in r0, 63
; CHECK-NEXT: cli ; CHECK-NEXT: cli
; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]] ; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: out 63, r0
define void @atomic_store8(i8* %foo) { define void @atomic_store8(i8* %foo) {
store atomic i8 1, i8* %foo unordered, align 1 store atomic i8 1, i8* %foo unordered, align 1
Show All 28 Lines

llvm/test/CodeGen/AVR/atomics/store16.ll

; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: atomic_store16 ; CHECK-LABEL: atomic_store16
; CHECK: in r0, 63 ; CHECK: in r0, 63
; CHECK-NEXT: cli ; CHECK-NEXT: cli
; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]] ; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
; CHECK-NEXT: std [[RD:(X|Y|Z)]]+1, [[RR:r[0-9]+]] ; CHECK-NEXT: std [[RD:(X|Y|Z)]]+1, [[RR:r[0-9]+]]
; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: out 63, r0
define void @atomic_store16(i16* %foo) { define void @atomic_store16(i16* %foo) {
Show All 16 Lines

llvm/test/CodeGen/AVR/atomics/swap.ll

; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: atomic_swap8 ; CHECK-LABEL: atomic_swap8
; CHECK: call __sync_lock_test_and_set_1 ; CHECK: call __sync_lock_test_and_set_1
define i8 @atomic_swap8(i8* %foo) { define i8 @atomic_swap8(i8* %foo) {
%val = atomicrmw xchg i8* %foo, i8 13 seq_cst %val = atomicrmw xchg i8* %foo, i8 13 seq_cst
ret i8 %val ret i8 %val
} }
Show All 21 Lines

llvm/test/CodeGen/AVR/avr-rust-issue-123.ll

; RUN: llc -O1 < %s -march=avr | FileCheck %s ; RUN: llc -O1 < %s -march=avr -verify-machineinstrs | FileCheck %s
; This test ensures that the Select8/Select16 expansion ; This test ensures that the Select8/Select16 expansion
; pass inserts an unconditional branch to the previous adjacent ; pass inserts an unconditional branch to the previous adjacent
; basic block when inserting new basic blocks when the ; basic block when inserting new basic blocks when the
; prior block has a fallthrough. ; prior block has a fallthrough.
; ;
; Before this bug was fixed, Select8/Select16 expansion ; Before this bug was fixed, Select8/Select16 expansion
; would leave a dangling fallthrough to an undefined block. ; would leave a dangling fallthrough to an undefined block.
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llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll

; RUN: llc -mcpu=atmega328 < %s -march=avr | FileCheck %s ; RUN: llc -mcpu=atmega328 < %s -march=avr -verify-machineinstrs | FileCheck %s
; This test verifies that the pointer to a basic block ; This test verifies that the pointer to a basic block
; should always be a pointer in address space 1. ; should always be a pointer in address space 1.
; ;
; If this were not the case, then programs targeting ; If this were not the case, then programs targeting
; AVR that attempted to read their own machine code ; AVR that attempted to read their own machine code
; via a pointer to a label would actually read from RAM ; via a pointer to a label would actually read from RAM
; using a pointer relative to the the start of program flash. ; using a pointer relative to the the start of program flash.
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llvm/test/CodeGen/AVR/branch-relaxation-long.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: relax_to_jmp: ; CHECK-LABEL: relax_to_jmp:
; CHECK: cpi r{{[0-9]+}}, 0 ; CHECK: cpi r{{[0-9]+}}, 0
; CHECK: brne [[BB1:.LBB[0-9]+_[0-9]+]] ; CHECK: brne [[BB1:.LBB[0-9]+_[0-9]+]]
; CHECK: jmp [[BB2:.LBB[0-9]+_[0-9]+]] ; CHECK: jmp [[BB2:.LBB[0-9]+_[0-9]+]]
; CHECK: [[BB1]]: ; CHECK: [[BB1]]:
; CHECK: nop ; CHECK: nop
; CHECK: [[BB2]]: ; CHECK: [[BB2]]:
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llvm/test/CodeGen/AVR/branch-relaxation.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: relax_breq ; CHECK-LABEL: relax_breq
; CHECK: cpi r{{[0-9]+}}, 0 ; CHECK: cpi r{{[0-9]+}}, 0
; CHECK: brne .LBB0_1 ; CHECK: brne .LBB0_1
; CHECK: rjmp .LBB0_2 ; CHECK: rjmp .LBB0_2
; .LBB0_1: ; .LBB0_1:
define i8 @relax_breq(i1 %a) { define i8 @relax_breq(i1 %a) {
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llvm/test/CodeGen/AVR/call.ll

; RUN: llc < %s -march=avr -mattr=avr6 | FileCheck %s ; RUN: llc < %s -march=avr -mattr=avr6 -verify-machineinstrs | FileCheck %s
; TODO: test returning byval structs ; TODO: test returning byval structs
declare i8 @foo8_1(i8) declare i8 @foo8_1(i8)
declare i8 @foo8_2(i8, i8, i8) declare i8 @foo8_2(i8, i8, i8)
declare i8 @foo8_3(i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8) declare i8 @foo8_3(i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8)
declare i16 @foo16_1(i16, i16) declare i16 @foo16_1(i16, i16)
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llvm/test/CodeGen/AVR/calling-conv/c/basic.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: ret_void_args_i8 ; CHECK-LABEL: ret_void_args_i8
define void @ret_void_args_i8(i8 %a) { define void @ret_void_args_i8(i8 %a) {
; CHECK: sts 4, r24 ; CHECK: sts 4, r24
store volatile i8 %a, i8* inttoptr (i64 4 to i8*) store volatile i8 %a, i8* inttoptr (i64 4 to i8*)
ret void ret void
} }
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llvm/test/CodeGen/AVR/calling-conv/c/basic_aggr.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: ret_void_args_struct_i8_i32 ; CHECK-LABEL: ret_void_args_struct_i8_i32
define void @ret_void_args_struct_i8_i32({ i8, i32 } %a) { define void @ret_void_args_struct_i8_i32({ i8, i32 } %a) {
start: start:
; CHECK: sts 4, r20 ; CHECK: sts 4, r20
%0 = extractvalue { i8, i32 } %a, 0 %0 = extractvalue { i8, i32 } %a, 0
store volatile i8 %0, i8* inttoptr (i64 4 to i8*) store volatile i8 %0, i8* inttoptr (i64 4 to i8*)
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llvm/test/CodeGen/AVR/calling-conv/c/call.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
declare void @ret_void_args_i8(i8 %a) declare void @ret_void_args_i8(i8 %a)
declare void @ret_void_args_i8_i32(i8 %a, i32 %b) declare void @ret_void_args_i8_i32(i8 %a, i32 %b)
declare void @ret_void_args_i8_i8_i8_i8(i8 %a, i8 %b, i8 %c, i8 %d) declare void @ret_void_args_i8_i8_i8_i8(i8 %a, i8 %b, i8 %c, i8 %d)
declare void @ret_void_args_i32_i16_i8(i32 %a, i16 %b, i8 %c) declare void @ret_void_args_i32_i16_i8(i32 %a, i16 %b, i8 %c)
declare void @ret_void_args_i64(i64 %a) declare void @ret_void_args_i64(i64 %a)
declare void @ret_void_args_i64_i64(i64 %a, i64 %b) declare void @ret_void_args_i64_i64(i64 %a, i64 %b)
declare void @ret_void_args_i64_i64_i16(i64 %a, i64 %b, i16 %c) declare void @ret_void_args_i64_i64_i16(i64 %a, i64 %b, i16 %c)
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llvm/test/CodeGen/AVR/calling-conv/c/call_aggr.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
declare void @ret_void_args_struct_i8_i32({ i8, i32 } %a) declare void @ret_void_args_struct_i8_i32({ i8, i32 } %a)
declare void @ret_void_args_struct_i8_i8_i8_i8({ i8, i8, i8, i8 } %a) declare void @ret_void_args_struct_i8_i8_i8_i8({ i8, i8, i8, i8 } %a)
declare void @ret_void_args_struct_i32_i16_i8({ i32, i16, i8} %a) declare void @ret_void_args_struct_i32_i16_i8({ i32, i16, i8} %a)
declare void @ret_void_args_struct_i8_i32_struct_i32_i8({ i8, i32 } %a, { i32, i8 } %b) declare void @ret_void_args_struct_i8_i32_struct_i32_i8({ i8, i32 } %a, { i32, i8 } %b)
; CHECK-LABEL: call_void_args_struct_i8_i32 ; CHECK-LABEL: call_void_args_struct_i8_i32
define void @call_void_args_struct_i8_i32() { define void @call_void_args_struct_i8_i32() {
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llvm/test/CodeGen/AVR/calling-conv/c/return.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: ret_i8 ; CHECK-LABEL: ret_i8
define i8 @ret_i8() { define i8 @ret_i8() {
; CHECK: ldi r24, 64 ; CHECK: ldi r24, 64
ret i8 64 ret i8 64
} }
; CHECK-LABEL: ret_i16 ; CHECK-LABEL: ret_i16
Show All 27 Lines

llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: ret_struct_i8_i16_i8 ; CHECK-LABEL: ret_struct_i8_i16_i8
define { i8, i16, i8 } @ret_struct_i8_i16_i8() { define { i8, i16, i8 } @ret_struct_i8_i16_i8() {
start: start:
; for some reason the i16 is loaded to r24:r25 ; for some reason the i16 is loaded to r24:r25
; and then moved to r23:r24 ; and then moved to r23:r24
; CHECK: ldi r22, 64 ; CHECK: ldi r22, 64
; CHECK-NEXT: r23, ; CHECK-NEXT: r23,
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llvm/test/CodeGen/AVR/calling-conv/c/stack.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: ret_void_args_i64_i64_i32 ; CHECK-LABEL: ret_void_args_i64_i64_i32
define void @ret_void_args_i64_i64_i32(i64 %a, i64 %b, i32 %c) { define void @ret_void_args_i64_i64_i32(i64 %a, i64 %b, i32 %c) {
; We're goign to clobber PTRREG Y ; We're goign to clobber PTRREG Y
; CHECK: push r28 ; CHECK: push r28
; CHECK-NEXT: push r29 ; CHECK-NEXT: push r29
; Load the stack pointer into Y. ; Load the stack pointer into Y.
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llvm/test/CodeGen/AVR/clear-bss.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK: .globl __do_clear_bss ; CHECK: .globl __do_clear_bss
@zeroed = internal constant [3 x i8] zeroinitializer @zeroed = internal constant [3 x i8] zeroinitializer

llvm/test/CodeGen/AVR/cmp.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
declare void @f1(i8) declare void @f1(i8)
declare void @f2(i8) declare void @f2(i8)
define void @cmp8(i8 %a, i8 %b) { define void @cmp8(i8 %a, i8 %b) {
; CHECK-LABEL: cmp8: ; CHECK-LABEL: cmp8:
; CHECK: cp ; CHECK: cp
; CHECK-NOT: cpc ; CHECK-NOT: cpc
%cmp = icmp eq i8 %a, %b %cmp = icmp eq i8 %a, %b
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llvm/test/CodeGen/AVR/com.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=avr | FileCheck %s ; RUN: llc < %s -mtriple=avr -verify-machineinstrs | FileCheck %s
define i8 @com8(i8 %x) { define i8 @com8(i8 %x) {
; CHECK-LABEL: com8: ; CHECK-LABEL: com8:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: com r24 ; CHECK-NEXT: com r24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%neg = xor i8 %x, -1 %neg = xor i8 %x, -1
ret i8 %neg ret i8 %neg
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llvm/test/CodeGen/AVR/copy-data-to-ram.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK: .globl __do_copy_data ; CHECK: .globl __do_copy_data
@str = internal global [3 x i8] c"foo" @str = internal global [3 x i8] c"foo"

llvm/test/CodeGen/AVR/ctlz.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
define i8 @count_leading_zeros(i8) unnamed_addr { define i8 @count_leading_zeros(i8) unnamed_addr {
entry-block: entry-block:
%1 = tail call i8 @llvm.ctlz.i8(i8 %0) %1 = tail call i8 @llvm.ctlz.i8(i8 %0)
ret i8 %1 ret i8 %1
} }
declare i8 @llvm.ctlz.i8(i8) declare i8 @llvm.ctlz.i8(i8)
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llvm/test/CodeGen/AVR/ctors.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
define void @do_nothing() addrspace(1) #0 { define void @do_nothing() addrspace(1) #0 {
; CHECK-LABEL: do_nothing: ; CHECK-LABEL: do_nothing:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
ret void ret void
} }
; CHECK: .globl __do_global_ctors ; CHECK: .globl __do_global_ctors
@llvm.global_ctors = appending global [1 x { i32, void () addrspace(1)*, i8* }] [{ i32, void () addrspace(1)*, i8* } { i32 65535, void () addrspace(1)* @do_nothing, i8* null }] @llvm.global_ctors = appending global [1 x { i32, void () addrspace(1)*, i8* }] [{ i32, void () addrspace(1)*, i8* } { i32 65535, void () addrspace(1)* @do_nothing, i8* null }]
; CHECK: .globl __do_global_dtors ; CHECK: .globl __do_global_dtors
@llvm.global_dtors = appending global [1 x { i32, void () addrspace(1)*, i8* }] [{ i32, void () addrspace(1)*, i8* } { i32 65535, void () addrspace(1)* @do_nothing, i8* null }] @llvm.global_dtors = appending global [1 x { i32, void () addrspace(1)*, i8* }] [{ i32, void () addrspace(1)*, i8* } { i32 65535, void () addrspace(1)* @do_nothing, i8* null }]

llvm/test/CodeGen/AVR/ctpop.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
define i8 @count_population(i8) unnamed_addr { define i8 @count_population(i8) unnamed_addr {
entry-block: entry-block:
%1 = tail call i8 @llvm.ctpop.i8(i8 %0) %1 = tail call i8 @llvm.ctpop.i8(i8 %0)
ret i8 %1 ret i8 %1
} }
declare i8 @llvm.ctpop.i8(i8) declare i8 @llvm.ctpop.i8(i8)
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llvm/test/CodeGen/AVR/cttz.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
define i8 @count_trailing_zeros(i8) unnamed_addr { define i8 @count_trailing_zeros(i8) unnamed_addr {
entry-block: entry-block:
%1 = tail call i8 @llvm.cttz.i8(i8 %0) %1 = tail call i8 @llvm.cttz.i8(i8 %0)
ret i8 %1 ret i8 %1
} }
declare i8 @llvm.cttz.i8(i8) declare i8 @llvm.cttz.i8(i8)
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llvm/test/CodeGen/AVR/directmem.ll

; RUN: llc -mattr=sram,addsubiw < %s -march=avr | FileCheck %s ; RUN: llc -mattr=sram,addsubiw < %s -march=avr -verify-machineinstrs | FileCheck %s
@char = common global i8 0 @char = common global i8 0
@char.array = common global [3 x i8] zeroinitializer @char.array = common global [3 x i8] zeroinitializer
@char.static = internal global i8 0 @char.static = internal global i8 0
@int = common global i16 0 @int = common global i16 0
@int.array = common global [3 x i16] zeroinitializer @int.array = common global [3 x i16] zeroinitializer
@int.static = internal global i16 0 @int.static = internal global i16 0
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llvm/test/CodeGen/AVR/div.ll

; RUN: llc -mattr=mul,movw < %s -march=avr | FileCheck %s ; RUN: llc -mattr=mul,movw < %s -march=avr -verify-machineinstrs | FileCheck %s
; Unsigned 8-bit division ; Unsigned 8-bit division
define i8 @udiv8(i8 %a, i8 %b) { define i8 @udiv8(i8 %a, i8 %b) {
; CHECK-LABEL: div8: ; CHECK-LABEL: div8:
; CHECK: call __udivmodqi4 ; CHECK: call __udivmodqi4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%quotient = udiv i8 %a, %b %quotient = udiv i8 %a, %b
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llvm/test/CodeGen/AVR/dynalloca.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
declare void @foo(i16*, i16*, i8*) declare void @foo(i16*, i16*, i8*)
define void @test1(i16 %x) { define void @test1(i16 %x) {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; Frame setup, with frame pointer ; Frame setup, with frame pointer
; CHECK: in r28, 61 ; CHECK: in r28, 61
; CHECK: in r29, 62 ; CHECK: in r29, 62
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llvm/test/CodeGen/AVR/eor.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; Tests for the exclusive OR operation. ; Tests for the exclusive OR operation.
define i8 @eor8_reg_reg(i8 %a, i8 %b) { define i8 @eor8_reg_reg(i8 %a, i8 %b) {
; CHECK-LABEL: eor8_reg_reg: ; CHECK-LABEL: eor8_reg_reg:
; CHECK: eor r24, r22 ; CHECK: eor r24, r22
%result = xor i8 %a, %b %result = xor i8 %a, %b
ret i8 %result ret i8 %result
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llvm/test/CodeGen/AVR/expand-integer-failure.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; Causes an assertion error ; Causes an assertion error
; Assertion failed: (Lo.getValueType() == TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) && ; Assertion failed: (Lo.getValueType() == TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
; Hi.getValueType() == Lo.getValueType() && ; Hi.getValueType() == Lo.getValueType() &&
; "Invalid type for expanded integer"), ; "Invalid type for expanded integer"),
; function SetExpandedInteger ; function SetExpandedInteger
; file lib/CodeGen/SelectionDAG/LegalizeTypes.cpp ; file lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
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llvm/test/CodeGen/AVR/features/avr-tiny.ll

; RUN: llc -mattr=avrtiny -O0 < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avrtiny -O0 < %s -march=avr -verify-machineinstrs | FileCheck %s
define i16 @reg_copy16(i16, i16 %a) { define i16 @reg_copy16(i16, i16 %a) {
; CHECK-LABEL: reg_copy16 ; CHECK-LABEL: reg_copy16
; CHECK: mov r24, r22 ; CHECK: mov r24, r22
; CHECK: mov r25, r23 ; CHECK: mov r25, r23
ret i16 %a ret i16 %a
} }

llvm/test/CodeGen/AVR/features/avr25.ll

; RUN: llc -mattr=avr25 -O0 < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr25 -O0 < %s -march=avr -verify-machineinstrs | FileCheck %s
; On most cores, the 16-bit 'MOVW' instruction can be used ; On most cores, the 16-bit 'MOVW' instruction can be used
define i16 @reg_copy16(i16, i16 %a) { define i16 @reg_copy16(i16, i16 %a) {
; CHECK-LABEL: reg_copy16 ; CHECK-LABEL: reg_copy16
; CHECK: movw r24, r22 ; CHECK: movw r24, r22
ret i16 %a ret i16 %a
} }

llvm/test/CodeGen/AVR/features/xmega_io.ll

; RUN: llc -O0 < %s -march=avr -mcpu avrxmega1 | FileCheck %s -check-prefix=XMEGA ; RUN: llc -O0 < %s -march=avr -mcpu avrxmega1 -verify-machineinstrs | FileCheck %s -check-prefix=XMEGA
; RUN: llc -O0 < %s -march=avr -mcpu avrxmega2 | FileCheck %s -check-prefix=XMEGA ; RUN: llc -O0 < %s -march=avr -mcpu avrxmega2 -verify-machineinstrs | FileCheck %s -check-prefix=XMEGA
; RUN: llc -O0 < %s -march=avr -mcpu avrxmega3 | FileCheck %s -check-prefix=XMEGA ; RUN: llc -O0 < %s -march=avr -mcpu avrxmega3 -verify-machineinstrs | FileCheck %s -check-prefix=XMEGA
; RUN: llc -O0 < %s -march=avr -mcpu avrxmega4 | FileCheck %s -check-prefix=XMEGA ; RUN: llc -O0 < %s -march=avr -mcpu avrxmega4 -verify-machineinstrs | FileCheck %s -check-prefix=XMEGA
; RUN: llc -O0 < %s -march=avr -mcpu avrxmega5 | FileCheck %s -check-prefix=XMEGA ; RUN: llc -O0 < %s -march=avr -mcpu avrxmega5 -verify-machineinstrs | FileCheck %s -check-prefix=XMEGA
; RUN: llc -O0 < %s -march=avr -mcpu avrxmega6 | FileCheck %s -check-prefix=XMEGA ; RUN: llc -O0 < %s -march=avr -mcpu avrxmega6 -verify-machineinstrs | FileCheck %s -check-prefix=XMEGA
; RUN: llc -O0 < %s -march=avr -mcpu avrxmega7 | FileCheck %s -check-prefix=XMEGA ; RUN: llc -O0 < %s -march=avr -mcpu avrxmega7 -verify-machineinstrs | FileCheck %s -check-prefix=XMEGA
; RUN: llc -O0 < %s -march=avr -mcpu avr2 | FileCheck %s -check-prefix=AVR ; RUN: llc -O0 < %s -march=avr -mcpu avr2 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
; RUN: llc -O0 < %s -march=avr -mcpu avr25 | FileCheck %s -check-prefix=AVR ; RUN: llc -O0 < %s -march=avr -mcpu avr25 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
; RUN: llc -O0 < %s -march=avr -mcpu avr3 | FileCheck %s -check-prefix=AVR ; RUN: llc -O0 < %s -march=avr -mcpu avr3 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
; RUN: llc -O0 < %s -march=avr -mcpu avr31 | FileCheck %s -check-prefix=AVR ; RUN: llc -O0 < %s -march=avr -mcpu avr31 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
; RUN: llc -O0 < %s -march=avr -mcpu avr35 | FileCheck %s -check-prefix=AVR ; RUN: llc -O0 < %s -march=avr -mcpu avr35 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
; RUN: llc -O0 < %s -march=avr -mcpu avr4 | FileCheck %s -check-prefix=AVR ; RUN: llc -O0 < %s -march=avr -mcpu avr4 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
; RUN: llc -O0 < %s -march=avr -mcpu avr5 | FileCheck %s -check-prefix=AVR ; RUN: llc -O0 < %s -march=avr -mcpu avr5 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
; RUN: llc -O0 < %s -march=avr -mcpu avr51 | FileCheck %s -check-prefix=AVR ; RUN: llc -O0 < %s -march=avr -mcpu avr51 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
; RUN: llc -O0 < %s -march=avr -mcpu avr6 | FileCheck %s -check-prefix=AVR ; RUN: llc -O0 < %s -march=avr -mcpu avr6 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
define i8 @read8_low_io() { define i8 @read8_low_io() {
; CHECK-LABEL: read8_low_io ; CHECK-LABEL: read8_low_io
; XMEGA: in r24, 8 ; XMEGA: in r24, 8
; AVR: lds r24, 8 ; AVR: lds r24, 8
%1 = load i8, i8* inttoptr (i16 8 to i8*) %1 = load i8, i8* inttoptr (i16 8 to i8*)
ret i8 %1 ret i8 %1
} }
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llvm/test/CodeGen/AVR/frame.ll

; RUN: llc -mattr=mul < %s -march=avr | FileCheck %s ; RUN: llc -mattr=mul < %s -march=avr -verify-machineinstrs | FileCheck %s
declare float @dsin(float) declare float @dsin(float)
declare float @dcos(float) declare float @dcos(float)
declare float @dasin(float) declare float @dasin(float)
; Test prologue and epilogue insertion ; Test prologue and epilogue insertion
define float @f3(float %days) { define float @f3(float %days) {
entry: entry:
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llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll

; RUN: llc < %s -march=avr -mattr=avr6 | FileCheck %s ; RUN: llc < %s -march=avr -mattr=avr6 -verify-machineinstrs | FileCheck %s
%str_slice = type { i8*, i16 } %str_slice = type { i8*, i16 }
%Machine = type { i16, [0 x i8], i16, [0 x i8], [16 x i8], [0 x i8] } %Machine = type { i16, [0 x i8], i16, [0 x i8], [16 x i8], [0 x i8] }
; CHECK-LABEL: step ; CHECK-LABEL: step
define void @step(%Machine*) { define void @step(%Machine*) {
ret void ret void
} }
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llvm/test/CodeGen/AVR/hardware-mul.ll

; RUN: llc -mattr=mul,movw < %s -march=avr | FileCheck %s ; RUN: llc -mattr=mul,movw < %s -march=avr -verify-machineinstrs | FileCheck %s
; Tests lowering of multiplication to hardware instructions. ; Tests lowering of multiplication to hardware instructions.
define i8 @mult8(i8 %a, i8 %b) { define i8 @mult8(i8 %a, i8 %b) {
; CHECK-LABEL: mult8: ; CHECK-LABEL: mult8:
; CHECK: muls r22, r24 ; CHECK: muls r22, r24
; CHECK: clr r1 ; CHECK: clr r1
; CHECK: mov r24, r0 ; CHECK: mov r24, r0
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llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; This tests how LLVM handles IR which puts very high ; This tests how LLVM handles IR which puts very high
; presure on the PTRREGS class for the register allocator. ; presure on the PTRREGS class for the register allocator.
; ;
; This causes a problem because we only have one small register ; This causes a problem because we only have one small register
; class for loading and storing from pointers - 'PTRREGS'. ; class for loading and storing from pointers - 'PTRREGS'.
; One of these registers is also used for the frame pointer, meaning ; One of these registers is also used for the frame pointer, meaning
; that we only ever have two registers available for these operations. ; that we only ever have two registers available for these operations.
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llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll

; RUN: llc -mattr=lpm,lpmw < %s -march=avr | FileCheck %s ; RUN: llc -mattr=lpm,lpmw < %s -march=avr -verify-machineinstrs | FileCheck %s
@callbackPtr = common global void (i16) addrspace(1)* null, align 8 @callbackPtr = common global void (i16) addrspace(1)* null, align 8
@myValuePtr = common global i16* null, align 8 @myValuePtr = common global i16* null, align 8
@externalConstant = external global i16, align 2 @externalConstant = external global i16, align 2
declare void @externalFunction(i16 signext) declare void @externalFunction(i16 signext)
declare void @bar(i8 signext, void (i16)*, i16*) declare void @bar(i8 signext, void (i16)*, i16*)
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llvm/test/CodeGen/AVR/impossible-reg-to-reg-copy.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; Test case for an assertion error. ; Test case for an assertion error.
; ;
; Error: ; Error:
; ``` ; ```
; Impossible reg-to-reg copy ; Impossible reg-to-reg copy
; UNREACHABLE executed at lib/Target/AVR/AVRInstrInfo.cpp ; UNREACHABLE executed at lib/Target/AVR/AVRInstrInfo.cpp
; ``` ; ```
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llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll

; RUN: not llc < %s -march=avr -no-integrated-as 2>&1 | FileCheck %s ; RUN: not llc < %s -march=avr -no-integrated-as -verify-machineinstrs 2>&1 | FileCheck %s
define void @foo(i16 %a) { define void @foo(i16 %a) {
; CHECK: error: invalid operand in inline asm: 'jl ${0:l}' ; CHECK: error: invalid operand in inline asm: 'jl ${0:l}'
%i.addr = alloca i32, align 4 %i.addr = alloca i32, align 4
call void asm sideeffect "jl ${0:l}", "*m"(i32* elementtype(i32) %i.addr) call void asm sideeffect "jl ${0:l}", "*m"(i32* elementtype(i32) %i.addr)
ret void ret void
} }

llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll

; RUN: llc < %s -march=avr -mattr=movw -no-integrated-as | FileCheck %s ; RUN: llc < %s -march=avr -mattr=movw -no-integrated-as -verify-machineinstrs | FileCheck %s
; XFAIL: * ; XFAIL: *
; CHECK-LABEL: no_operands: ; CHECK-LABEL: no_operands:
define void @no_operands() { define void @no_operands() {
; CHECK: add {{r[0-9]+}}, {{r[0-9]+}} ; CHECK: add {{r[0-9]+}}, {{r[0-9]+}}
call void asm sideeffect "add r24, r22", ""() nounwind call void asm sideeffect "add r24, r22", ""() nounwind
ret void ret void
} }
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llvm/test/CodeGen/AVR/inline-asm/inline-asm2.ll

; RUN: llc < %s -march=avr -no-integrated-as | FileCheck %s ; RUN: llc < %s -march=avr -no-integrated-as -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: foo ; CHECK-LABEL: foo
define void @foo(i16 %a) { define void @foo(i16 %a) {
call void asm sideeffect "add $0, $0", "Z"(i16 %a) nounwind call void asm sideeffect "add $0, $0", "Z"(i16 %a) nounwind
ret void ret void
} }

llvm/test/CodeGen/AVR/inline-asm/inline-asm3.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=avr | FileCheck %s ; RUN: llc < %s -mtriple=avr -verify-machineinstrs | FileCheck %s
define void @add_r_i8(i8 signext %0, i8 signext %1) { define void @add_r_i8(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: add_r_i8: ; CHECK-LABEL: add_r_i8:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: mov r20, r22 ; CHECK-NEXT: mov r20, r22
; CHECK-NEXT: mov r22, r24 ; CHECK-NEXT: mov r22, r24
; CHECK-NEXT: ;APP ; CHECK-NEXT: ;APP
; CHECK-NEXT: mov r24, r22 ; CHECK-NEXT: mov r24, r22
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llvm/test/CodeGen/AVR/integration/blink.ll

; RUN: llc < %s -march=avr -mcpu=atmega328p | FileCheck %s ; RUN: llc < %s -march=avr -mcpu=atmega328p -verify-machineinstrs | FileCheck %s
; This test checks a basic 'blinking led' program. ; This test checks a basic 'blinking led' program.
; It is written for the ATmega328P ; It is written for the ATmega328P
; Derived from the following C program (with some cleanups): ; Derived from the following C program (with some cleanups):
; #include <avr/io.h> ; #include <avr/io.h>
; ;
; void setup_ddr() { ; void setup_ddr() {
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llvm/test/CodeGen/AVR/interrupts.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
@count = global i8 0 @count = global i8 0
define avr_intrcc void @interrupt_handler() { define avr_intrcc void @interrupt_handler() {
; CHECK-LABEL: interrupt_handler: ; CHECK-LABEL: interrupt_handler:
; CHECK: sei ; CHECK: sei
; CHECK-NEXT: push r0 ; CHECK-NEXT: push r0
; CHECK-NEXT: push r1 ; CHECK-NEXT: push r1
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llvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll

; RUN: not --crash llc -O0 < %s -march=avr 2>&1 | FileCheck %s ; RUN: not --crash llc -O0 < %s -march=avr -verify-machineinstrs 2>&1 | FileCheck %s
define void @foo() { define void @foo() {
entry: entry:
; CHECK: Invalid register name "r28". ; CHECK: Invalid register name "r28".
%val1 = call i8 @llvm.read_register.i8(metadata !0) %val1 = call i8 @llvm.read_register.i8(metadata !0)
ret void ret void
} }
declare i8 @llvm.read_register.i8(metadata) declare i8 @llvm.read_register.i8(metadata)
!0 = !{!"r28"} !0 = !{!"r28"}

llvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll

; RUN: llc -O0 < %s -march=avr | FileCheck %s ; RUN: llc -O0 < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: read_sp: ; CHECK-LABEL: read_sp:
; CHECK: in r24, 61 ; CHECK: in r24, 61
; CHECK: in r25, 62 ; CHECK: in r25, 62
define i16 @read_sp() { define i16 @read_sp() {
entry: entry:
%sp = call i16 @llvm.read_register.i16(metadata !0) %sp = call i16 @llvm.read_register.i16(metadata !0)
ret i16 %sp ret i16 %sp
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llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll

; RUN: llc -O0 < %s -march=avr | FileCheck %s ; RUN: llc -O0 < %s -march=avr -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: foo ; CHECK-LABEL: foo
define void @foo() { define void @foo() {
entry: entry:
br label %save br label %save
; CHECK-LABEL: save ; CHECK-LABEL: save
; CHECK: in [[SREG1:r[0-9]+]], 61 ; CHECK: in [[SREG1:r[0-9]+]], 61
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llvm/test/CodeGen/AVR/io.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
define i8 @read8() { define i8 @read8() {
; CHECK-LABEL: read8 ; CHECK-LABEL: read8
; CHECK: in r24, 8 ; CHECK: in r24, 8
%1 = load i8, i8* inttoptr (i16 40 to i8*) %1 = load i8, i8* inttoptr (i16 40 to i8*)
ret i8 %1 ret i8 %1
} }
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llvm/test/CodeGen/AVR/issue-cannot-select-bswap.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
declare i16 @llvm.bswap.i16(i16) declare i16 @llvm.bswap.i16(i16)
define i16 @foo(i16) { define i16 @foo(i16) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
entry-block: entry-block:
%1 = tail call i16 @llvm.bswap.i16(i16 %0) %1 = tail call i16 @llvm.bswap.i16(i16 %0)
ret i16 %1 ret i16 %1
} }

llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll

; RUN: llc < %s -march=avr -mcpu=atmega328 | FileCheck %s ; RUN: llc < %s -march=avr -mcpu=atmega328 -verify-machineinstrs | FileCheck %s
; This test case is designed to trigger a bug caused by the register ; This test case is designed to trigger a bug caused by the register
; allocator not handling the case where a target generates a load/store with ; allocator not handling the case where a target generates a load/store with
; a frame index that happens to be an earlyclobber instruction. ; a frame index that happens to be an earlyclobber instruction.
; ;
; It is taken from the translated LLVM IR of the Rust core library. ; It is taken from the translated LLVM IR of the Rust core library.
; ;
; The error message looked like ; The error message looked like
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llvm/test/CodeGen/AVR/jmp-long.ll

; RUN: llc -filetype=obj -march avr -mattr=jmpcall < %s | llvm-objdump -dr --mattr=jmpcall - | FileCheck %s ; RUN: llc -filetype=obj -march avr -mattr=jmpcall < %s -verify-machineinstrs \
; RUN: | llvm-objdump -dr --mattr=jmpcall - | FileCheck %s
; Test the fix in https://reviews.llvm.org/D78459. ; Test the fix in https://reviews.llvm.org/D78459.
; Long branches (that use jmp instead of rjmp) were broken: the jump was to a ; Long branches (that use jmp instead of rjmp) were broken: the jump was to a
; location 0x20000 away from where it should be. This test is a regression test ; location 0x20000 away from where it should be. This test is a regression test
; to make sure long branches are correct. ; to make sure long branches are correct.
declare void @bar() addrspace(1) declare void @bar() addrspace(1)
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llvm/test/CodeGen/AVR/large-return-size.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
define void @call_more_than_64_bits() { define void @call_more_than_64_bits() {
; CHECK-LABEL: call_more_than_64_bits ; CHECK-LABEL: call_more_than_64_bits
entry-block: entry-block:
%foo = call { i64, i1 } @more_than_64_bits() %foo = call { i64, i1 } @more_than_64_bits()
ret void ret void
} }
declare { i64, i1 } @more_than_64_bits() declare { i64, i1 } @more_than_64_bits()

llvm/test/CodeGen/AVR/lower-formal-args-struct-return.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; This test ensures that the backend can lower returns of struct values. ; This test ensures that the backend can lower returns of struct values.
; It does not check how these are lowered. ; It does not check how these are lowered.
; ;
; In the past, this code used to return an error ; In the past, this code used to return an error
; ;
; Assertion `InVals.size() == Ins.size() && "LowerFormalArguments didn't emit the correct number of values!"' failed. ; Assertion `InVals.size() == Ins.size() && "LowerFormalArguments didn't emit the correct number of values!"' failed.
; ;
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llvm/test/CodeGen/AVR/lower-formal-arguments-assertion.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
define void @foo(i1) { define void @foo(i1) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: ret ; CHECK: ret
ret void ret void
} }

llvm/test/CodeGen/AVR/neg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=avr | FileCheck %s ; RUN: llc < %s -mtriple=avr -verify-machineinstrs | FileCheck %s
define i8 @neg8(i8 %x) { define i8 @neg8(i8 %x) {
; CHECK-LABEL: neg8: ; CHECK-LABEL: neg8:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: neg r24 ; CHECK-NEXT: neg r24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sub = sub i8 0, %x %sub = sub i8 0, %x
ret i8 %sub ret i8 %sub
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llvm/test/CodeGen/AVR/no-print-operand-twice.ll

; RUN: llc -no-integrated-as -march=avr < %s | FileCheck %s ; RUN: llc -no-integrated-as -march=avr < %s -verify-machineinstrs | FileCheck %s
define void @test() { define void @test() {
entry: entry:
; CHECK: /* result: 68719476738 */ ; CHECK: /* result: 68719476738 */
tail call void asm sideeffect "/* result: ${0:c} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 ) tail call void asm sideeffect "/* result: ${0:c} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 )
ret void ret void
} }

llvm/test/CodeGen/AVR/or.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
define i8 @or8_reg_reg(i8 %a, i8 %b) { define i8 @or8_reg_reg(i8 %a, i8 %b) {
; CHECK-LABEL: or8_reg_reg: ; CHECK-LABEL: or8_reg_reg:
; CHECK: or r24, r22 ; CHECK: or r24, r22
%result = or i8 %a, %b %result = or i8 %a, %b
ret i8 %result ret i8 %result
} }
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llvm/test/CodeGen/AVR/pre-schedule.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
target triple = "avr-unknown-unknown" target triple = "avr-unknown-unknown"
; The case illustrate DAG schedular may pre-schedule the node has ; The case illustrate DAG schedular may pre-schedule the node has
; ADJCALLSTACKDOWN parent, so ADJCALLSTACKUP may hold CallResource too long ; ADJCALLSTACKDOWN parent, so ADJCALLSTACKUP may hold CallResource too long
; and make other calls can't be scheduled. If there's no other available node ; and make other calls can't be scheduled. If there's no other available node
; to schedule, the scheduler will try to rename the register by creating the ; to schedule, the scheduler will try to rename the register by creating the
; copy to avoid the conflict which will fail because CallResource is not a real ; copy to avoid the conflict which will fail because CallResource is not a real
; physical register. ; physical register.
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llvm/test/CodeGen/AVR/progmem-extended.ll

; RUN: llc < %s -march=avr -mattr=movw,lpmx | FileCheck %s ; RUN: llc < %s -march=avr -mattr=movw,lpmx -verify-machineinstrs | FileCheck %s
; XFAIL: * ; XFAIL: *
# Wide LPM is currently unimplemented in the pseudo expansion pass. # Wide LPM is currently unimplemented in the pseudo expansion pass.
; Tests the extended LPM instructions (LPMW, LPM Rd, Z+). ; Tests the extended LPM instructions (LPMW, LPM Rd, Z+).
define i8 @test8(i8 addrspace(1)* %p) { define i8 @test8(i8 addrspace(1)* %p) {
; CHECK-LABEL: test8: ; CHECK-LABEL: test8:
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llvm/test/CodeGen/AVR/progmem.ll

; RUN: llc < %s -march=avr -mattr=movw,lpm | FileCheck %s ; RUN: llc < %s -march=avr -mattr=movw,lpm -verify-machineinstrs | FileCheck %s
; XFAIL: * ; XFAIL: *
; Tests the standard LPM instruction ; Tests the standard LPM instruction
define i8 @test8(i8 addrspace(1)* %p) { define i8 @test8(i8 addrspace(1)* %p) {
; CHECK-LABEL: test8: ; CHECK-LABEL: test8:
; CHECK: movw r30, r24 ; CHECK: movw r30, r24
; CHECK: lpm r24, Z ; CHECK: lpm r24, Z
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llvm/test/CodeGen/AVR/rem.ll

; RUN: llc -mattr=mul,movw < %s -march=avr | FileCheck %s ; RUN: llc -mattr=mul,movw < %s -march=avr -verify-machineinstrs | FileCheck %s
; Unsigned 8-bit remision ; Unsigned 8-bit remision
define i8 @urem8(i8 %a, i8 %b) { define i8 @urem8(i8 %a, i8 %b) {
; CHECK-LABEL: rem8: ; CHECK-LABEL: rem8:
; CHECK: call __udivmodqi4 ; CHECK: call __udivmodqi4
; CHECK-NEXT: mov r24, r25 ; CHECK-NEXT: mov r24, r25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%rem = urem i8 %a, %b %rem = urem i8 %a, %b
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llvm/test/CodeGen/AVR/return.ll

; RUN: llc -mattr=avr6,sram < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr6,sram < %s -march=avr -verify-machineinstrs | FileCheck %s
;TODO: test returning byval structs ;TODO: test returning byval structs
; TODO: test naked functions ; TODO: test naked functions
define void @return_void() { define void @return_void() {
; CHECK: return_void:{{[a-zA-Z0-9 #@]*}} ; CHECK: return_void:{{[a-zA-Z0-9 #@]*}}
; CHECK-NEXT: {{.*}}: ; CHECK-NEXT: {{.*}}:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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llvm/test/CodeGen/AVR/rot.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; Bit rotation tests. ; Bit rotation tests.
; CHECK-LABEL: rol8: ; CHECK-LABEL: rol8:
define i8 @rol8(i8 %val, i8 %amt) { define i8 @rol8(i8 %val, i8 %amt) {
; CHECK: andi r22, 7 ; CHECK: andi r22, 7
; CHECK-NEXT: dec r22 ; CHECK-NEXT: dec r22
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llvm/test/CodeGen/AVR/runtime-trig.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; Checks that `sin` and `cos` nodes are expanded into calls to ; Checks that `sin` and `cos` nodes are expanded into calls to
; the `sin` and `cos` runtime library functions. ; the `sin` and `cos` runtime library functions.
; On AVR, the only floats supported are 32-bits, and so the ; On AVR, the only floats supported are 32-bits, and so the
; function names have no `f` or `d` suffix. ; function names have no `f` or `d` suffix.
declare float @llvm.sin.f32(float %x) declare float @llvm.sin.f32(float %x)
declare float @llvm.cos.f32(float %x) declare float @llvm.cos.f32(float %x)
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llvm/test/CodeGen/AVR/rust-avr-bug-112.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; The avr-rust bug can be found here: ; The avr-rust bug can be found here:
; https://github.com/avr-rust/rust/issues/112 ; https://github.com/avr-rust/rust/issues/112
; ;
; In this test, the codegen stage generates a FRMIDX ; In this test, the codegen stage generates a FRMIDX
; instruction. Later in the pipeline, the frame index ; instruction. Later in the pipeline, the frame index
; gets expanded into a 16-bit MOVWRdRr instruction. ; gets expanded into a 16-bit MOVWRdRr instruction.
; ;
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llvm/test/CodeGen/AVR/rust-avr-bug-37.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
%"fmt::Formatter" = type { i32, { i8*, void (i8*)** } } %"fmt::Formatter" = type { i32, { i8*, void (i8*)** } }
@str.1b = external constant [0 x i8] @str.1b = external constant [0 x i8]
define void @"TryFromIntError::Debug"(%"fmt::Formatter"* dereferenceable(32)) unnamed_addr #0 personality i32 (...) addrspace(1)* @rust_eh_personality { define void @"TryFromIntError::Debug"(%"fmt::Formatter"* dereferenceable(32)) unnamed_addr #0 personality i32 (...) addrspace(1)* @rust_eh_personality {
; CHECK-LABEL: "TryFromIntError::Debug" ; CHECK-LABEL: "TryFromIntError::Debug"
start: start:
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llvm/test/CodeGen/AVR/rust-avr-bug-95.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
%"fmt::Formatter.1.77.153.229.305.381.1673" = type { [0 x i8], i32, [0 x i8], i32, [0 x i8], i8, [0 x i8], %"option::Option<usize>.0.76.152.228.304.380.1672", [0 x i8], %"option::Option<usize>.0.76.152.228.304.380.1672", [0 x i8], { {}*, {}* }, [0 x i8], { i8*, i8* }, [0 x i8], { [0 x { i8*, i8* }]*, i16 }, [0 x i8] } %"fmt::Formatter.1.77.153.229.305.381.1673" = type { [0 x i8], i32, [0 x i8], i32, [0 x i8], i8, [0 x i8], %"option::Option<usize>.0.76.152.228.304.380.1672", [0 x i8], %"option::Option<usize>.0.76.152.228.304.380.1672", [0 x i8], { {}*, {}* }, [0 x i8], { i8*, i8* }, [0 x i8], { [0 x { i8*, i8* }]*, i16 }, [0 x i8] }
%"option::Option<usize>.0.76.152.228.304.380.1672" = type { [0 x i8], i8, [2 x i8] } %"option::Option<usize>.0.76.152.228.304.380.1672" = type { [0 x i8], i8, [2 x i8] }
@str.4S = external constant [5 x i8] @str.4S = external constant [5 x i8]
; Function Attrs: uwtable ; Function Attrs: uwtable
define void @"_ZN65_$LT$lib..str..Chars$LT$$u27$a$GT$$u20$as$u20$lib..fmt..Debug$GT$3fmt17h76a537e22649f739E"(%"fmt::Formatter.1.77.153.229.305.381.1673"* dereferenceable(27) %__arg_0) unnamed_addr #0 personality i32 (...) addrspace(1)* @rust_eh_personality { define void @"_ZN65_$LT$lib..str..Chars$LT$$u27$a$GT$$u20$as$u20$lib..fmt..Debug$GT$3fmt17h76a537e22649f739E"(%"fmt::Formatter.1.77.153.229.305.381.1673"* dereferenceable(27) %__arg_0) unnamed_addr #0 personality i32 (...) addrspace(1)* @rust_eh_personality {
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llvm/test/CodeGen/AVR/rust-avr-bug-99.ll

; RUN: llc < %s -march=avr -mcpu=avr5 | FileCheck %s ; RUN: llc < %s -march=avr -mcpu=avr5 -verify-machineinstrs | FileCheck %s
; The original reason for this failure is that the BranchFolderPass disables liveness ; The original reason for this failure is that the BranchFolderPass disables liveness
; tracking unless you override the trackLivenessAfterRegAlloc function and return true. ; tracking unless you override the trackLivenessAfterRegAlloc function and return true.
; This probably should be the default because all main targets do this (maybe some gpu targets don't). ; This probably should be the default because all main targets do this (maybe some gpu targets don't).
; More info can be found at https://github.com/avr-rust/rust/issues/99. ; More info can be found at https://github.com/avr-rust/rust/issues/99.
%struct.quux = type { [0 x i8], i64, [0 x i8], i64, [0 x i8], i64, [0 x i8], i64, [0 x i8] } %struct.quux = type { [0 x i8], i64, [0 x i8], i64, [0 x i8], i64, [0 x i8], i64, [0 x i8] }
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llvm/test/CodeGen/AVR/rust-trait-object.ll

; RUN: llc < %s -march=avr -filetype=asm | FileCheck %s -check-prefix=CHECK-ASM ; RUN: llc < %s -march=avr -filetype=asm -verify-machineinstrs \
; RUN: llc < %s -march=avr -filetype=obj | llvm-objdump -Dr - \ ; RUN: | FileCheck %s -check-prefix=CHECK-ASM
; RUN: | FileCheck %s -check-prefix=CHECK-OBJ ; RUN: llc < %s -march=avr -filetype=obj -verify-machineinstrs \
; RUN: | llvm-objdump -Dr - | FileCheck %s -check-prefix=CHECK-OBJ
; Somewhat pruned test case from rustc using trait objects ; Somewhat pruned test case from rustc using trait objects
%TraitObjectA = type {} %TraitObjectA = type {}
; CHECK-ASM-LABEL: vtable.0: ; CHECK-ASM-LABEL: vtable.0:
; CHECK-ASM-NEXT: .short pm(drop_in_place2) ; CHECK-ASM-NEXT: .short pm(drop_in_place2)
; CHECK-ASM-NEXT: .short 0 ; CHECK-ASM-NEXT: .short 0
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llvm/test/CodeGen/AVR/sections.ll

; RUN: llc < %s -march=avr --mcpu=atxmega384d3 \ ; RUN: llc < %s -march=avr --mcpu=atxmega384d3 -verify-machineinstrs \
; RUN: | FileCheck --check-prefixes=CHECK,NOSECTIONS %s ; RUN: | FileCheck --check-prefixes=CHECK,NOSECTIONS %s
; RUN: llc -function-sections -data-sections < %s -march=avr --mcpu=atxmega384d3 \ ; RUN: llc -function-sections -data-sections < %s -march=avr --mcpu=atxmega384d3 -verify-machineinstrs \
; RUN: | FileCheck --check-prefixes=CHECK,SECTIONS %s ; RUN: | FileCheck --check-prefixes=CHECK,SECTIONS %s
; RUN: not llc -function-sections -data-sections < %s -march=avr --mcpu=at90s8515 2>&1 \ ; RUN: not llc -function-sections -data-sections < %s -march=avr --mcpu=at90s8515 -verify-machineinstrs 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-8515 %s ; RUN: | FileCheck --check-prefixes=CHECK-8515 %s
; RUN: not llc -function-sections -data-sections < %s -march=avr --mcpu=attiny40 2>&1 \ ; RUN: not llc -function-sections -data-sections < %s -march=avr --mcpu=attiny40 -verify-machineinstrs 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-tiny40 %s ; RUN: | FileCheck --check-prefixes=CHECK-tiny40 %s
; Test that functions (in address space 1) are not considered .progmem data. ; Test that functions (in address space 1) are not considered .progmem data.
; CHECK: .text ; CHECK: .text
; SECTIONS: .text.somefunc,"ax",@progbits ; SECTIONS: .text.somefunc,"ax",@progbits
; CHECK-LABEL: somefunc: ; CHECK-LABEL: somefunc:
define void @somefunc() addrspace(1) { define void @somefunc() addrspace(1) {
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llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll

; RUN: llc -march=avr -print-after=finalize-isel -cgp-freq-ratio-to-skip-merge=10 < %s 2>&1 | FileCheck %s ; RUN: llc -march=avr -print-after=finalize-isel -cgp-freq-ratio-to-skip-merge=10 < %s \
; RUN: 2>&1 -verify-machineinstrs | FileCheck %s
; Because `switch` seems to trigger Machine Basic Blocks to be ordered ; Because `switch` seems to trigger Machine Basic Blocks to be ordered
; in a different order than they were constructed, this exposes an ; in a different order than they were constructed, this exposes an
; error in the `expand-isel-pseudos` pass. Specifically, it thought we ; error in the `expand-isel-pseudos` pass. Specifically, it thought we
; could always fallthrough to a newly-constructed MBB. However, ; could always fallthrough to a newly-constructed MBB. However,
; there's no guarantee that either of the constructed MBBs need to ; there's no guarantee that either of the constructed MBBs need to
; occur immediately after the currently-focused one! ; occur immediately after the currently-focused one!
; ;
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llvm/test/CodeGen/AVR/sext.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; sext R17:R16, R13 ; sext R17:R16, R13
; mov r16, r13 ; mov r16, r13
; mov r17, r13 ; mov r17, r13
; lsl r17 ; lsl r17
; sbc r17, r17 ; sbc r17, r17
define i16 @sext1(i8 %x, i8 %y) { define i16 @sext1(i8 %x, i8 %y) {
; CHECK-LABEL: sext1: ; CHECK-LABEL: sext1:
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llvm/test/CodeGen/AVR/shift-expand.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -avr-shift-expand -S %s -o - | FileCheck %s ; RUN: opt -avr-shift-expand -S %s -verify-machineinstrs -o - | FileCheck %s
; The avr-shift-expand pass expands large shifts with a non-constant shift ; The avr-shift-expand pass expands large shifts with a non-constant shift
; amount to a loop. These loops avoid generating a (non-existing) builtin such ; amount to a loop. These loops avoid generating a (non-existing) builtin such
; as __ashlsi3. ; as __ashlsi3.
target datalayout = "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8" target datalayout = "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8"
target triple = "avr" target triple = "avr"
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llvm/test/CodeGen/AVR/sign-extension.ll

; RUN: llc -march=avr < %s | FileCheck %s ; RUN: llc -march=avr -verify-machineinstrs < %s | FileCheck %s
define i8 @sign_extended_1_to_8(i1) { define i8 @sign_extended_1_to_8(i1) {
; CHECK-LABEL: sign_extended_1_to_8 ; CHECK-LABEL: sign_extended_1_to_8
entry-block: entry-block:
%1 = sext i1 %0 to i8 %1 = sext i1 %0 to i8
ret i8 %1 ret i8 %1
} }
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llvm/test/CodeGen/AVR/smul-with-overflow.ll

; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
define i1 @signed_multiplication_did_overflow(i8, i8) unnamed_addr { define i1 @signed_multiplication_did_overflow(i8, i8) unnamed_addr {
; CHECK-LABEL: signed_multiplication_did_overflow: ; CHECK-LABEL: signed_multiplication_did_overflow:
entry-block: entry-block:
%2 = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %0, i8 %1) %2 = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %0, i8 %1)
%3 = extractvalue { i8, i1 } %2, 1 %3 = extractvalue { i8, i1 } %2, 1
ret i1 %3 ret i1 %3
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llvm/test/CodeGen/AVR/software-mul.ll

; RUN: llc -mattr=avr6,-mul < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr6,-mul < %s -march=avr -verify-machineinstrs | FileCheck %s
; RUN: llc -mcpu=attiny85 < %s -march=avr | FileCheck %s ; RUN: llc -mcpu=attiny85 < %s -march=avr -verify-machineinstrs | FileCheck %s
; RUN: llc -mcpu=ata5272 < %s -march=avr | FileCheck %s ; RUN: llc -mcpu=ata5272 < %s -march=avr -verify-machineinstrs | FileCheck %s
; RUN: llc -mcpu=attiny861a < %s -march=avr | FileCheck %s ; RUN: llc -mcpu=attiny861a < %s -march=avr -verify-machineinstrs | FileCheck %s
; RUN: llc -mcpu=at90usb82 < %s -march=avr | FileCheck %s ; RUN: llc -mcpu=at90usb82 < %s -march=avr -verify-machineinstrs | FileCheck %s
; Tests lowering of multiplication to compiler support routines. ; Tests lowering of multiplication to compiler support routines.
; CHECK-LABEL: mul8: ; CHECK-LABEL: mul8:
define i8 @mul8(i8 %a, i8 %b) { define i8 @mul8(i8 %a, i8 %b) {
; CHECK: mov r25, r24 ; CHECK: mov r25, r24
; CHECK: mov r24, r22 ; CHECK: mov r24, r22
; CHECK: mov r22, r25 ; CHECK: mov r22, r25
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llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll

; RUN: llc -O0 < %s -march=avr | FileCheck %s ; RUN: llc -O0 < %s -march=avr -verify-machineinstrs | FileCheck %s
define i32 @std_ldd_overflow() { define i32 @std_ldd_overflow() {
%src = alloca [4 x i8] %src = alloca [4 x i8]
%dst = alloca [4 x i8] %dst = alloca [4 x i8]
%buf = alloca [28 x i16] %buf = alloca [28 x i16]
%1 = bitcast [4 x i8]* %src to i32* %1 = bitcast [4 x i8]* %src to i32*
store i32 0, i32 *%1 store i32 0, i32 *%1
%2 = bitcast [4 x i8]* %dst to i8* %2 = bitcast [4 x i8]* %dst to i8*
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llvm/test/CodeGen/AVR/store-undef.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; This test checks that we can successfully lower a store ; This test checks that we can successfully lower a store
; to an undefined pointer. ; to an undefined pointer.
; CHECK-LABEL: foo ; CHECK-LABEL: foo
define void @foo() { define void @foo() {
; CHECK: st [[PTRREG:X|Y|Z]], r1 ; CHECK: st [[PTRREG:X|Y|Z]], r1
store i8 0, i8* undef, align 4 store i8 0, i8* undef, align 4
ret void ret void
} }

llvm/test/CodeGen/AVR/store.ll

; RUN: llc -mattr=avr6,sram < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr6,sram < %s -march=avr -verify-machineinstrs | FileCheck %s
define void @store8(i8* %x, i8 %y) { define void @store8(i8* %x, i8 %y) {
; CHECK-LABEL: store8: ; CHECK-LABEL: store8:
; CHECK: st {{[XYZ]}}, r22 ; CHECK: st {{[XYZ]}}, r22
store i8 %y, i8* %x store i8 %y, i8* %x
ret void ret void
} }
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llvm/test/CodeGen/AVR/struct.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=avr < %s | FileCheck %s --check-prefix=CHECKA ; RUN: llc -mtriple=avr < %s -verify-machineinstrs \
; RUN: llc -mtriple=avr -mattr=+movw < %s | FileCheck %s --check-prefix=CHECKB ; RUN: | FileCheck %s --check-prefix=CHECKA
; RUN: llc -mtriple=avr -mattr=+movw < %s -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefix=CHECKB
%struct.s10 = type { i16, i16, i16, i16, i16 } %struct.s10 = type { i16, i16, i16, i16, i16 }
%struct.s06 = type { i16, i16, i16 } %struct.s06 = type { i16, i16, i16 }
%struct.s04 = type { i16, i16 } %struct.s04 = type { i16, i16 }
define void @foo10(%struct.s10* sret(%struct.s10) %0, i16 %1, i16 %2, i16 %3) addrspace(1) { define void @foo10(%struct.s10* sret(%struct.s10) %0, i16 %1, i16 %2, i16 %3) addrspace(1) {
; CHECKA-LABEL: foo10: ; CHECKA-LABEL: foo10:
; CHECKA: ; %bb.0: ; CHECKA: ; %bb.0:
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llvm/test/CodeGen/AVR/sub.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
define i8 @sub8_reg_reg(i8 %a, i8 %b) { define i8 @sub8_reg_reg(i8 %a, i8 %b) {
; CHECK-LABEL: sub8_reg_reg: ; CHECK-LABEL: sub8_reg_reg:
; CHECK: sub r24, r22 ; CHECK: sub r24, r22
%result = sub i8 %a, %b %result = sub i8 %a, %b
ret i8 %result ret i8 %result
} }
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llvm/test/CodeGen/AVR/trunc.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
define i8 @trunc8_loreg(i16 %x, i16 %y) { define i8 @trunc8_loreg(i16 %x, i16 %y) {
; CHECK-LABEL: trunc8_loreg: ; CHECK-LABEL: trunc8_loreg:
; CHECK: mov r24, r22 ; CHECK: mov r24, r22
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%conv = trunc i16 %y to i8 %conv = trunc i16 %y to i8
ret i8 %conv ret i8 %conv
} }
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llvm/test/CodeGen/AVR/umul-with-overflow.ll

; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
define i1 @unsigned_multiplication_did_overflow(i8, i8) unnamed_addr { define i1 @unsigned_multiplication_did_overflow(i8, i8) unnamed_addr {
; CHECK-LABEL: unsigned_multiplication_did_overflow: ; CHECK-LABEL: unsigned_multiplication_did_overflow:
entry-block: entry-block:
%2 = tail call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %0, i8 %1) %2 = tail call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %0, i8 %1)
%3 = extractvalue { i8, i1 } %2, 1 %3 = extractvalue { i8, i1 } %2, 1
ret i1 %3 ret i1 %3
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llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll

; RUN: llc -O1 < %s -march=avr | FileCheck %s ; RUN: llc -O1 < %s -march=avr -verify-machineinstrs | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.9" target triple = "x86_64-apple-macosx10.9"
%Vs6UInt16 = type <{ i16 }> %Vs6UInt16 = type <{ i16 }>
%Sb = type <{ i1 }> %Sb = type <{ i1 }>
define hidden void @setServoAngle(i16) { define hidden void @setServoAngle(i16) {
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llvm/test/CodeGen/AVR/unaligned-atomic-loads.ll

; RUN: llc -mattr=addsubiw < %s -march=avr | FileCheck %s ; RUN: llc -mattr=addsubiw < %s -march=avr -verify-machineinstrs | FileCheck %s
; This verifies that the middle end can handle an unaligned atomic load. ; This verifies that the middle end can handle an unaligned atomic load.
; ;
; In the past, an assertion inside the SelectionDAGBuilder would always ; In the past, an assertion inside the SelectionDAGBuilder would always
; hit an assertion for unaligned loads and stores. ; hit an assertion for unaligned loads and stores.
%AtomicI16 = type { %CellI16, [0 x i8] } %AtomicI16 = type { %CellI16, [0 x i8] }
%CellI16 = type { i16, [0 x i8] } %CellI16 = type { i16, [0 x i8] }
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llvm/test/CodeGen/AVR/varargs.ll

; RUN: llc -mattr=sram,movw,addsubiw < %s -march=avr | FileCheck %s ; RUN: llc -mattr=sram,movw,addsubiw < %s -march=avr -verify-machineinstrs | FileCheck %s
declare void @llvm.va_start(i8*) declare void @llvm.va_start(i8*)
declare i16 @vsprintf(i8* nocapture, i8* nocapture, i8*) declare i16 @vsprintf(i8* nocapture, i8* nocapture, i8*)
declare void @llvm.va_end(i8*) declare void @llvm.va_end(i8*)
define i16 @varargs1(i8* nocapture %x, ...) { define i16 @varargs1(i8* nocapture %x, ...) {
; CHECK-LABEL: varargs1: ; CHECK-LABEL: varargs1:
; CHECK: movw r20, r28 ; CHECK: movw r20, r28
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llvm/test/CodeGen/AVR/xor.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
define i8 @xor8_reg_reg(i8 %a, i8 %b) { define i8 @xor8_reg_reg(i8 %a, i8 %b) {
; CHECK-LABEL: xor8_reg_reg: ; CHECK-LABEL: xor8_reg_reg:
; CHECK: eor r24, r22 ; CHECK: eor r24, r22
%result = xor i8 %a, %b %result = xor i8 %a, %b
ret i8 %result ret i8 %result
} }
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llvm/test/CodeGen/AVR/zext.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
; zext R25:R24, R24 ; zext R25:R24, R24
; eor R25, R25 ; eor R25, R25
define i16 @zext1(i8 %x) { define i16 @zext1(i8 %x) {
; CHECK-LABEL: zext1: ; CHECK-LABEL: zext1:
; CHECK: clr r25 ; CHECK: clr r25
%1 = zext i8 %x to i16 %1 = zext i8 %x to i16
ret i16 %1 ret i16 %1
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