[PowerPC] Set the special DSCR with a compiler option.

[stefanp]

Summary

Add a compiler option and the instructions required to set the
special Data Stream Control Register (DSCR). The special register will
not be set by default.

Original patch by: Muhammad Usman

[stefanp]

Cleaned up some of the formatting issues.

[lei]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

3081

//Disable these alias on AIX since they are not supported.

[nemanjai]

LGTM.

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

438

It likely doesn't matter, but we should get rid of this kill.

[stefanp]

Addressed comments and rebased patch to top of main.

llvm/lib/Target/PowerPC/P10InstrResources.td

 // Single crack instructions
 // 6 Cycles Load operations, 2 input operands
 def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY, P10LD_Read, P10LD_Read],
       (instrs
     LBZCIX,
     LDCIX,
     LHZCIX,
     LWZCIX,
-    MTSPR, MTSPR8, MTSR, MTVRSAVE, MTVRSAVEv
+    MTSPR, MTSPR8, MTSR, MTUDSCR, MTVRSAVE, MTVRSAVEv
 )>;
 
 // Expand instructions
 // 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load operations, 1 input operands
 def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10LD_Read],
       (instrs
     LMW
 )>;
def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_SX_3C],
     LXVP,
     LXVPX
 )>;
 
 // Single crack instructions
 // 13 Cycles Unknown operations, 1 input operands
 def : InstRW<[P10W_MFL_13C, P10W_DISP_EVEN, P10W_DISP_ANY],
       (instrs
-    MFSPR, MFSPR8, MFSR, MFTB8, MFVRSAVE, MFVRSAVEv
+    MFSPR, MFSPR8, MFSR, MFTB8, MFUDSCR, MFVRSAVE, MFVRSAVEv
 )>;
 
 // 10 Cycles SIMD Matrix Multiply Engine operations, 0 input operands
 def : InstRW<[P10W_MM_10C, P10W_DISP_ANY],
       (instrs
     XXSETACCZ
 )>;
 

llvm/lib/Target/PowerPC/P9InstrResources.td

 // dispatches.
 def : InstRW<[P9_DIV_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_EVEN_1C],
       (instrs
     (instregex "M(T|F)VRSAVE(v)?$"),
     (instregex "M(T|F)PMR$"),
     (instregex "M(T|F)TB(8)?$"),
     (instregex "MF(SPR|CTR|LR)(8)?$"),
     (instregex "M(T|F)MSR(D)?$"),
+    (instregex "M(T|F)(U)?DSCR$"),
     (instregex "MTSPR(8)?$")
 )>;
 
 // 16 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
 // superslice. That includes both exec pipelines (EXECO, EXECE) and two
 // dispatches.
 def : InstRW<[P9_DIV_16C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
       (instrs

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 }
 let Uses = [LR] in {
 def MFLR  : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
                           "mflr $rT", IIC_SprMFSPR>,
             PPC970_DGroup_First, PPC970_Unit_FXU;
 }
 }
 
+let hasSideEffects = 1 in {
+  def MTUDSCR : XFXForm_7_ext<31, 467, 3, (outs), (ins gprc:$rX),
+                              "mtspr 3, $rX", IIC_SprMTSPR>,
+                PPC970_DGroup_Single, PPC970_Unit_FXU;
+  def MFUDSCR : XFXForm_1_ext<31, 339, 3, (outs gprc:$rX), (ins),
+                              "mfspr $rX, 3", IIC_SprMFSPR>,
+                PPC970_DGroup_First, PPC970_Unit_FXU;
+}
+
+// Disable these alias on AIX since they are not supported.
+let Predicates = [ModernAs] in {
+// Aliases for moving to/from dscr to mtspr/mfspr
+def : InstAlias<"mtudscr $Rx", (MTUDSCR gprc:$Rx)>;
+def : InstAlias<"mfudscr $Rx", (MFUDSCR gprc:$Rx)>;
+}
+
 let isCodeGenOnly = 1 in {
   // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
   // like a GPR on the PPC970.  As such, copies in and out have the same
   // performance characteristics as an OR instruction.
   def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
                                "mtspr 256, $rS", IIC_IntGeneral>,
                  PPC970_DGroup_Single, PPC970_Unit_FXU;
   def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

 #include "PPCSubtarget.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/LivePhysRegs.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "ppc-pre-emit-peephole"
 

 static cl::opt<bool>
 EnablePCRelLinkerOpt("ppc-pcrel-linker-opt", cl::Hidden, cl::init(true),
                      cl::desc("enable PC Relative linker optimization"));
 
 static cl::opt<bool>
 RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true),
                    cl::desc("Run pre-emit peephole optimizations."));
 
+static cl::opt<uint64_t>
+DSCRValue("ppc-set-dscr", cl::Hidden,
+          cl::desc("Set the Data Stream Control Register."));
+
 namespace {
 
 static bool hasPCRelativeForm(MachineInstr &Use) {
   switch (Use.getOpcode()) {
   default:
     return false;
   case PPC::LBZ:
   case PPC::LBZ8:
bool removeAccPrimeUnprime(MachineBasicBlock &MBB) {
 
       for (MachineInstr *MI : InstrsToErase)
         MI->eraseFromParent();
       NumRemovedInPreEmit += InstrsToErase.size();
       return !InstrsToErase.empty();
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override {
+      // If the user wants to set the DSCR using command-line options,
+      // load in the specified value at the start of main.
+      if (DSCRValue.getNumOccurrences() > 0 && MF.getName().equals("main") &&
+          MF.getFunction().hasExternalLinkage()) {
+        DSCRValue = (uint32_t)(DSCRValue & 0x01FFFFFF); // 25-bit DSCR mask
+        RegScavenger RS;
+        MachineBasicBlock &MBB = MF.front();
+        // Find an unused GPR according to register liveness
+        RS.enterBasicBlock(MBB);
+        unsigned InDSCR = RS.FindUnusedReg(&PPC::GPRCRegClass);
+        if (InDSCR) {
+          const PPCInstrInfo *TII =
+              MF.getSubtarget<PPCSubtarget>().getInstrInfo();
+          DebugLoc dl;
+          MachineBasicBlock::iterator IP = MBB.begin(); // Insert Point
+          // Copy the 32-bit DSCRValue integer into the GPR InDSCR using LIS and
+          // ORI, then move to DSCR. If the requested DSCR value is contained
+          // in a 16-bit signed number, we can emit a single `LI`, but the
+          // impact of saving one instruction in one function does not warrant
+          // any additional complexity in the logic here.
+          BuildMI(MBB, IP, dl, TII->get(PPC::LIS), InDSCR)
+              .addImm(DSCRValue >> 16);
+          BuildMI(MBB, IP, dl, TII->get(PPC::ORI), InDSCR)
+              .addReg(InDSCR)
+              .addImm(DSCRValue & 0xFFFF);
+          BuildMI(MBB, IP, dl, TII->get(PPC::MTUDSCR))
+              .addReg(InDSCR, RegState::Kill);
+        } else
+          errs() << "Warning: Ran out of registers - Unable to set DSCR as "
+                    "requested";
+      }
+
       if (skipFunction(MF.getFunction()) || !RunPreEmitPeephole) {
         // Remove UNENCODED_NOP even when this pass is disabled.
         // This needs to be done unconditionally so we don't emit zeros
         // in the instruction stream.
         SmallVector<MachineInstr *, 4> InstrsToErase;
         for (MachineBasicBlock &MBB : MF)
           for (MachineInstr &MI : MBB)
             if (MI.getOpcode() == PPC::UNENCODED_NOP)

llvm/test/CodeGen/PowerPC/dscr-set.ll

+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr9 \
+; RUN:     | FileCheck %s -check-prefix=DEFAULT
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr9 \
+; RUN:     -ppc-set-dscr=0xFFFFFFFFFFFFFFFF | FileCheck %s -check-prefix=UPPER
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr9 \
+; RUN:     -ppc-set-dscr=0x01C4 | FileCheck %s -check-prefix=LOWER
+
+define i32 @main() {
+
+; CHECK:       # %bb.0:
+
+; DEFAULT-NOT:     mtudscr
+
+; UPPER:     lis [[inReg:[0-9]+]], 511
+; UPPER-NEXT:    ori [[inReg]], [[inReg]], 65535
+; UPPER-NEXT:    mtudscr [[inReg]]
+
+; LOWER:     lis [[inReg:[0-9]+]], 0
+; LOWER-NEXT:    ori [[inReg]], [[inReg]], 452
+; LOWER-NEXT:    mtudscr [[inReg]]
+
+       ret i32 1
+}

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt

 0x7c 0x62 0x26 0xf5
 
 # CHECK: mtspr 600, 2                    
 0x7c 0x58 0x93 0xa6
 
 # CHECK: mfspr 2, 600                    
 0x7c 0x58 0x92 0xa6
 
+# CHECK: mtudscr 2
+0x7c 0x43 0x03 0xa6
+
+# CHECK: mfudscr 2
+0x7c 0x43 0x02 0xa6
+
 # CHECK: mtcrf 123, 2                    
 0x7c 0x47 0xb1 0x20
 
 # CHECK: mfcr 2                          
 0x7c 0x40 0x00 0x26
 
 # CHECK: mtocrf 16, 2                    
 0x7c 0x51 0x01 0x20

llvm/test/MC/PowerPC/ppc64-encoding-ext.s

 # CHECK-LE: mfudscr 2                       # encoding: [0xa6,0x02,0x43,0x7c]
             mfudscr 2
 # CHECK-BE: mfrtcu 2                        # encoding: [0x7c,0x44,0x02,0xa6]
 # CHECK-LE: mfrtcu 2                        # encoding: [0xa6,0x02,0x44,0x7c]
             mfrtcu 2
 # CHECK-BE: mfrtcl 2                        # encoding: [0x7c,0x45,0x02,0xa6]
 # CHECK-LE: mfrtcl 2                        # encoding: [0xa6,0x02,0x45,0x7c]
             mfrtcl 2
+# CHECK-BE: mtudscr 2                       # encoding: [0x7c,0x43,0x03,0xa6]
+# CHECK-LE: mtudscr 2                       # encoding: [0xa6,0x03,0x43,0x7c]
+            mtudscr 2
+# CHECK-BE: mfudscr 2                       # encoding: [0x7c,0x43,0x02,0xa6]
+# CHECK-LE: mfudscr 2                       # encoding: [0xa6,0x02,0x43,0x7c]
+            mfudscr 2
 # CHECK-BE: mtdscr 2                        # encoding: [0x7c,0x51,0x03,0xa6]
 # CHECK-LE: mtdscr 2                        # encoding: [0xa6,0x03,0x51,0x7c]
             mtdscr 2
 # CHECK-BE: mfdscr 2                        # encoding: [0x7c,0x51,0x02,0xa6]
 # CHECK-LE: mfdscr 2                        # encoding: [0xa6,0x02,0x51,0x7c]
             mfdscr 2
 # CHECK-BE: mtdsisr 2                       # encoding: [0x7c,0x52,0x03,0xa6]
 # CHECK-LE: mtdsisr 2                       # encoding: [0xa6,0x03,0x52,0x7c]