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Differential D116171

[OpenMP] Fix incorrect type when casting from uintptr
ClosedPublic

Authored by nikic on Dec 22 2021, 8:27 AM.

Details

Reviewers
jdoerfert
ABataev
Commits
rG1201a0f3955b: [OpenMP] Fix incorrect type when casting from uintptr
Summary

MakeNaturalAlignAddrLValue() expects the pointee type, but the pointer type was passed. As a result, the natural alignment of the pointer (usually 8) was always used in place of the natural alignment of the value type.

Diff Detail

Event Timeline

nikic created this revision.Dec 22 2021, 8:27 AM
Herald added subscribers: asavonic, guansong, yaxunl. · View Herald TranscriptDec 22 2021, 8:27 AM
nikic requested review of this revision.Dec 22 2021, 8:27 AM
Herald added a reviewer: jdoerfert. · View Herald TranscriptDec 22 2021, 8:27 AM
Herald added a subscriber: sstefan1. · View Herald Transcript
nikic added a reviewer: ABataev.Dec 22 2021, 8:27 AM
ABataev accepted this revision.Dec 22 2021, 8:52 AM

LG

This revision is now accepted and ready to land.Dec 22 2021, 8:52 AM
Harbormaster completed remote builds in B140400: Diff 395878.Dec 22 2021, 9:08 AM
This revision was landed with ongoing or failed builds.Dec 22 2021, 11:59 PM
Closed by commit rG1201a0f3955b: [OpenMP] Fix incorrect type when casting from uintptr (authored by nikic). · Explain Why
This revision was automatically updated to reflect the committed changes.
nikic added a commit: rG1201a0f3955b: [OpenMP] Fix incorrect type when casting from uintptr.
Herald added a project: Restricted Project. · View Herald TranscriptDec 22 2021, 11:59 PM
Herald added a subscriber: cfe-commits. · View Herald Transcript

Revision Contents

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lib/
CodeGen/
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utils/
update_cc_test_checks/
Inputs/
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Diff 395986

clang/lib/CodeGen/CGStmtOpenMP.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 372 Lines • ▼ Show 20 Linesstatic Address castValueFromUintptr(CodeGenFunction &CGF, SourceLocation Loc,
QualType DstType, StringRef Name, QualType DstType, StringRef Name,
LValue AddrLV) { LValue AddrLV) {
ASTContext &Ctx = CGF.getContext(); ASTContext &Ctx = CGF.getContext();
llvm::Value *CastedPtr = CGF.EmitScalarConversion( llvm::Value *CastedPtr = CGF.EmitScalarConversion(
AddrLV.getAddress(CGF).getPointer(), Ctx.getUIntPtrType(), AddrLV.getAddress(CGF).getPointer(), Ctx.getUIntPtrType(),
Ctx.getPointerType(DstType), Loc); Ctx.getPointerType(DstType), Loc);
Address TmpAddr = Address TmpAddr =
CGF.MakeNaturalAlignAddrLValue(CastedPtr, Ctx.getPointerType(DstType)) CGF.MakeNaturalAlignAddrLValue(CastedPtr, DstType).getAddress(CGF);
.getAddress(CGF);
return TmpAddr; return TmpAddr;
} }
static QualType getCanonicalParamType(ASTContext &C, QualType T) { static QualType getCanonicalParamType(ASTContext &C, QualType T) {
if (T->isLValueReferenceType()) if (T->isLValueReferenceType())
return C.getLValueReferenceType( return C.getLValueReferenceType(
getCanonicalParamType(C, T.getNonReferenceType()), getCanonicalParamType(C, T.getNonReferenceType()),
/*SpelledAsLValue=*/false); /*SpelledAsLValue=*/false);
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clang/test/OpenMP/debug-info-complex-byval.cpp

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// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META36:![0-9]+]], metadata !DIExpression()), !dbg [[DBG35]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META36:![0-9]+]], metadata !DIExpression()), !dbg [[DBG35]]
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i64* [[B_ADDR]], metadata [[META37:![0-9]+]], metadata !DIExpression()), !dbg [[DBG35]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i64* [[B_ADDR]], metadata [[META37:![0-9]+]], metadata !DIExpression()), !dbg [[DBG35]]
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to { float, float }*, !dbg [[DBG38:![0-9]+]] // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to { float, float }*, !dbg [[DBG38:![0-9]+]]
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG38]] // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG38]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG38]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG38]]
// CHECK1-NEXT: [[TMP2:%.*]] = bitcast { float, float }* [[CONV]] to <2 x float>*, !dbg [[DBG38]] // CHECK1-NEXT: [[TMP2:%.*]] = bitcast { float, float }* [[CONV]] to <2 x float>*, !dbg [[DBG38]]
// CHECK1-NEXT: [[TMP3:%.*]] = load <2 x float>, <2 x float>* [[TMP2]], align 8, !dbg [[DBG38]] // CHECK1-NEXT: [[TMP3:%.*]] = load <2 x float>, <2 x float>* [[TMP2]], align 4, !dbg [[DBG38]]
// CHECK1-NEXT: call void @.omp_outlined._debug__(i32* [[TMP0]], i32* [[TMP1]], <2 x float> [[TMP3]]) #[[ATTR4:[0-9]+]], !dbg [[DBG38]] // CHECK1-NEXT: call void @.omp_outlined._debug__(i32* [[TMP0]], i32* [[TMP1]], <2 x float> [[TMP3]]) #[[ATTR4:[0-9]+]], !dbg [[DBG38]]
// CHECK1-NEXT: ret void, !dbg [[DBG38]] // CHECK1-NEXT: ret void, !dbg [[DBG38]]
// //

clang/test/OpenMP/distribute_parallel_for_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,963 Lines • ▼ Show 20 Lines
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK1-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK1: omp.dispatch.cond: // CHECK1: omp.dispatch.cond:
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32 // CHECK1-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32
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// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK1-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
// CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]])
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK1: omp.dispatch.cond: // CHECK1: omp.dispatch.cond:
// CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK2-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK2-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK2: omp.dispatch.cond: // CHECK2: omp.dispatch.cond:
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32 // CHECK2-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32
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// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK2-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK2-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
// CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) // CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]])
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK2: omp.dispatch.cond: // CHECK2: omp.dispatch.cond:
// CHECK2-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK9: omp.dispatch.cond: // CHECK9: omp.dispatch.cond:
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32 // CHECK9-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32
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// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) // CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]])
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK9: omp.dispatch.cond: // CHECK9: omp.dispatch.cond:
// CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 1,707 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK9: omp.dispatch.cond: // CHECK9: omp.dispatch.cond:
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32 // CHECK9-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32
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// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) // CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]])
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK9: omp.dispatch.cond: // CHECK9: omp.dispatch.cond:
// CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK10: omp.dispatch.cond: // CHECK10: omp.dispatch.cond:
// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32 // CHECK10-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32
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// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) // CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]])
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK10: omp.dispatch.cond: // CHECK10: omp.dispatch.cond:
// CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK10: omp.dispatch.cond: // CHECK10: omp.dispatch.cond:
// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32 // CHECK10-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32
▲ Show 20 Lines • Show All 476 Lines • ▼ Show 20 Lines
// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) // CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]])
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK10: omp.dispatch.cond: // CHECK10: omp.dispatch.cond:
// CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp

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// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK1-NEXT: store double 1.000000e+00, double* [[CONV]], align 8 // CHECK1-NEXT: store double 1.000000e+00, double* [[CONV]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8
// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8 // CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8
// CHECK1-NEXT: store i32 3, i32* [[CONV2]], align 8 // CHECK1-NEXT: store i32 3, i32* [[CONV2]], align 4
// CHECK1-NEXT: store float 4.000000e+00, float* [[CONV3]], align 8 // CHECK1-NEXT: store float 4.000000e+00, float* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK1-NEXT: store double* [[CONV]], double** [[TMP11]], align 8 // CHECK1-NEXT: store double* [[CONV]], double** [[TMP11]], align 8
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK1-NEXT: [[TMP13:%.*]] = load double*, double** [[TMP]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = load double*, double** [[TMP]], align 8
// CHECK1-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8 // CHECK1-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK1-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 // CHECK1-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3
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// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK2-NEXT: store double 1.000000e+00, double* [[CONV]], align 8 // CHECK2-NEXT: store double 1.000000e+00, double* [[CONV]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8
// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8 // CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8
// CHECK2-NEXT: store i32 3, i32* [[CONV2]], align 8 // CHECK2-NEXT: store i32 3, i32* [[CONV2]], align 4
// CHECK2-NEXT: store float 4.000000e+00, float* [[CONV3]], align 8 // CHECK2-NEXT: store float 4.000000e+00, float* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK2-NEXT: store double* [[CONV]], double** [[TMP11]], align 8 // CHECK2-NEXT: store double* [[CONV]], double** [[TMP11]], align 8
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK2-NEXT: [[TMP13:%.*]] = load double*, double** [[TMP]], align 8 // CHECK2-NEXT: [[TMP13:%.*]] = load double*, double** [[TMP]], align 8
// CHECK2-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8 // CHECK2-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK2-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 // CHECK2-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3
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// CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK8: omp.inner.for.cond.cleanup: // CHECK8: omp.inner.for.cond.cleanup:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK8: omp.inner.for.body: // CHECK8: omp.inner.for.body:
// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4
// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]] // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]]
// CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 // CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4
// CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8 // CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8
// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 // CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4
// CHECK8-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64 // CHECK8-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64
// CHECK8-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i64 0, i64 [[IDXPROM11]] // CHECK8-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i64 0, i64 [[IDXPROM11]]
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// CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK8: omp.inner.for.cond.cleanup: // CHECK8: omp.inner.for.cond.cleanup:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK8: omp.inner.for.body: // CHECK8: omp.inner.for.body:
// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4
// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 // CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4
// CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 // CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8
// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 // CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4
// CHECK8-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64 // CHECK8-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64
// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
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// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK9: omp.inner.for.cond.cleanup: // CHECK9: omp.inner.for.cond.cleanup:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]]
// CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8 // CHECK9-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8
// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4
// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64 // CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64
// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i64 0, i64 [[IDXPROM11]] // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i64 0, i64 [[IDXPROM11]]
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// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK9: omp.inner.for.cond.cleanup: // CHECK9: omp.inner.for.cond.cleanup:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 // CHECK9-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8
// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4
// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64
// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
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clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp

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// CHECK1-SAME: (i64 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-SAME: (i64 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8
// CHECK1-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 // CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
// CHECK1-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 // CHECK1-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i8**)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i8** [[TMP2]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i8**)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i8** [[TMP2]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK2-SAME: (i64 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-SAME: (i64 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8
// CHECK2-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 // CHECK2-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
// CHECK2-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 // CHECK2-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i8**)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i8** [[TMP2]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i8**)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i8** [[TMP2]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
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clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK1-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK1: omp.dispatch.cond: // CHECK1: omp.dispatch.cond:
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32 // CHECK1-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32
▲ Show 20 Lines • Show All 544 Lines • ▼ Show 20 Lines
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK1-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
// CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]])
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK1: omp.dispatch.cond: // CHECK1: omp.dispatch.cond:
// CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 1,382 Lines • ▼ Show 20 Lines
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK2-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK2-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK2: omp.dispatch.cond: // CHECK2: omp.dispatch.cond:
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32 // CHECK2-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32
▲ Show 20 Lines • Show All 544 Lines • ▼ Show 20 Lines
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK2-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK2-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
// CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) // CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]])
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK2: omp.dispatch.cond: // CHECK2: omp.dispatch.cond:
// CHECK2-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 5,729 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK9: omp.dispatch.cond: // CHECK9: omp.dispatch.cond:
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32 // CHECK9-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32
▲ Show 20 Lines • Show All 524 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) // CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]])
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK9: omp.dispatch.cond: // CHECK9: omp.dispatch.cond:
// CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 1,812 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK9: omp.dispatch.cond: // CHECK9: omp.dispatch.cond:
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32 // CHECK9-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32
▲ Show 20 Lines • Show All 524 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
// CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) // CHECK9-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]])
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK9: omp.dispatch.cond: // CHECK9: omp.dispatch.cond:
// CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK10: omp.dispatch.cond: // CHECK10: omp.dispatch.cond:
// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32 // CHECK10-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32
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// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) // CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]])
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK10: omp.dispatch.cond: // CHECK10: omp.dispatch.cond:
// CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK10: omp.dispatch.cond: // CHECK10: omp.dispatch.cond:
// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32 // CHECK10-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP14]] to i32
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// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
// CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
// CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]]) // CHECK10-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], i32 35, i32 [[TMP11]], i32 [[TMP12]], i32 1, i32 [[TMP10]])
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK10: omp.dispatch.cond: // CHECK10: omp.dispatch.cond:
// CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp

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// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
// CHECK1-NEXT: store double 1.000000e+00, double* [[CONV]], align 8, !llvm.access.group !8 // CHECK1-NEXT: store double 1.000000e+00, double* [[CONV]], align 8, !llvm.access.group !8
// CHECK1-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8, !llvm.access.group !8 // CHECK1-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8, !llvm.access.group !8
// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8 // CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8
// CHECK1-NEXT: store i32 3, i32* [[CONV2]], align 8, !llvm.access.group !8 // CHECK1-NEXT: store i32 3, i32* [[CONV2]], align 4, !llvm.access.group !8
// CHECK1-NEXT: store float 4.000000e+00, float* [[CONV3]], align 8, !llvm.access.group !8 // CHECK1-NEXT: store float 4.000000e+00, float* [[CONV3]], align 4, !llvm.access.group !8
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK1-NEXT: store double* [[CONV]], double** [[TMP11]], align 8, !llvm.access.group !8 // CHECK1-NEXT: store double* [[CONV]], double** [[TMP11]], align 8, !llvm.access.group !8
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK1-NEXT: [[TMP13:%.*]] = load double*, double** [[TMP]], align 8, !llvm.access.group !8 // CHECK1-NEXT: [[TMP13:%.*]] = load double*, double** [[TMP]], align 8, !llvm.access.group !8
// CHECK1-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8, !llvm.access.group !8 // CHECK1-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8, !llvm.access.group !8
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK1-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8 // CHECK1-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3
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// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
// CHECK2-NEXT: store double 1.000000e+00, double* [[CONV]], align 8, !llvm.access.group !8 // CHECK2-NEXT: store double 1.000000e+00, double* [[CONV]], align 8, !llvm.access.group !8
// CHECK2-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8, !llvm.access.group !8 // CHECK2-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8, !llvm.access.group !8
// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8 // CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8
// CHECK2-NEXT: store i32 3, i32* [[CONV2]], align 8, !llvm.access.group !8 // CHECK2-NEXT: store i32 3, i32* [[CONV2]], align 4, !llvm.access.group !8
// CHECK2-NEXT: store float 4.000000e+00, float* [[CONV3]], align 8, !llvm.access.group !8 // CHECK2-NEXT: store float 4.000000e+00, float* [[CONV3]], align 4, !llvm.access.group !8
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK2-NEXT: store double* [[CONV]], double** [[TMP11]], align 8, !llvm.access.group !8 // CHECK2-NEXT: store double* [[CONV]], double** [[TMP11]], align 8, !llvm.access.group !8
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK2-NEXT: [[TMP13:%.*]] = load double*, double** [[TMP]], align 8, !llvm.access.group !8 // CHECK2-NEXT: [[TMP13:%.*]] = load double*, double** [[TMP]], align 8, !llvm.access.group !8
// CHECK2-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8, !llvm.access.group !8 // CHECK2-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8, !llvm.access.group !8
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK2-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8 // CHECK2-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3
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// CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK8: omp.inner.for.cond.cleanup: // CHECK8: omp.inner.for.cond.cleanup:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK8: omp.inner.for.body: // CHECK8: omp.inner.for.body:
// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 // CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]] // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]]
// CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 // CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
// CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8, !llvm.access.group !9 // CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8, !llvm.access.group !9
// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK8-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64 // CHECK8-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64
// CHECK8-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i64 0, i64 [[IDXPROM11]] // CHECK8-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i64 0, i64 [[IDXPROM11]]
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// CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK8: omp.inner.for.cond.cleanup: // CHECK8: omp.inner.for.cond.cleanup:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK8: omp.inner.for.body: // CHECK8: omp.inner.for.body:
// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17 // CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 // CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
// CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !17 // CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !17
// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 // CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK8-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64 // CHECK8-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64
// CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
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// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK9: omp.inner.for.cond.cleanup: // CHECK9: omp.inner.for.cond.cleanup:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]]
// CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 // CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8, !llvm.access.group !9 // CHECK9-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8, !llvm.access.group !9
// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64 // CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64
// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i64 0, i64 [[IDXPROM11]] // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i64 0, i64 [[IDXPROM11]]
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// CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK9: omp.inner.for.cond.cleanup: // CHECK9: omp.inner.for.cond.cleanup:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 // CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
// CHECK9-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !17 // CHECK9-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !17
// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64
// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
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clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp

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// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then: // CHECK11: omp_if.then:
// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then: // CHECK11: omp_if.then:
// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then: // CHECK12: omp_if.then:
// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then: // CHECK12: omp_if.then:
// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp

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// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK4-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[D_ADDR]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[D_ADDR]], align 8
// CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false) // CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)
// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 // CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK4: user_code.entry: // CHECK4: user_code.entry:
// CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) // CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
// CHECK4-NEXT: store i32 [[TMP6]], i32* [[CONV1]], align 4 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[CONV1]], align 4
// CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8 // CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]], [10 x i32]* [[TMP1]], i32* [[TMP2]], i64 [[TMP7]], [10 x i32]* [[TMP3]]) #[[ATTR4:[0-9]+]] // CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP0]], [10 x i32]* [[TMP1]], i32* [[TMP2]], i64 [[TMP7]], [10 x i32]* [[TMP3]]) #[[ATTR4:[0-9]+]]
// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
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// CHECK4-NEXT: store [10 x i32]* [[D]], [10 x i32]** [[D_ADDR]], align 8 // CHECK4-NEXT: store [10 x i32]* [[D]], [10 x i32]** [[D_ADDR]], align 8
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK4-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[C_ADDR]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[C_ADDR]], align 8
// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK4-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[D_ADDR]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[D_ADDR]], align 8
// CHECK4-NEXT: [[C1:%.*]] = call i8* @__kmpc_alloc_shared(i64 40) // CHECK4-NEXT: [[C1:%.*]] = call i8* @__kmpc_alloc_shared(i64 40)
// CHECK4-NEXT: [[C_ON_STACK:%.*]] = bitcast i8* [[C1]] to [10 x i32]* // CHECK4-NEXT: [[C_ON_STACK:%.*]] = bitcast i8* [[C1]] to [10 x i32]*
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK4-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK4-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK4-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK4-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 // CHECK4-NEXT: store i32 0, i32* [[I]], align 4
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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clang/test/OpenMP/nvptx_parallel_codegen.cpp

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// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** // CHECK1-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*), i8** [[TMP2]], i64 0) // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined___wrapper to i8*), i8** [[TMP2]], i64 0)
// CHECK1-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8** // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 0, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP3]], i64 0) // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 0, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP3]], i64 0)
// CHECK1-NEXT: [[TMP4:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS2]] to i8** // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS2]] to i8**
// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__2 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__2_wrapper to i8*), i8** [[TMP4]], i64 0) // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__2 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__2_wrapper to i8*), i8** [[TMP4]], i64 0)
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// CHECK1: worker.exit: // CHECK1: worker.exit:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
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// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1000 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1000
// CHECK1-NEXT: [[TMP4:%.*]] = zext i1 [[CMP]] to i32 // CHECK1-NEXT: [[TMP4:%.*]] = zext i1 [[CMP]] to i32
// CHECK1-NEXT: [[TMP5:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 [[TMP4]], i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__3 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8*), i8** [[TMP5]], i64 0) // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 [[TMP4]], i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__3 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8*), i8** [[TMP5]], i64 0)
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP7]] to i32 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP7]] to i32
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV2]], align 8 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV2]], align 2
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK1-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// CHECK1: worker.exit: // CHECK1: worker.exit:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[A1:%.*]] = call i8* @__kmpc_alloc_shared(i64 4) // CHECK1-NEXT: [[A1:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK1-NEXT: [[A_ON_STACK:%.*]] = bitcast i8* [[A1]] to i32* // CHECK1-NEXT: [[A_ON_STACK:%.*]] = bitcast i8* [[A1]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[A_ON_STACK]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[A_ON_STACK]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK1-NEXT: [[TMP4:%.*]] = bitcast i32* [[A_ON_STACK]] to i8* // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i32* [[A_ON_STACK]] to i8*
// CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8 // CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
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// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1000 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1000
// CHECK2-NEXT: [[TMP4:%.*]] = zext i1 [[CMP]] to i32 // CHECK2-NEXT: [[TMP4:%.*]] = zext i1 [[CMP]] to i32
// CHECK2-NEXT: [[TMP5:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 [[TMP4]], i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__3 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8*), i8** [[TMP5]], i32 0) // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 [[TMP4]], i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__3 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8*), i8** [[TMP5]], i32 0)
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK2-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP7]] to i32 // CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP7]] to i32
// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK2-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK2-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// CHECK2: worker.exit: // CHECK2: worker.exit:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
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clang/test/OpenMP/nvptx_parallel_for_codegen.cpp

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// CHECK-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true) // CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)
// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK: user_code.entry: // CHECK: user_code.entry:
// CHECK-NEXT: [[D:%.*]] = call i8* @__kmpc_alloc_shared(i64 4) // CHECK-NEXT: [[D:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK-NEXT: [[D_ON_STACK:%.*]] = bitcast i8* [[D]] to i32* // CHECK-NEXT: [[D_ON_STACK:%.*]] = bitcast i8* [[D]] to i32*
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK-NEXT: store i32 [[TMP3]], i32* [[D_ON_STACK]], align 4 // CHECK-NEXT: store i32 [[TMP3]], i32* [[D_ON_STACK]], align 4
// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK-NEXT: [[TMP5:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* // CHECK-NEXT: [[TMP5:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
// CHECK-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 8 // CHECK-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 8
// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-NEXT: [[TMP7:%.*]] = bitcast i32* [[D_ON_STACK]] to i8* // CHECK-NEXT: [[TMP7:%.*]] = bitcast i32* [[D_ON_STACK]] to i8*
// CHECK-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8 // CHECK-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8
// CHECK-NEXT: [[TMP8:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** // CHECK-NEXT: [[TMP8:%.*]] = bitcast [2 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
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clang/test/OpenMP/nvptx_target_codegen.cpp

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// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 8 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// CHECK1: worker.exit: // CHECK1: worker.exit:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53
// CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {
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// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP10]] to double // CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP10]] to double
// CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK1-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP3]] to i32 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP3]] to i32
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i32 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i32
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP5]], 1
// CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// CHECK1: worker.exit: // CHECK1: worker.exit:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP5]] to double // CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP5]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP6:%.*]] = load double, double* [[A4]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load double, double* [[A4]], align 8
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
// CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// CHECK1: worker.exit: // CHECK1: worker.exit:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry: // CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2
// CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// CHECK2: worker.exit: // CHECK2: worker.exit:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53
// CHECK2-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {
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// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry: // CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK2-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 // CHECK2-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK2-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK2-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP5]], 1
// CHECK2-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// CHECK2: worker.exit: // CHECK2: worker.exit:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
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// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry: // CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP3]] to i32 // CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP3]] to i32
// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK2-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK2-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// CHECK2: worker.exit: // CHECK2: worker.exit:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
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// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK3: user_code.entry: // CHECK3: user_code.entry:
// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// CHECK3: worker.exit: // CHECK3: worker.exit:
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53
// CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { // CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {
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// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK3: user_code.entry: // CHECK3: user_code.entry:
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP5]], 1
// CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// CHECK3: worker.exit: // CHECK3: worker.exit:
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
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// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK3: user_code.entry: // CHECK3: user_code.entry:
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP3]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP3]] to i32
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// CHECK3: worker.exit: // CHECK3: worker.exit:
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
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clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp

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// CHECK1-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK1-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP0]] to i8*
// CHECK1-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8 // CHECK1-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK1-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP1]] to i8* // CHECK1-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP1]] to i8*
// CHECK1-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 8 // CHECK1-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
// CHECK1-NEXT: [[TMP11:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8* // CHECK1-NEXT: [[TMP11:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
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// CHECK4-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
// CHECK4-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK4-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) // CHECK4-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true)
// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1 // CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK4: user_code.entry: // CHECK4: user_code.entry:
// CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK4-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP0]] to i8*
// CHECK4-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8 // CHECK4-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8
// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK4-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP1]] to i8* // CHECK4-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP1]] to i8*
// CHECK4-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 8 // CHECK4-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 8
// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
// CHECK4-NEXT: [[TMP11:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8* // CHECK4-NEXT: [[TMP11:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8*
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clang/test/OpenMP/nvptx_target_printf_codegen.c

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// CHECK-64-NEXT: [[FOO_ADDR:%.*]] = alloca i64, align 8 // CHECK-64-NEXT: [[FOO_ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[TMP:%.*]] = alloca [[PRINTF_ARGS_0:%.*]], align 8 // CHECK-64-NEXT: [[TMP:%.*]] = alloca [[PRINTF_ARGS_0:%.*]], align 8
// CHECK-64-NEXT: store i64 [[FOO]], i64* [[FOO_ADDR]], align 8 // CHECK-64-NEXT: store i64 [[FOO]], i64* [[FOO_ADDR]], align 8
// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[FOO_ADDR]] to i32* // CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[FOO_ADDR]] to i32*
// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry: // CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK-64-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 // CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] // CHECK-64-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
// CHECK-64: if.then: // CHECK-64: if.then:
// CHECK-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[PRINTF_ARGS_0]], %printf_args.0* [[TMP]], i32 0, i32 0 // CHECK-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[PRINTF_ARGS_0]], %printf_args.0* [[TMP]], i32 0, i32 0
// CHECK-64-NEXT: store i32 42, i32* [[TMP2]], align 4 // CHECK-64-NEXT: store i32 42, i32* [[TMP2]], align 4
// CHECK-64-NEXT: [[TMP3:%.*]] = bitcast %printf_args.0* [[TMP]] to i8* // CHECK-64-NEXT: [[TMP3:%.*]] = bitcast %printf_args.0* [[TMP]] to i8*
// CHECK-64-NEXT: [[TMP4:%.*]] = call i32 @__llvm_omp_vprintf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str2, i64 0, i64 0), i8* [[TMP3]], i32 4) // CHECK-64-NEXT: [[TMP4:%.*]] = call i32 @__llvm_omp_vprintf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str2, i64 0, i64 0), i8* [[TMP3]], i32 4)
// CHECK-64-NEXT: br label [[IF_END]] // CHECK-64-NEXT: br label [[IF_END]]
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clang/test/OpenMP/nvptx_target_teams_codegen.cpp

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// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i8* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1 // CHECK1-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP3]]) #[[ATTR1:[0-9]+]] // CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP3]]) #[[ATTR1:[0-9]+]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// CHECK1: worker.exit: // CHECK1: worker.exit:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
// CHECK1-NEXT: store i8 49, i8* [[CONV]], align 8 // CHECK1-NEXT: store i8 49, i8* [[CONV]], align 1
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28
// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP3]]) #[[ATTR1]] // CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP3]]) #[[ATTR1]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// CHECK1: worker.exit: // CHECK1: worker.exit:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: store i16 1, i16* [[CONV]], align 8 // CHECK1-NEXT: store i16 1, i16* [[CONV]], align 2
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33
// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP3]]) #[[ATTR1]] // CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP3]]) #[[ATTR1]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry: // CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1 // CHECK2-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1:[0-9]+]] // CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1:[0-9]+]]
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// CHECK2: worker.exit: // CHECK2: worker.exit:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8*
// CHECK2-NEXT: store i8 49, i8* [[CONV]], align 4 // CHECK2-NEXT: store i8 49, i8* [[CONV]], align 1
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28
// CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry: // CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]] // CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]]
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// CHECK2: worker.exit: // CHECK2: worker.exit:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK2-NEXT: store i16 1, i16* [[CONV]], align 4 // CHECK2-NEXT: store i16 1, i16* [[CONV]], align 2
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33
// CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry: // CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK2-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]] // CHECK2-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]]
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
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// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8*
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK3: user_code.entry: // CHECK3: user_code.entry:
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8*
// CHECK3-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1 // CHECK3-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1:[0-9]+]] // CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1:[0-9]+]]
// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// CHECK3: worker.exit: // CHECK3: worker.exit:
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8*
// CHECK3-NEXT: store i8 49, i8* [[CONV]], align 4 // CHECK3-NEXT: store i8 49, i8* [[CONV]], align 1
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28
// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK3: user_code.entry: // CHECK3: user_code.entry:
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]] // CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]]
// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// CHECK3: worker.exit: // CHECK3: worker.exit:
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: store i16 1, i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 1, i16* [[CONV]], align 2
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33
// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true)
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK3: user_code.entry: // CHECK3: user_code.entry:
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK3-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]] // CHECK3-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR1]]
// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true)
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
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clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp

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// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[L_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[L_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[L_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[L_CASTED]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8 // CHECK1-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
// CHECK1-NEXT: [[L2:%.*]] = call i8* @__kmpc_alloc_shared(i64 4) // CHECK1-NEXT: [[L2:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK1-NEXT: [[L_ON_STACK:%.*]] = bitcast i8* [[L2]] to i32* // CHECK1-NEXT: [[L_ON_STACK:%.*]] = bitcast i8* [[L2]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
// CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] // CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[L_CASTED]] to i32* // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[L_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[L_CASTED]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[L_CASTED]], align 8
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to i8* // CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to i8*
// CHECK1-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8 // CHECK1-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK1-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to i8* // CHECK1-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to i8*
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// CHECK1: omp.loop.exit: // CHECK1: omp.loop.exit:
// CHECK1-NEXT: [[TMP46:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP46:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP47:%.*]] = load i32, i32* [[TMP46]], align 4 // CHECK1-NEXT: [[TMP47:%.*]] = load i32, i32* [[TMP46]], align 4
// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP47]]) // CHECK1-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP47]])
// CHECK1-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0 // CHECK1-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0
// CHECK1-NEXT: br i1 [[TMP49]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP49]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK1: .omp.lastprivate.then: // CHECK1: .omp.lastprivate.then:
// CHECK1-NEXT: [[TMP50:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP50:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP50]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[TMP50]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done: // CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: br label [[OMP_PRECOND_END]] // CHECK1-NEXT: br label [[OMP_PRECOND_END]]
// CHECK1: omp.precond.end: // CHECK1: omp.precond.end:
// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[L2]], i64 4) // CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[L2]], i64 4)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8 // CHECK1-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I6]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 1, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 1, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1
// CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK1: omp.dispatch.end: // CHECK1: omp.dispatch.end:
// CHECK1-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4
// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP27]]) // CHECK1-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP27]])
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 // CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
// CHECK1-NEXT: br i1 [[TMP29]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP29]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK1: .omp.lastprivate.then: // CHECK1: .omp.lastprivate.then:
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done: // CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: br label [[OMP_PRECOND_END]] // CHECK1-NEXT: br label [[OMP_PRECOND_END]]
// CHECK1: omp.precond.end: // CHECK1: omp.precond.end:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34
// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-SAME: (i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 8
// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]] // CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] // CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK1-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to i8* // CHECK1-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to i8*
// CHECK1-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8 // CHECK1-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to i8* // CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to i8*
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK1-NEXT: store i64 [[F]], i64* [[F_ADDR]], align 8 // CHECK1-NEXT: store i64 [[F]], i64* [[F_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[F_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[F_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[F_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[F_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[F_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[F_CASTED]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i64 [[TMP4]]) #[[ATTR2]] // CHECK1-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100 // CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[F_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[F_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[F_CASTED]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[F_CASTED]], align 8
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to i8* // CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to i8*
// CHECK1-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 // CHECK1-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK1-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to i8* // CHECK1-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to i8*
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// CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[DIV5]], 10 // CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[DIV5]], 10
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL6]] // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL6]]
// CHECK1-NEXT: [[MUL7:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK1-NEXT: [[MUL7:%.*]] = mul nsw i32 [[SUB]], 1
// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 0, [[MUL7]] // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 0, [[MUL7]]
// CHECK1-NEXT: store i32 [[ADD8]], i32* [[J]], align 4 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[J]], align 4
// CHECK1-NEXT: store i32 10, i32* [[K]], align 4 // CHECK1-NEXT: store i32 10, i32* [[K]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]] // CHECK1-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]]
// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP11]], [[MUL9]] // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP11]], [[MUL9]]
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[K]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[K]], align 4
// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD10]], [[TMP14]] // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD10]], [[TMP14]]
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[J]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[J]], align 4
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// CHECK1-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK1-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: call void @__omp_outlined__8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [10 x [10 x i32]]* [[TMP0]]) #[[ATTR2]] // CHECK1-NEXT: call void @__omp_outlined__8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [10 x [10 x i32]]* [[TMP0]]) #[[ATTR2]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK1-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = sext i32 [[DIV]] to i64 // CHECK1-NEXT: [[CONV4:%.*]] = sext i32 [[DIV]] to i64
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i32 [[TMP4]], 0 // CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i32 [[TMP4]], 0
// CHECK1-NEXT: [[DIV6:%.*]] = sdiv i32 [[SUB5]], 1 // CHECK1-NEXT: [[DIV6:%.*]] = sdiv i32 [[SUB5]], 1
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// CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP16]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP16]], 1
// CHECK1-NEXT: [[CMP14:%.*]] = icmp slt i64 [[TMP15]], [[ADD]] // CHECK1-NEXT: [[CMP14:%.*]] = icmp slt i64 [[TMP15]], [[ADD]]
// CHECK1-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8
// CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV15:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV15:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV15]], align 4 // CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV15]], align 4
// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK1-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP17]] to i8* // CHECK1-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP17]] to i8*
// CHECK1-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 8 // CHECK1-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 8
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK1-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP18]] to i8* // CHECK1-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP18]] to i8*
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK1-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = sext i32 [[DIV]] to i64 // CHECK1-NEXT: [[CONV4:%.*]] = sext i32 [[DIV]] to i64
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i32 [[TMP4]], 0 // CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i32 [[TMP4]], 0
// CHECK1-NEXT: [[DIV6:%.*]] = sdiv i32 [[SUB5]], 1 // CHECK1-NEXT: [[DIV6:%.*]] = sdiv i32 [[SUB5]], 1
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// CHECK1-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8 // CHECK1-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[V_ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[V_ADDR]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: call void @__omp_outlined__10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i32* [[TMP5]]) #[[ATTR2]] // CHECK1-NEXT: call void @__omp_outlined__10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i32* [[TMP5]]) #[[ATTR2]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
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// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8 // CHECK1-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] // CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: [[TMP20:%.*]] = load i32*, i32** [[V_ADDR]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load i32*, i32** [[V_ADDR]], align 8
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK1-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP15]] to i8* // CHECK1-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP15]] to i8*
// CHECK1-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 8 // CHECK1-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 8
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
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// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8 // CHECK1-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false) // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry: // CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[L_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[L_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[L_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[L_CASTED]], align 8
// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
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// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8 // CHECK2-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
// CHECK2-NEXT: [[L2:%.*]] = call i8* @__kmpc_alloc_shared(i64 4) // CHECK2-NEXT: [[L2:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK2-NEXT: [[L_ON_STACK:%.*]] = bitcast i8* [[L2]] to i32* // CHECK2-NEXT: [[L_ON_STACK:%.*]] = bitcast i8* [[L2]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK2-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK2-NEXT: store i32 0, i32* [[I]], align 4 // CHECK2-NEXT: store i32 0, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
// CHECK2-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] // CHECK2-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[L_CASTED]] to i32* // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[L_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 // CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[L_CASTED]], align 8 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[L_CASTED]], align 8
// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK2-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to i8* // CHECK2-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to i8*
// CHECK2-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8 // CHECK2-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8
// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK2-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to i8* // CHECK2-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to i8*
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// CHECK2: omp.loop.exit: // CHECK2: omp.loop.exit:
// CHECK2-NEXT: [[TMP46:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP46:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP47:%.*]] = load i32, i32* [[TMP46]], align 4 // CHECK2-NEXT: [[TMP47:%.*]] = load i32, i32* [[TMP46]], align 4
// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP47]]) // CHECK2-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP47]])
// CHECK2-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0 // CHECK2-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0
// CHECK2-NEXT: br i1 [[TMP49]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP49]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK2: .omp.lastprivate.then: // CHECK2: .omp.lastprivate.then:
// CHECK2-NEXT: [[TMP50:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP50:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP50]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[TMP50]], i32* [[CONV1]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done: // CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: br label [[OMP_PRECOND_END]] // CHECK2-NEXT: br label [[OMP_PRECOND_END]]
// CHECK2: omp.precond.end: // CHECK2: omp.precond.end:
// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[L2]], i64 4) // CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[L2]], i64 4)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
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// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8 // CHECK2-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK2-NEXT: store i32 0, i32* [[I]], align 4 // CHECK2-NEXT: store i32 0, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I6]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 1, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 1, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1 // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1
// CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK2: omp.dispatch.end: // CHECK2: omp.dispatch.end:
// CHECK2-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4
// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP27]]) // CHECK2-NEXT: call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP27]])
// CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 // CHECK2-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
// CHECK2-NEXT: br i1 [[TMP29]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP29]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK2: .omp.lastprivate.then: // CHECK2: .omp.lastprivate.then:
// CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done: // CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: br label [[OMP_PRECOND_END]] // CHECK2-NEXT: br label [[OMP_PRECOND_END]]
// CHECK2: omp.precond.end: // CHECK2: omp.precond.end:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34
// CHECK2-SAME: (i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-SAME: (i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 8
// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry: // CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK2-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]] // CHECK2-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
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// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK2-NEXT: store i32 0, i32* [[I]], align 4 // CHECK2-NEXT: store i32 0, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] // CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK2-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to i8* // CHECK2-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to i8*
// CHECK2-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8 // CHECK2-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8
// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK2-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to i8* // CHECK2-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to i8*
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// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK2-NEXT: store i32 0, i32* [[I]], align 4 // CHECK2-NEXT: store i32 0, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
▲ Show 20 Lines • Show All 255 Lines • ▼ Show 20 Lines
// CHECK2-NEXT: store i64 [[F]], i64* [[F_ADDR]], align 8 // CHECK2-NEXT: store i64 [[F]], i64* [[F_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[F_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[F_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry: // CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[F_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[F_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[F_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[F_CASTED]], align 8
// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK2-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i64 [[TMP4]]) #[[ATTR2]] // CHECK2-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
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// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100 // CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[F_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[F_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[F_CASTED]], align 8 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[F_CASTED]], align 8
// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK2-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to i8* // CHECK2-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to i8*
// CHECK2-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8 // CHECK2-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK2-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to i8* // CHECK2-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to i8*
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// CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[DIV5]], 10 // CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[DIV5]], 10
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL6]] // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL6]]
// CHECK2-NEXT: [[MUL7:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK2-NEXT: [[MUL7:%.*]] = mul nsw i32 [[SUB]], 1
// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 0, [[MUL7]] // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 0, [[MUL7]]
// CHECK2-NEXT: store i32 [[ADD8]], i32* [[J]], align 4 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[J]], align 4
// CHECK2-NEXT: store i32 10, i32* [[K]], align 4 // CHECK2-NEXT: store i32 10, i32* [[K]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]] // CHECK2-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]]
// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP11]], [[MUL9]] // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP11]], [[MUL9]]
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[K]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[K]], align 4
// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD10]], [[TMP14]] // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD10]], [[TMP14]]
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[J]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[J]], align 4
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// CHECK2-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK2-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry: // CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK2-NEXT: call void @__omp_outlined__8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [10 x [10 x i32]]* [[TMP0]]) #[[ATTR2]] // CHECK2-NEXT: call void @__omp_outlined__8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [10 x [10 x i32]]* [[TMP0]]) #[[ATTR2]]
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
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// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK2-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK2-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0 // CHECK2-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0
// CHECK2-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 // CHECK2-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], [[DIV5]] // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], [[DIV5]]
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// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK2-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK2-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
// CHECK2-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV12:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV12:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP21]], i32* [[CONV12]], align 4 // CHECK2-NEXT: store i32 [[TMP21]], i32* [[CONV12]], align 4
// CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK2-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP18]] to i8* // CHECK2-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP18]] to i8*
// CHECK2-NEXT: store i8* [[TMP24]], i8** [[TMP23]], align 8 // CHECK2-NEXT: store i8* [[TMP24]], i8** [[TMP23]], align 8
// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK2-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP20]] to i8* // CHECK2-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP20]] to i8*
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// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK2-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK2-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0 // CHECK2-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0
// CHECK2-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 // CHECK2-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], [[DIV5]] // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], [[DIV5]]
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// CHECK2-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8 // CHECK2-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry: // CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[V_ADDR]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[V_ADDR]], align 8
// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK2-NEXT: call void @__omp_outlined__10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i32* [[TMP5]]) #[[ATTR2]] // CHECK2-NEXT: call void @__omp_outlined__10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i32* [[TMP5]]) #[[ATTR2]]
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
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// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 8 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8 // CHECK2-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK2-NEXT: store i32 0, i32* [[I]], align 4 // CHECK2-NEXT: store i32 0, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] // CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: [[TMP20:%.*]] = load i32*, i32** [[V_ADDR]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load i32*, i32** [[V_ADDR]], align 8
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK2-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP15]] to i8* // CHECK2-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP15]] to i8*
// CHECK2-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 8 // CHECK2-NEXT: store i8* [[TMP22]], i8** [[TMP21]], align 8
// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
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// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8 // CHECK2-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK2-NEXT: store i32 0, i32* [[I]], align 4 // CHECK2-NEXT: store i32 0, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp

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// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], i32* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], i32* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 // CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
// CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
// CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] // CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32* // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to i8* // CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to i8*
// CHECK1-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8 // CHECK1-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK1-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to i8* // CHECK1-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to i8*
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// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 // CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
// CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK1: omp.precond.then: // CHECK1: omp.precond.then:
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP5]] to i32 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP5]] to i32
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP6]] to i32 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP6]] to i32
// CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK1: omp.dispatch.cond: // CHECK1: omp.dispatch.cond:
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: [[CONV8:%.*]] = trunc i64 [[TMP11]] to i32 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i64 [[TMP11]] to i32
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// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false) // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)
// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK4: user_code.entry: // CHECK4: user_code.entry:
// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) // CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32* // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], i32* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], i32* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]
// CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
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// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 // CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK4-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK4-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK4-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK4-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 // CHECK4-NEXT: store i32 0, i32* [[I]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
// CHECK4-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] // CHECK4-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
// CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK4-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK4-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK4-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK4-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[CONV8:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32* // CHECK4-NEXT: [[CONV8:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
// CHECK4-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 // CHECK4-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK4-NEXT: [[TMP19:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8 // CHECK4-NEXT: [[TMP19:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK4-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK4-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK4-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 // CHECK4-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK4-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK4-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK4-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to i8* // CHECK4-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to i8*
// CHECK4-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8 // CHECK4-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8
// CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK4-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to i8* // CHECK4-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to i8*
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// CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 // CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
// CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK4-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK4-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK4-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK4-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK4-NEXT: store i32 0, i32* [[I]], align 4 // CHECK4-NEXT: store i32 0, i32* [[I]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK4: omp.precond.then: // CHECK4: omp.precond.then:
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP5]] to i32 // CHECK4-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP5]] to i32
// CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK4-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP6]] to i32 // CHECK4-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP6]] to i32
// CHECK4-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 // CHECK4-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
// CHECK4-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK4: omp.dispatch.cond: // CHECK4: omp.dispatch.cond:
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK4-NEXT: [[CONV8:%.*]] = trunc i64 [[TMP11]] to i32 // CHECK4-NEXT: [[CONV8:%.*]] = trunc i64 [[TMP11]] to i32
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clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp

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// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 false)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[L_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[L_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[L_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[L_CASTED]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i32]* [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8 // CHECK1-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
// CHECK1-NEXT: [[L2:%.*]] = call i8* @__kmpc_alloc_shared(i64 4) // CHECK1-NEXT: [[L2:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK1-NEXT: [[L_ON_STACK:%.*]] = bitcast i8* [[L2]] to i32* // CHECK1-NEXT: [[L_ON_STACK:%.*]] = bitcast i8* [[L2]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
// CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] // CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !12 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !12 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !12
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !12 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[L_CASTED]] to i32* // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[L_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !12 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[L_CASTED]], align 8, !llvm.access.group !12 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[L_CASTED]], align 8, !llvm.access.group !12
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to i8* // CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to i8*
// CHECK1-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8, !llvm.access.group !12 // CHECK1-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8, !llvm.access.group !12
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK1-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to i8* // CHECK1-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to i8*
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// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD20]], i32* [[I5]], align 4 // CHECK1-NEXT: store i32 [[ADD20]], i32* [[I5]], align 4
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK1: .omp.final.done: // CHECK1: .omp.final.done:
// CHECK1-NEXT: [[TMP51:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP51:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0 // CHECK1-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0
// CHECK1-NEXT: br i1 [[TMP52]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP52]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK1: .omp.lastprivate.then: // CHECK1: .omp.lastprivate.then:
// CHECK1-NEXT: [[TMP53:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP53:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP53]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[TMP53]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done: // CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: br label [[OMP_PRECOND_END]] // CHECK1-NEXT: br label [[OMP_PRECOND_END]]
// CHECK1: omp.precond.end: // CHECK1: omp.precond.end:
// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[L2]], i64 4) // CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[L2]], i64 4)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8 // CHECK1-NEXT: store i64 [[L]], i64* [[L_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !16 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !16
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !16 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !16
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 1, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16 // CHECK1-NEXT: store i32 1, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !16 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !16
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8, !llvm.access.group !16 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4, !llvm.access.group !16
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1
// CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
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// CHECK1-NEXT: [[ADD18:%.*]] = add nsw i32 0, [[MUL17]] // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i32 0, [[MUL17]]
// CHECK1-NEXT: store i32 [[ADD18]], i32* [[I6]], align 4 // CHECK1-NEXT: store i32 [[ADD18]], i32* [[I6]], align 4
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK1: .omp.final.done: // CHECK1: .omp.final.done:
// CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
// CHECK1-NEXT: br i1 [[TMP32]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP32]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK1: .omp.lastprivate.then: // CHECK1: .omp.lastprivate.then:
// CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done: // CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: br label [[OMP_PRECOND_END]] // CHECK1-NEXT: br label [[OMP_PRECOND_END]]
// CHECK1: omp.precond.end: // CHECK1: omp.precond.end:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32
// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-SAME: (i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 8
// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]] // CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], [1000 x i16]* [[TMP0]]) #[[ATTR2]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] // CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !19 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !19
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !19 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !19
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !19 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !19
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !19 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !19
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK1-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to i8* // CHECK1-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to i8*
// CHECK1-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8, !llvm.access.group !19 // CHECK1-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8, !llvm.access.group !19
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to i8* // CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to i8*
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK1-NEXT: store i64 [[F]], i64* [[F_ADDR]], align 8 // CHECK1-NEXT: store i64 [[F]], i64* [[F_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[F_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[F_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 false)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[F_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[F_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[F_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[F_CASTED]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i64 [[TMP4]]) #[[ATTR2]] // CHECK1-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], [10 x [10 x i32]]* [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false) // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 false)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
// CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100 // CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !31 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !31
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !31 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !31
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[F_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[F_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4, !llvm.access.group !31 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4, !llvm.access.group !31
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[F_CASTED]], align 8, !llvm.access.group !31 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[F_CASTED]], align 8, !llvm.access.group !31
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to i8* // CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to i8*
// CHECK1-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8, !llvm.access.group !31 // CHECK1-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8, !llvm.access.group !31
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK1-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to i8* // CHECK1-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to i8*
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// CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[DIV5]], 10 // CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[DIV5]], 10
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL6]] // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL6]]
// CHECK1-NEXT: [[MUL7:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK1-NEXT: [[MUL7:%.*]] = mul nsw i32 [[SUB]], 1
// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 0, [[MUL7]] // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 0, [[MUL7]]
// CHECK1-NEXT: store i32 [[ADD8]], i32* [[J]], align 4, !llvm.access.group !34 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[J]], align 4, !llvm.access.group !34
// CHECK1-NEXT: store i32 10, i32* [[K]], align 4, !llvm.access.group !34 // CHECK1-NEXT: store i32 10, i32* [[K]], align 4, !llvm.access.group !34
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !34 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !34
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !34 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !34
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !34 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !34
// CHECK1-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]] // CHECK1-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]]
// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP11]], [[MUL9]] // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP11]], [[MUL9]]
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[K]], align 4, !llvm.access.group !34 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[K]], align 4, !llvm.access.group !34
// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD10]], [[TMP14]] // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD10]], [[TMP14]]
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !34 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !34
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !34 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !34
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clang/test/OpenMP/nvptx_teams_codegen.cpp

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// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 // CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ARGC1:%.*]] = call i8* @__kmpc_alloc_shared(i64 4) // CHECK1-NEXT: [[ARGC1:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK1-NEXT: [[ARGC_ON_STACK:%.*]] = bitcast i8* [[ARGC1]] to i32* // CHECK1-NEXT: [[ARGC_ON_STACK:%.*]] = bitcast i8* [[ARGC1]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[ARGC_ON_STACK]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[ARGC_ON_STACK]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32* [[ARGC_ON_STACK]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32* [[ARGC_ON_STACK]]) #[[ATTR2:[0-9]+]]
// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[ARGC1]], i64 4) // CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[ARGC1]], i64 4)
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// CHECK3-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 // CHECK3-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK3: user_code.entry: // CHECK3: user_code.entry:
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK3-NEXT: [[ARGC3:%.*]] = call i8* @__kmpc_alloc_shared(i64 4) // CHECK3-NEXT: [[ARGC3:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK3-NEXT: [[ARGC_ON_STACK:%.*]] = bitcast i8* [[ARGC3]] to i32* // CHECK3-NEXT: [[ARGC_ON_STACK:%.*]] = bitcast i8* [[ARGC3]] to i32*
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[ARGC_ON_STACK]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[ARGC_ON_STACK]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32* [[ARGC_ON_STACK]]) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32* [[ARGC_ON_STACK]]) #[[ATTR2:[0-9]+]]
// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[ARGC3]], i64 4) // CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[ARGC3]], i64 4)
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clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp

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// CHECK1-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 // CHECK1-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
// CHECK1-NEXT: store i64 [[D]], i64* [[D_ADDR]], align 8 // CHECK1-NEXT: store i64 [[D]], i64* [[D_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[C_ADDR]] to i8* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[C_ADDR]] to i8*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[D_ADDR]] to float* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[D_ADDR]] to float*
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry: // CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[C2:%.*]] = call i8* @__kmpc_alloc_shared(i64 1) // CHECK1-NEXT: [[C2:%.*]] = call i8* @__kmpc_alloc_shared(i64 1)
// CHECK1-NEXT: store i8 [[TMP1]], i8* [[C2]], align 1 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[C2]], align 1
// CHECK1-NEXT: [[TMP2:%.*]] = load float, float* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load float, float* [[CONV1]], align 4
// CHECK1-NEXT: [[D3:%.*]] = call i8* @__kmpc_alloc_shared(i64 4) // CHECK1-NEXT: [[D3:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK1-NEXT: [[D_ON_STACK:%.*]] = bitcast i8* [[D3]] to float* // CHECK1-NEXT: [[D_ON_STACK:%.*]] = bitcast i8* [[D3]] to float*
// CHECK1-NEXT: store float [[TMP2]], float* [[D_ON_STACK]], align 4 // CHECK1-NEXT: store float [[TMP2]], float* [[D_ON_STACK]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i8* [[C2]], float* [[D_ON_STACK]]) #[[ATTR3]] // CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i8* [[C2]], float* [[D_ON_STACK]]) #[[ATTR3]]
// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[D3]], i64 4) // CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[D3]], i64 4)
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// CHECK2-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 // CHECK2-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
// CHECK2-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4 // CHECK2-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[C_ADDR]] to i8* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[C_ADDR]] to i8*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i32* [[D_ADDR]] to float* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i32* [[D_ADDR]] to float*
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry: // CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[C2:%.*]] = call i8* @__kmpc_alloc_shared(i32 1) // CHECK2-NEXT: [[C2:%.*]] = call i8* @__kmpc_alloc_shared(i32 1)
// CHECK2-NEXT: store i8 [[TMP1]], i8* [[C2]], align 1 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[C2]], align 1
// CHECK2-NEXT: [[TMP2:%.*]] = load float, float* [[CONV1]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load float, float* [[CONV1]], align 4
// CHECK2-NEXT: [[D3:%.*]] = call i8* @__kmpc_alloc_shared(i32 4) // CHECK2-NEXT: [[D3:%.*]] = call i8* @__kmpc_alloc_shared(i32 4)
// CHECK2-NEXT: [[D_ON_STACK:%.*]] = bitcast i8* [[D3]] to float* // CHECK2-NEXT: [[D_ON_STACK:%.*]] = bitcast i8* [[D3]] to float*
// CHECK2-NEXT: store float [[TMP2]], float* [[D_ON_STACK]], align 4 // CHECK2-NEXT: store float [[TMP2]], float* [[D_ON_STACK]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
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// CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
// CHECK3-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4 // CHECK3-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[C_ADDR]] to i8* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[C_ADDR]] to i8*
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[D_ADDR]] to float* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[D_ADDR]] to float*
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 true, i1 true)
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK3: user_code.entry: // CHECK3: user_code.entry:
// CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[C2:%.*]] = call i8* @__kmpc_alloc_shared(i32 1) // CHECK3-NEXT: [[C2:%.*]] = call i8* @__kmpc_alloc_shared(i32 1)
// CHECK3-NEXT: store i8 [[TMP1]], i8* [[C2]], align 1 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[C2]], align 1
// CHECK3-NEXT: [[TMP2:%.*]] = load float, float* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load float, float* [[CONV1]], align 4
// CHECK3-NEXT: [[D3:%.*]] = call i8* @__kmpc_alloc_shared(i32 4) // CHECK3-NEXT: [[D3:%.*]] = call i8* @__kmpc_alloc_shared(i32 4)
// CHECK3-NEXT: [[D_ON_STACK:%.*]] = bitcast i8* [[D3]] to float* // CHECK3-NEXT: [[D_ON_STACK:%.*]] = bitcast i8* [[D3]] to float*
// CHECK3-NEXT: store float [[TMP2]], float* [[D_ON_STACK]], align 4 // CHECK3-NEXT: store float [[TMP2]], float* [[D_ON_STACK]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
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clang/test/OpenMP/parallel_firstprivate_codegen.cpp

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// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
// CHECK9: omp.arraycpy.done4: // CHECK9: omp.arraycpy.done4:
// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
// CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0
// CHECK9-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0
// CHECK9-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* // CHECK9-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
// CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* // CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false)
// CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 8 // CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 4
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2
// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK9: arraydestroy.body: // CHECK9: arraydestroy.body:
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
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// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK9-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i64 4, i8* inttoptr (i64 1 to i8*)) // CHECK9-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i64 4, i8* inttoptr (i64 1 to i8*))
// CHECK9-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32* // CHECK9-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8* // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8*
// CHECK9-NEXT: call void @__kmpc_free(i32 [[TMP1]], i8* [[TMP3]], i8* inttoptr (i64 1 to i8*)) // CHECK9-NEXT: call void @__kmpc_free(i32 [[TMP1]], i8* [[TMP3]], i8* inttoptr (i64 1 to i8*))
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
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// CHECK9-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8* // CHECK9-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8*
// CHECK9-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* // CHECK9-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false)
// CHECK9-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8 // CHECK9-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 // CHECK9-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 // CHECK9-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1
// CHECK9-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 // CHECK9-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1
// CHECK9-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 // CHECK9-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP6]], align 8
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2
// CHECK9-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
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// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
// CHECK10: omp.arraycpy.done4: // CHECK10: omp.arraycpy.done4:
// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
// CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) // CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] // CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0
// CHECK10-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0
// CHECK10-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* // CHECK10-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
// CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* // CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false)
// CHECK10-NEXT: store i32 2, i32* [[CONV1]], align 8 // CHECK10-NEXT: store i32 2, i32* [[CONV1]], align 4
// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
// CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2
// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK10: arraydestroy.body: // CHECK10: arraydestroy.body:
// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
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// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK10-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i64 4, i8* inttoptr (i64 1 to i8*)) // CHECK10-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i64 4, i8* inttoptr (i64 1 to i8*))
// CHECK10-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32* // CHECK10-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8* // CHECK10-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8*
// CHECK10-NEXT: call void @__kmpc_free(i32 [[TMP1]], i8* [[TMP3]], i8* inttoptr (i64 1 to i8*)) // CHECK10-NEXT: call void @__kmpc_free(i32 [[TMP1]], i8* [[TMP3]], i8* inttoptr (i64 1 to i8*))
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
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// CHECK10-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8* // CHECK10-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8*
// CHECK10-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* // CHECK10-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false) // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false)
// CHECK10-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8 // CHECK10-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
// CHECK10-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 // CHECK10-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 // CHECK10-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1
// CHECK10-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 // CHECK10-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1
// CHECK10-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 // CHECK10-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP6]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP6]], align 8
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2
// CHECK10-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
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// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32*
// CHECK11-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 // CHECK11-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
// CHECK11-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 // CHECK11-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8
// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK11-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 // CHECK11-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 // CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1
// CHECK11-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 // CHECK11-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP3]], align 8 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP3]], align 8
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1
// CHECK11-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 // CHECK11-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK11-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK11-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
// CHECK11-NEXT: store i32 1, i32* [[G1]], align 128 // CHECK11-NEXT: store i32 1, i32* [[G1]], align 128
// CHECK11-NEXT: store i32 2, i32* [[CONV]], align 8 // CHECK11-NEXT: store i32 2, i32* [[CONV]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0
// CHECK11-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8 // CHECK11-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1
// CHECK11-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8 // CHECK11-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8
// CHECK11-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK11-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
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// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK12-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK12-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK12-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK12-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
// CHECK12-NEXT: store i32 1, i32* [[G1]], align 128 // CHECK12-NEXT: store i32 1, i32* [[G1]], align 128
// CHECK12-NEXT: store i32 2, i32* [[CONV]], align 8 // CHECK12-NEXT: store i32 2, i32* [[CONV]], align 4
// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 0 // CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 0
// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 // CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128
// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 1 // CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 1
// CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 // CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8
// CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 2 // CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 2
// CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 // CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4
// CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 3 // CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 3
// CHECK12-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 16 // CHECK12-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 16
// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 4 // CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 4
// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 // CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8
// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 // CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 7
// CHECK12-NEXT: [[TMP2:%.*]] = load volatile i32, i32* [[G1]], align 128 // CHECK12-NEXT: [[TMP2:%.*]] = load volatile i32, i32* [[G1]], align 128
// CHECK12-NEXT: store volatile i32 [[TMP2]], i32* [[BLOCK_CAPTURED]], align 128 // CHECK12-NEXT: store volatile i32 [[TMP2]], i32* [[BLOCK_CAPTURED]], align 128
// CHECK12-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 // CHECK12-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[BLOCK_CAPTURED2]], align 32 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[BLOCK_CAPTURED2]], align 32
// CHECK12-NEXT: [[TMP4:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]] to void ()* // CHECK12-NEXT: [[TMP4:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]] to void ()*
// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP4]] to %struct.__block_literal_generic* // CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP4]] to %struct.__block_literal_generic*
// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3
// CHECK12-NEXT: [[TMP6:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK12-NEXT: [[TMP6:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8*
// CHECK12-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP5]], align 8 // CHECK12-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP5]], align 8
// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to void (i8*)* // CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to void (i8*)*
// CHECK12-NEXT: call void [[TMP8]](i8* [[TMP6]]) // CHECK12-NEXT: call void [[TMP8]](i8* [[TMP6]])
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// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 // CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4
// CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.4 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 // CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.4 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8
// CHECK12-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 // CHECK12-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5
// CHECK12-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 // CHECK12-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8
// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 // CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6
// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK12-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 8 // CHECK12-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 8
// CHECK12-NEXT: [[BLOCK_CAPTURED7:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 // CHECK12-NEXT: [[BLOCK_CAPTURED7:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK12-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED7]], align 8 // CHECK12-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED7]], align 8
// CHECK12-NEXT: [[BLOCK_CAPTURED8:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 // CHECK12-NEXT: [[BLOCK_CAPTURED8:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7
// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP3]], align 8 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP3]], align 8
// CHECK12-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED8]], align 8 // CHECK12-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED8]], align 8
// CHECK12-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* // CHECK12-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()*
// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic* // CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic*
// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 // CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3
// CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8*
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// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32*
// CHECK12-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 // CHECK12-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
// CHECK12-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 // CHECK12-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8
// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK12-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 // CHECK12-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 // CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1
// CHECK12-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 // CHECK12-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP3]], align 8 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP3]], align 8
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1
// CHECK12-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 // CHECK12-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe
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clang/test/OpenMP/parallel_for_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// CHECK1-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]] // CHECK1-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]]
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK1: omp.precond.then: // CHECK1: omp.precond.then:
// CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8
// CHECK1-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8
// CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64
// CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]) // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]])
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK1: omp.dispatch.cond: // CHECK1: omp.dispatch.cond:
// CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8
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// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
// CHECK1: invoke.cont: // CHECK1: invoke.cont:
// CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]]
// CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]] // CHECK1-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]]
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float // CHECK1-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float
// CHECK1-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]] // CHECK1-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]]
// CHECK1-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]] // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]]
// CHECK1-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4
// CHECK1-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]] // CHECK1-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]]
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// CHECK2-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]] // CHECK2-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]]
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK2: omp.precond.then: // CHECK2: omp.precond.then:
// CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8
// CHECK2-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8
// CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64 // CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64
// CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK2-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]) // CHECK2-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]])
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK2: omp.dispatch.cond: // CHECK2: omp.dispatch.cond:
// CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8
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// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
// CHECK2: invoke.cont: // CHECK2: invoke.cont:
// CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float // CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]]
// CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]] // CHECK2-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]]
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float // CHECK2-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float
// CHECK2-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]] // CHECK2-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]]
// CHECK2-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]] // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]]
// CHECK2-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4
// CHECK2-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]] // CHECK2-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]]
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// CHECK3-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]] // CHECK3-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]]
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK3: omp.precond.then: // CHECK3: omp.precond.then:
// CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK3-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8
// CHECK3-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8 // CHECK3-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8
// CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64 // CHECK3-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64
// CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]) // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]])
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK3: omp.dispatch.cond: // CHECK3: omp.dispatch.cond:
// CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8
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// CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
// CHECK3: invoke.cont: // CHECK3: invoke.cont:
// CHECK3-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float // CHECK3-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
// CHECK3-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64 // CHECK3-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]]
// CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]] // CHECK3-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]]
// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float // CHECK3-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float
// CHECK3-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]] // CHECK3-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]]
// CHECK3-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8 // CHECK3-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8
// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK3-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64 // CHECK3-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64
// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]] // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]]
// CHECK3-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4
// CHECK3-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]] // CHECK3-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]]
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// CHECK4-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]] // CHECK4-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]]
// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK4: omp.precond.then: // CHECK4: omp.precond.then:
// CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK4-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8
// CHECK4-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8 // CHECK4-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8
// CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64 // CHECK4-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64
// CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK4-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]) // CHECK4-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]])
// CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK4: omp.dispatch.cond: // CHECK4: omp.dispatch.cond:
// CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8
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// CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
// CHECK4: invoke.cont: // CHECK4: invoke.cont:
// CHECK4-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float // CHECK4-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
// CHECK4-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64 // CHECK4-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]] // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]]
// CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]] // CHECK4-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]]
// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float // CHECK4-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float
// CHECK4-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]] // CHECK4-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]]
// CHECK4-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8 // CHECK4-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8
// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK4-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64 // CHECK4-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64
// CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]] // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]]
// CHECK4-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4 // CHECK4-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4
// CHECK4-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]] // CHECK4-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]]
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// CHECK5-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]], !dbg [[DBG15]] // CHECK5-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]], !dbg [[DBG15]]
// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]], !dbg [[DBG14]] // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]], !dbg [[DBG14]]
// CHECK5: omp.precond.then: // CHECK5: omp.precond.then:
// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG15]] // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG15]]
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]] // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]]
// CHECK5-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] // CHECK5-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]]
// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG15]] // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG15]]
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG15]] // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG15]]
// CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8, !dbg [[DBG14]] // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1, !dbg [[DBG14]]
// CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64, !dbg [[DBG14]] // CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64, !dbg [[DBG14]]
// CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG14]] // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG14]]
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4, !dbg [[DBG14]] // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4, !dbg [[DBG14]]
// CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]), !dbg [[DBG14]] // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]), !dbg [[DBG14]]
// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG14]] // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG14]]
// CHECK5: omp.dispatch.cond: // CHECK5: omp.dispatch.cond:
// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]]
// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]] // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]]
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// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG111:![0-9]+]] // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG111:![0-9]+]]
// CHECK5: invoke.cont: // CHECK5: invoke.cont:
// CHECK5-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG111]] // CHECK5-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG111]]
// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG111]] // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG111]]
// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64, !dbg [[DBG111]] // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64, !dbg [[DBG111]]
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]], !dbg [[DBG111]] // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]], !dbg [[DBG111]]
// CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG111]] // CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG111]]
// CHECK5-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]], !dbg [[DBG111]] // CHECK5-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]], !dbg [[DBG111]]
// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG111]] // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG111]]
// CHECK5-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float, !dbg [[DBG111]] // CHECK5-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float, !dbg [[DBG111]]
// CHECK5-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]], !dbg [[DBG111]] // CHECK5-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]], !dbg [[DBG111]]
// CHECK5-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG111]] // CHECK5-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG111]]
// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG111]] // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG111]]
// CHECK5-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64, !dbg [[DBG111]] // CHECK5-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64, !dbg [[DBG111]]
// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]], !dbg [[DBG111]] // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]], !dbg [[DBG111]]
// CHECK5-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !dbg [[DBG111]] // CHECK5-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !dbg [[DBG111]]
// CHECK5-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]], !dbg [[DBG111]] // CHECK5-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]], !dbg [[DBG111]]
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// CHECK6-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]] // CHECK6-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]]
// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK6: omp.precond.then: // CHECK6: omp.precond.then:
// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8
// CHECK6-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8 // CHECK6-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8
// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64 // CHECK6-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64
// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK6-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]) // CHECK6-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]])
// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK6: omp.dispatch.cond: // CHECK6: omp.dispatch.cond:
// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 // CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8
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// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z3foov() // CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z3foov()
// CHECK6-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float // CHECK6-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float
// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
// CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]] // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]]
// CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK6-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]] // CHECK6-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]]
// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float // CHECK6-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float
// CHECK6-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]] // CHECK6-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]]
// CHECK6-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8 // CHECK6-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8
// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK6-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64 // CHECK6-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64
// CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]] // CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]]
// CHECK6-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4 // CHECK6-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4
// CHECK6-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]] // CHECK6-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]]
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clang/test/OpenMP/parallel_master_codegen.cpp

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// CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK13-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK13-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK13-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK13-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK13-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK13: omp_if.then: // CHECK13: omp_if.then:
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK13-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 // CHECK13-NEXT: store i32 [[INC]], i32* [[CONV]], align 4
// CHECK13-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK13-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK13-NEXT: br label [[OMP_IF_END]] // CHECK13-NEXT: br label [[OMP_IF_END]]
// CHECK13: omp_if.end: // CHECK13: omp_if.end:
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev // CHECK14-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev
// CHECK14-SAME: () #[[ATTR0:[0-9]+]] { // CHECK14-SAME: () #[[ATTR0:[0-9]+]] {
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// CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK14-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK14-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK14-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK14-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK14-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK14: omp_if.then: // CHECK14: omp_if.then:
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK14-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 // CHECK14-NEXT: store i32 [[INC]], i32* [[CONV]], align 4
// CHECK14-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK14-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK14-NEXT: br label [[OMP_IF_END]] // CHECK14-NEXT: br label [[OMP_IF_END]]
// CHECK14: omp_if.end: // CHECK14: omp_if.end:
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev // CHECK17-LABEL: define {{[^@]+}}@_Z36parallel_master_default_firstprivatev
// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
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// CHECK17-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A1]], align 4 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A1]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1
// CHECK17-NEXT: store i32 [[ADD]], i32* [[A1]], align 4 // CHECK17-NEXT: store i32 [[ADD]], i32* [[A1]], align 4
// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP0]], i32 0, i32 1 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP0]], i32 0, i32 1
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4
// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
// CHECK17-NEXT: store i32 [[ADD2]], i32* [[B]], align 4 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[B]], align 4
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 // CHECK17-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
// CHECK17-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[INC]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* @_ZN2St1yE, align 4 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* @_ZN2St1yE, align 4
// CHECK17-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK17-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK17-NEXT: store i32 [[INC3]], i32* @_ZN2St1yE, align 4 // CHECK17-NEXT: store i32 [[INC3]], i32* @_ZN2St1yE, align 4
// CHECK17-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK17-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
// CHECK17-NEXT: br label [[OMP_IF_END]] // CHECK17-NEXT: br label [[OMP_IF_END]]
// CHECK17: omp_if.end: // CHECK17: omp_if.end:
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
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// CHECK18-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A1]], align 4 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A1]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1
// CHECK18-NEXT: store i32 [[ADD]], i32* [[A1]], align 4 // CHECK18-NEXT: store i32 [[ADD]], i32* [[A1]], align 4
// CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP0]], i32 0, i32 1 // CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP0]], i32 0, i32 1
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4
// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
// CHECK18-NEXT: store i32 [[ADD2]], i32* [[B]], align 4 // CHECK18-NEXT: store i32 [[ADD2]], i32* [[B]], align 4
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 // CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
// CHECK18-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[INC]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* @_ZN2St1yE, align 4 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* @_ZN2St1yE, align 4
// CHECK18-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK18-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK18-NEXT: store i32 [[INC3]], i32* @_ZN2St1yE, align 4 // CHECK18-NEXT: store i32 [[INC3]], i32* @_ZN2St1yE, align 4
// CHECK18-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK18-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
// CHECK18-NEXT: br label [[OMP_IF_END]] // CHECK18-NEXT: br label [[OMP_IF_END]]
// CHECK18: omp_if.end: // CHECK18: omp_if.end:
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
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// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK21-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK21-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK21-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK21-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK21-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK21-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK21-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK21-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK21: omp_if.then: // CHECK21: omp_if.then:
// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK21-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 // CHECK21-NEXT: store i32 [[INC]], i32* [[CONV]], align 4
// CHECK21-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK21-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK21-NEXT: br label [[OMP_IF_END]] // CHECK21-NEXT: br label [[OMP_IF_END]]
// CHECK21: omp_if.end: // CHECK21: omp_if.end:
// CHECK21-NEXT: ret void // CHECK21-NEXT: ret void
// //
// //
// CHECK22-LABEL: define {{[^@]+}}@_Z28parallel_master_firstprivatev // CHECK22-LABEL: define {{[^@]+}}@_Z28parallel_master_firstprivatev
// CHECK22-SAME: () #[[ATTR0:[0-9]+]] { // CHECK22-SAME: () #[[ATTR0:[0-9]+]] {
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// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK22-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK22-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK22-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK22-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK22-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK22-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK22-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK22: omp_if.then: // CHECK22: omp_if.then:
// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK22-NEXT: store i32 [[INC]], i32* [[CONV]], align 8 // CHECK22-NEXT: store i32 [[INC]], i32* [[CONV]], align 4
// CHECK22-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK22-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK22-NEXT: br label [[OMP_IF_END]] // CHECK22-NEXT: br label [[OMP_IF_END]]
// CHECK22: omp_if.end: // CHECK22: omp_if.end:
// CHECK22-NEXT: ret void // CHECK22-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv // CHECK25-LABEL: define {{[^@]+}}@_Z22parallel_master_copyinv
// CHECK25-SAME: () #[[ATTR0:[0-9]+]] { // CHECK25-SAME: () #[[ATTR0:[0-9]+]] {
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clang/test/OpenMP/parallel_master_taskloop_codegen.cpp

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// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) // CHECK1-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
// CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 4 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 4
// CHECK1-NEXT: [[TMP9:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP8]] to i32* // CHECK1-NEXT: [[TMP9:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP8]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[TMP9]], align 8 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[TMP9]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5
// CHECK1-NEXT: store i64 0, i64* [[TMP10]], align 8 // CHECK1-NEXT: store i64 0, i64* [[TMP10]], align 8
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// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*)) // CHECK1-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*))
// CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1* // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1*
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5
// CHECK1-NEXT: store i64 0, i64* [[TMP8]], align 8 // CHECK1-NEXT: store i64 0, i64* [[TMP8]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 6 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 6
// CHECK1-NEXT: store i64 9, i64* [[TMP9]], align 8 // CHECK1-NEXT: store i64 9, i64* [[TMP9]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 7 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 7
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// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK1-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 // CHECK1-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
// CHECK1-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 0
// CHECK1-NEXT: store i32* [[TMP0]], i32** [[TMP6]], align 8 // CHECK1-NEXT: store i32* [[TMP0]], i32** [[TMP6]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 1 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK1-NEXT: store i8*** [[TMP1]], i8**** [[TMP7]], align 8 // CHECK1-NEXT: store i8*** [[TMP1]], i8**** [[TMP7]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK1-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_6]], align 4 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_6]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i8**, i8*** [[TMP1]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i8**, i8*** [[TMP1]], align 8
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
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// CHECK1-NEXT: store i64 [[SUB17]], i64* [[DOTCAPTURE_EXPR_11]], align 8 // CHECK1-NEXT: store i64 [[SUB17]], i64* [[DOTCAPTURE_EXPR_11]], align 8
// CHECK1-NEXT: [[TMP19:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i64 80, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..7 to i32 (i32, i8*)*)) // CHECK1-NEXT: [[TMP19:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i64 80, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..7 to i32 (i32, i8*)*))
// CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to %struct.kmp_task_t_with_privates.3* // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to %struct.kmp_task_t_with_privates.3*
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP20]], i32 0, i32 0 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP20]], i32 0, i32 0
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 0 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 0
// CHECK1-NEXT: [[TMP23:%.*]] = load i8*, i8** [[TMP22]], align 8 // CHECK1-NEXT: [[TMP23:%.*]] = load i8*, i8** [[TMP22]], align 8
// CHECK1-NEXT: [[TMP24:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8* // CHECK1-NEXT: [[TMP24:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP23]], i8* align 8 [[TMP24]], i64 16, i1 false) // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP23]], i8* align 8 [[TMP24]], i64 16, i1 false)
// CHECK1-NEXT: [[TMP25:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP25:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP25]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP25]] to i1
// CHECK1-NEXT: [[TMP26:%.*]] = sext i1 [[TOBOOL]] to i32 // CHECK1-NEXT: [[TMP26:%.*]] = sext i1 [[TOBOOL]] to i32
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 5 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 5
// CHECK1-NEXT: store i64 0, i64* [[TMP27]], align 8 // CHECK1-NEXT: store i64 0, i64* [[TMP27]], align 8
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 6 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 6
// CHECK1-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_11]], align 8 // CHECK1-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_11]], align 8
// CHECK1-NEXT: store i64 [[TMP29]], i64* [[TMP28]], align 8 // CHECK1-NEXT: store i64 [[TMP29]], i64* [[TMP28]], align 8
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 7 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 7
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// CHECK1-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 // CHECK1-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
// CHECK1-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[AGG_CAPTURED]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[AGG_CAPTURED]], i32 0, i32 0
// CHECK1-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8 // CHECK1-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[AGG_CAPTURED]], i32 0, i32 1 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK1-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8 // CHECK1-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8
// CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK1-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
// CHECK1-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8 // CHECK1-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
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// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) // CHECK2-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
// CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 4 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 4
// CHECK2-NEXT: [[TMP9:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP8]] to i32* // CHECK2-NEXT: [[TMP9:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP8]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[TMP9]], align 8 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[TMP9]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5
// CHECK2-NEXT: store i64 0, i64* [[TMP10]], align 8 // CHECK2-NEXT: store i64 0, i64* [[TMP10]], align 8
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// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*)) // CHECK2-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*))
// CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1* // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1*
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0
// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5
// CHECK2-NEXT: store i64 0, i64* [[TMP8]], align 8 // CHECK2-NEXT: store i64 0, i64* [[TMP8]], align 8
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 6 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 6
// CHECK2-NEXT: store i64 9, i64* [[TMP9]], align 8 // CHECK2-NEXT: store i64 9, i64* [[TMP9]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 7 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 7
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// CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK2-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 // CHECK2-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
// CHECK2-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 0 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 0
// CHECK2-NEXT: store i32* [[TMP0]], i32** [[TMP6]], align 8 // CHECK2-NEXT: store i32* [[TMP0]], i32** [[TMP6]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 1 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK2-NEXT: store i8*** [[TMP1]], i8**** [[TMP7]], align 8 // CHECK2-NEXT: store i8*** [[TMP1]], i8**** [[TMP7]], align 8
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK2-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_6]], align 4 // CHECK2-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_6]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i8**, i8*** [[TMP1]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i8**, i8*** [[TMP1]], align 8
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
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// CHECK2-NEXT: store i64 [[SUB17]], i64* [[DOTCAPTURE_EXPR_11]], align 8 // CHECK2-NEXT: store i64 [[SUB17]], i64* [[DOTCAPTURE_EXPR_11]], align 8
// CHECK2-NEXT: [[TMP19:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i64 80, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..7 to i32 (i32, i8*)*)) // CHECK2-NEXT: [[TMP19:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 1, i64 80, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..7 to i32 (i32, i8*)*))
// CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to %struct.kmp_task_t_with_privates.3* // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to %struct.kmp_task_t_with_privates.3*
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP20]], i32 0, i32 0 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP20]], i32 0, i32 0
// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 0 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 0
// CHECK2-NEXT: [[TMP23:%.*]] = load i8*, i8** [[TMP22]], align 8 // CHECK2-NEXT: [[TMP23:%.*]] = load i8*, i8** [[TMP22]], align 8
// CHECK2-NEXT: [[TMP24:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8* // CHECK2-NEXT: [[TMP24:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP23]], i8* align 8 [[TMP24]], i64 16, i1 false) // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP23]], i8* align 8 [[TMP24]], i64 16, i1 false)
// CHECK2-NEXT: [[TMP25:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP25:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP25]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP25]] to i1
// CHECK2-NEXT: [[TMP26:%.*]] = sext i1 [[TOBOOL]] to i32 // CHECK2-NEXT: [[TMP26:%.*]] = sext i1 [[TOBOOL]] to i32
// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 5 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 5
// CHECK2-NEXT: store i64 0, i64* [[TMP27]], align 8 // CHECK2-NEXT: store i64 0, i64* [[TMP27]], align 8
// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 6 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 6
// CHECK2-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_11]], align 8 // CHECK2-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_11]], align 8
// CHECK2-NEXT: store i64 [[TMP29]], i64* [[TMP28]], align 8 // CHECK2-NEXT: store i64 [[TMP29]], i64* [[TMP28]], align 8
// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 7 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 7
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// CHECK2-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 // CHECK2-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
// CHECK2-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[AGG_CAPTURED]], i32 0, i32 0 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[AGG_CAPTURED]], i32 0, i32 0
// CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8 // CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[AGG_CAPTURED]], i32 0, i32 1 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8 // CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8
// CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK2-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
// CHECK2-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8 // CHECK2-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
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clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp

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// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) // CHECK1-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
// CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 4 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 4
// CHECK1-NEXT: [[TMP9:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP8]] to i32* // CHECK1-NEXT: [[TMP9:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP8]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[TMP9]], align 8 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[TMP9]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5
// CHECK1-NEXT: store i64 0, i64* [[TMP10]], align 8 // CHECK1-NEXT: store i64 0, i64* [[TMP10]], align 8
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// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*)) // CHECK1-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*))
// CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1* // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1*
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5
// CHECK1-NEXT: store i64 0, i64* [[TMP8]], align 8 // CHECK1-NEXT: store i64 0, i64* [[TMP8]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 6 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 6
// CHECK1-NEXT: store i64 9, i64* [[TMP9]], align 8 // CHECK1-NEXT: store i64 9, i64* [[TMP9]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 7 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 7
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// CHECK1-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 0
// CHECK1-NEXT: store i32* [[TMP0]], i32** [[TMP7]], align 8 // CHECK1-NEXT: store i32* [[TMP0]], i32** [[TMP7]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 1 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK1-NEXT: store i32* [[TMP1]], i32** [[TMP8]], align 8 // CHECK1-NEXT: store i32* [[TMP1]], i32** [[TMP8]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 2 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 2
// CHECK1-NEXT: store i8*** [[TMP2]], i8**** [[TMP9]], align 8 // CHECK1-NEXT: store i8*** [[TMP2]], i8**** [[TMP9]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTCAPTURE_EXPR_6]], align 4 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTCAPTURE_EXPR_6]], align 4
// CHECK1-NEXT: [[TMP13:%.*]] = load i8**, i8*** [[TMP2]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = load i8**, i8*** [[TMP2]], align 8
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
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// CHECK1-NEXT: [[TMP21:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 1, i64 88, i64 24, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..7 to i32 (i32, i8*)*)) // CHECK1-NEXT: [[TMP21:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 1, i64 88, i64 24, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..7 to i32 (i32, i8*)*))
// CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8* [[TMP21]] to %struct.kmp_task_t_with_privates.3* // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8* [[TMP21]] to %struct.kmp_task_t_with_privates.3*
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP22]], i32 0, i32 0 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP22]], i32 0, i32 0
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 0 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 0
// CHECK1-NEXT: [[TMP25:%.*]] = load i8*, i8** [[TMP24]], align 8 // CHECK1-NEXT: [[TMP25:%.*]] = load i8*, i8** [[TMP24]], align 8
// CHECK1-NEXT: [[TMP26:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8* // CHECK1-NEXT: [[TMP26:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP25]], i8* align 8 [[TMP26]], i64 24, i1 false) // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP25]], i8* align 8 [[TMP26]], i64 24, i1 false)
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], %struct.kmp_task_t_with_privates.3* [[TMP22]], i32 0, i32 1 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], %struct.kmp_task_t_with_privates.3* [[TMP22]], i32 0, i32 1
// CHECK1-NEXT: [[TMP28:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP28:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP28]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP28]] to i1
// CHECK1-NEXT: [[TMP29:%.*]] = sext i1 [[TOBOOL]] to i32 // CHECK1-NEXT: [[TMP29:%.*]] = sext i1 [[TOBOOL]] to i32
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 5 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 5
// CHECK1-NEXT: store i64 0, i64* [[TMP30]], align 8 // CHECK1-NEXT: store i64 0, i64* [[TMP30]], align 8
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 6 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 6
// CHECK1-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_11]], align 8 // CHECK1-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_11]], align 8
// CHECK1-NEXT: store i64 [[TMP32]], i64* [[TMP31]], align 8 // CHECK1-NEXT: store i64 [[TMP32]], i64* [[TMP31]], align 8
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 7 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 7
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// CHECK1-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 // CHECK1-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
// CHECK1-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 0
// CHECK1-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8 // CHECK1-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 1 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK1-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8 // CHECK1-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8
// CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK1-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
// CHECK1-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8 // CHECK1-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
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// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) // CHECK2-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
// CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 4 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 4
// CHECK2-NEXT: [[TMP9:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP8]] to i32* // CHECK2-NEXT: [[TMP9:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP8]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[TMP9]], align 8 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[TMP9]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5
// CHECK2-NEXT: store i64 0, i64* [[TMP10]], align 8 // CHECK2-NEXT: store i64 0, i64* [[TMP10]], align 8
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// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*)) // CHECK2-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*))
// CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1* // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1*
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0
// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5
// CHECK2-NEXT: store i64 0, i64* [[TMP8]], align 8 // CHECK2-NEXT: store i64 0, i64* [[TMP8]], align 8
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 6 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 6
// CHECK2-NEXT: store i64 9, i64* [[TMP9]], align 8 // CHECK2-NEXT: store i64 9, i64* [[TMP9]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 7 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 7
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// CHECK2-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 0
// CHECK2-NEXT: store i32* [[TMP0]], i32** [[TMP7]], align 8 // CHECK2-NEXT: store i32* [[TMP0]], i32** [[TMP7]], align 8
// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 1 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP8]], align 8 // CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP8]], align 8
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 2 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 2
// CHECK2-NEXT: store i8*** [[TMP2]], i8**** [[TMP9]], align 8 // CHECK2-NEXT: store i8*** [[TMP2]], i8**** [[TMP9]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTCAPTURE_EXPR_6]], align 4 // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTCAPTURE_EXPR_6]], align 4
// CHECK2-NEXT: [[TMP13:%.*]] = load i8**, i8*** [[TMP2]], align 8 // CHECK2-NEXT: [[TMP13:%.*]] = load i8**, i8*** [[TMP2]], align 8
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
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// CHECK2-NEXT: [[TMP21:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 1, i64 88, i64 24, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..7 to i32 (i32, i8*)*)) // CHECK2-NEXT: [[TMP21:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 1, i64 88, i64 24, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..7 to i32 (i32, i8*)*))
// CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8* [[TMP21]] to %struct.kmp_task_t_with_privates.3* // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8* [[TMP21]] to %struct.kmp_task_t_with_privates.3*
// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP22]], i32 0, i32 0 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP22]], i32 0, i32 0
// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 0 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 0
// CHECK2-NEXT: [[TMP25:%.*]] = load i8*, i8** [[TMP24]], align 8 // CHECK2-NEXT: [[TMP25:%.*]] = load i8*, i8** [[TMP24]], align 8
// CHECK2-NEXT: [[TMP26:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8* // CHECK2-NEXT: [[TMP26:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP25]], i8* align 8 [[TMP26]], i64 24, i1 false) // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP25]], i8* align 8 [[TMP26]], i64 24, i1 false)
// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], %struct.kmp_task_t_with_privates.3* [[TMP22]], i32 0, i32 1 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], %struct.kmp_task_t_with_privates.3* [[TMP22]], i32 0, i32 1
// CHECK2-NEXT: [[TMP28:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP28:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP28]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP28]] to i1
// CHECK2-NEXT: [[TMP29:%.*]] = sext i1 [[TOBOOL]] to i32 // CHECK2-NEXT: [[TMP29:%.*]] = sext i1 [[TOBOOL]] to i32
// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 5 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 5
// CHECK2-NEXT: store i64 0, i64* [[TMP30]], align 8 // CHECK2-NEXT: store i64 0, i64* [[TMP30]], align 8
// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 6 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 6
// CHECK2-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_11]], align 8 // CHECK2-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_11]], align 8
// CHECK2-NEXT: store i64 [[TMP32]], i64* [[TMP31]], align 8 // CHECK2-NEXT: store i64 [[TMP32]], i64* [[TMP31]], align 8
// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 7 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 7
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// CHECK2-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 // CHECK2-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
// CHECK2-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 0 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 0
// CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8 // CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 1 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8 // CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8
// CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK2-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
// CHECK2-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8 // CHECK2-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
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// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK3-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) // CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
// CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 4 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 4
// CHECK3-NEXT: [[TMP9:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP8]] to i32* // CHECK3-NEXT: [[TMP9:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP8]] to i32*
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[TMP9]], align 8 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[TMP9]], align 8
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5
// CHECK3-NEXT: store i64 0, i64* [[TMP10]], align 8 // CHECK3-NEXT: store i64 0, i64* [[TMP10]], align 8
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// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*)) // CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*))
// CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1* // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1*
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5
// CHECK3-NEXT: store i64 0, i64* [[TMP8]], align 8 // CHECK3-NEXT: store i64 0, i64* [[TMP8]], align 8
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 6 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 6
// CHECK3-NEXT: store i64 9, i64* [[TMP9]], align 8 // CHECK3-NEXT: store i64 9, i64* [[TMP9]], align 8
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 7 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 7
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// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 0
// CHECK3-NEXT: store i32* [[TMP0]], i32** [[TMP7]], align 8 // CHECK3-NEXT: store i32* [[TMP0]], i32** [[TMP7]], align 8
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 1 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK3-NEXT: store i32* [[TMP1]], i32** [[TMP8]], align 8 // CHECK3-NEXT: store i32* [[TMP1]], i32** [[TMP8]], align 8
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 2 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 2
// CHECK3-NEXT: store i8*** [[TMP2]], i8**** [[TMP9]], align 8 // CHECK3-NEXT: store i8*** [[TMP2]], i8**** [[TMP9]], align 8
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 3 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 3
// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[TMP10]], align 8 // CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[TMP10]], align 8
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK3-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK3-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR_6]], align 4 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR_6]], align 4
// CHECK3-NEXT: [[TMP15:%.*]] = load i8**, i8*** [[TMP2]], align 8 // CHECK3-NEXT: [[TMP15:%.*]] = load i8**, i8*** [[TMP2]], align 8
// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
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// CHECK3-NEXT: [[TMP23:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 1, i64 88, i64 32, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..7 to i32 (i32, i8*)*)) // CHECK3-NEXT: [[TMP23:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 1, i64 88, i64 32, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..7 to i32 (i32, i8*)*))
// CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8* [[TMP23]] to %struct.kmp_task_t_with_privates.3* // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8* [[TMP23]] to %struct.kmp_task_t_with_privates.3*
// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP24]], i32 0, i32 0 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP24]], i32 0, i32 0
// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 0 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 0
// CHECK3-NEXT: [[TMP27:%.*]] = load i8*, i8** [[TMP26]], align 8 // CHECK3-NEXT: [[TMP27:%.*]] = load i8*, i8** [[TMP26]], align 8
// CHECK3-NEXT: [[TMP28:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8* // CHECK3-NEXT: [[TMP28:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8*
// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP27]], i8* align 8 [[TMP28]], i64 32, i1 false) // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP27]], i8* align 8 [[TMP28]], i64 32, i1 false)
// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], %struct.kmp_task_t_with_privates.3* [[TMP24]], i32 0, i32 1 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], %struct.kmp_task_t_with_privates.3* [[TMP24]], i32 0, i32 1
// CHECK3-NEXT: [[TMP30:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP30:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL18:%.*]] = trunc i8 [[TMP30]] to i1 // CHECK3-NEXT: [[TOBOOL18:%.*]] = trunc i8 [[TMP30]] to i1
// CHECK3-NEXT: [[TMP31:%.*]] = sext i1 [[TOBOOL18]] to i32 // CHECK3-NEXT: [[TMP31:%.*]] = sext i1 [[TOBOOL18]] to i32
// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 5 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 5
// CHECK3-NEXT: store i64 0, i64* [[TMP32]], align 8 // CHECK3-NEXT: store i64 0, i64* [[TMP32]], align 8
// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 6 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 6
// CHECK3-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_11]], align 8 // CHECK3-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_11]], align 8
// CHECK3-NEXT: store i64 [[TMP34]], i64* [[TMP33]], align 8 // CHECK3-NEXT: store i64 [[TMP34]], i64* [[TMP33]], align 8
// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 7 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 7
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// CHECK3-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 // CHECK3-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
// CHECK3-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK3-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 0 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 0
// CHECK3-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8 // CHECK3-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 1 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK3-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8 // CHECK3-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8
// CHECK3-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK3-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK3-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
// CHECK3-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8 // CHECK3-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0
// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK3-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK3-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
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// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK4-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) // CHECK4-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
// CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 4 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 4
// CHECK4-NEXT: [[TMP9:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP8]] to i32* // CHECK4-NEXT: [[TMP9:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP8]] to i32*
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[TMP9]], align 8 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[TMP9]], align 8
// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5
// CHECK4-NEXT: store i64 0, i64* [[TMP10]], align 8 // CHECK4-NEXT: store i64 0, i64* [[TMP10]], align 8
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// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*)) // CHECK4-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*))
// CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1* // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1*
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0
// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 5
// CHECK4-NEXT: store i64 0, i64* [[TMP8]], align 8 // CHECK4-NEXT: store i64 0, i64* [[TMP8]], align 8
// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 6 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 6
// CHECK4-NEXT: store i64 9, i64* [[TMP9]], align 8 // CHECK4-NEXT: store i64 9, i64* [[TMP9]], align 8
// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 7 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP7]], i32 0, i32 7
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// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 0 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 0
// CHECK4-NEXT: store i32* [[TMP0]], i32** [[TMP7]], align 8 // CHECK4-NEXT: store i32* [[TMP0]], i32** [[TMP7]], align 8
// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 1 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK4-NEXT: store i32* [[TMP1]], i32** [[TMP8]], align 8 // CHECK4-NEXT: store i32* [[TMP1]], i32** [[TMP8]], align 8
// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 2 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 2
// CHECK4-NEXT: store i8*** [[TMP2]], i8**** [[TMP9]], align 8 // CHECK4-NEXT: store i8*** [[TMP2]], i8**** [[TMP9]], align 8
// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 3 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 3
// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[TMP10]], align 8 // CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[TMP10]], align 8
// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK4-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK4-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR_6]], align 4 // CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR_6]], align 4
// CHECK4-NEXT: [[TMP15:%.*]] = load i8**, i8*** [[TMP2]], align 8 // CHECK4-NEXT: [[TMP15:%.*]] = load i8**, i8*** [[TMP2]], align 8
// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
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// CHECK4-NEXT: [[TMP23:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 1, i64 88, i64 32, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..7 to i32 (i32, i8*)*)) // CHECK4-NEXT: [[TMP23:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 1, i64 88, i64 32, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.3*)* @.omp_task_entry..7 to i32 (i32, i8*)*))
// CHECK4-NEXT: [[TMP24:%.*]] = bitcast i8* [[TMP23]] to %struct.kmp_task_t_with_privates.3* // CHECK4-NEXT: [[TMP24:%.*]] = bitcast i8* [[TMP23]] to %struct.kmp_task_t_with_privates.3*
// CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP24]], i32 0, i32 0 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP24]], i32 0, i32 0
// CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 0 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 0
// CHECK4-NEXT: [[TMP27:%.*]] = load i8*, i8** [[TMP26]], align 8 // CHECK4-NEXT: [[TMP27:%.*]] = load i8*, i8** [[TMP26]], align 8
// CHECK4-NEXT: [[TMP28:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8* // CHECK4-NEXT: [[TMP28:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8*
// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP27]], i8* align 8 [[TMP28]], i64 32, i1 false) // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP27]], i8* align 8 [[TMP28]], i64 32, i1 false)
// CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], %struct.kmp_task_t_with_privates.3* [[TMP24]], i32 0, i32 1 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], %struct.kmp_task_t_with_privates.3* [[TMP24]], i32 0, i32 1
// CHECK4-NEXT: [[TMP30:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP30:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL18:%.*]] = trunc i8 [[TMP30]] to i1 // CHECK4-NEXT: [[TOBOOL18:%.*]] = trunc i8 [[TMP30]] to i1
// CHECK4-NEXT: [[TMP31:%.*]] = sext i1 [[TOBOOL18]] to i32 // CHECK4-NEXT: [[TMP31:%.*]] = sext i1 [[TOBOOL18]] to i32
// CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 5 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 5
// CHECK4-NEXT: store i64 0, i64* [[TMP32]], align 8 // CHECK4-NEXT: store i64 0, i64* [[TMP32]], align 8
// CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 6 // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 6
// CHECK4-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_11]], align 8 // CHECK4-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_11]], align 8
// CHECK4-NEXT: store i64 [[TMP34]], i64* [[TMP33]], align 8 // CHECK4-NEXT: store i64 [[TMP34]], i64* [[TMP33]], align 8
// CHECK4-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 7 // CHECK4-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 7
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// CHECK4-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 // CHECK4-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
// CHECK4-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK4-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 0 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 0
// CHECK4-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8 // CHECK4-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 1 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK4-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8 // CHECK4-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8
// CHECK4-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK4-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK4-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
// CHECK4-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8 // CHECK4-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0
// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK4-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK4-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
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clang/test/OpenMP/single_codegen.cpp

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// CHECK1-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK1-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK1-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 // CHECK1-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
// CHECK1-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP4]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP4]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK1-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4 // CHECK1-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1
// CHECK1-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1
// CHECK1-NEXT: store i32 [[DIV]], i32* [[TMP10]], align 4 // CHECK1-NEXT: store i32 [[DIV]], i32* [[TMP10]], align 4
// CHECK1-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK1-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1-NEXT: br label [[OMP_IF_END]]
// CHECK1: omp_if.end: // CHECK1: omp_if.end:
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// CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK2-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 // CHECK2-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
// CHECK2-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP4]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP4]], align 8
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK2-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4 // CHECK2-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1 // CHECK2-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1
// CHECK2-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1
// CHECK2-NEXT: store i32 [[DIV]], i32* [[TMP10]], align 4 // CHECK2-NEXT: store i32 [[DIV]], i32* [[TMP10]], align 4
// CHECK2-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK2-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK2-NEXT: br label [[OMP_IF_END]] // CHECK2-NEXT: br label [[OMP_IF_END]]
// CHECK2: omp_if.end: // CHECK2: omp_if.end:
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// CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK3-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 // CHECK3-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
// CHECK3-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK3-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP4]], align 8 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP4]], align 8
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK3-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4 // CHECK3-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1
// CHECK3-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 // CHECK3-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK3-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8 // CHECK3-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1
// CHECK3-NEXT: store i32 [[DIV]], i32* [[TMP10]], align 4 // CHECK3-NEXT: store i32 [[DIV]], i32* [[TMP10]], align 4
// CHECK3-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK3-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3-NEXT: br label [[OMP_IF_END]]
// CHECK3: omp_if.end: // CHECK3: omp_if.end:
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// CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK4-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 // CHECK4-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
// CHECK4-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK4-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP4]], align 8 // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP4]], align 8
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK4-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4 // CHECK4-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1
// CHECK4-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 // CHECK4-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8 // CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1
// CHECK4-NEXT: store i32 [[DIV]], i32* [[TMP10]], align 4 // CHECK4-NEXT: store i32 [[DIV]], i32* [[TMP10]], align 4
// CHECK4-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) // CHECK4-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COPYPRIVATE_DID_IT]], align 4
// CHECK4-NEXT: br label [[OMP_IF_END]] // CHECK4-NEXT: br label [[OMP_IF_END]]
// CHECK4: omp_if.end: // CHECK4: omp_if.end:
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// CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB28:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG166]] // CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB28:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG166]]
// CHECK5-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG166]] // CHECK5-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG166]]
// CHECK5-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG166]] // CHECK5-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG166]]
// CHECK5: omp_if.then: // CHECK5: omp_if.then:
// CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP4]], align 8, !dbg [[DBG165]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP4]], align 8, !dbg [[DBG165]]
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4, !dbg [[DBG168:![0-9]+]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4, !dbg [[DBG168:![0-9]+]]
// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1, !dbg [[DBG168]] // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1, !dbg [[DBG168]]
// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4, !dbg [[DBG168]] // CHECK5-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4, !dbg [[DBG168]]
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 8, !dbg [[DBG169:![0-9]+]] // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 4, !dbg [[DBG169:![0-9]+]]
// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1, !dbg [[DBG169]] // CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1, !dbg [[DBG169]]
// CHECK5-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8, !dbg [[DBG169]] // CHECK5-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4, !dbg [[DBG169]]
// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8, !dbg [[DBG167]] // CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8, !dbg [[DBG167]]
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4, !dbg [[DBG170:![0-9]+]] // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4, !dbg [[DBG170:![0-9]+]]
// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1, !dbg [[DBG170]] // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1, !dbg [[DBG170]]
// CHECK5-NEXT: store i32 [[DIV]], i32* [[TMP10]], align 4, !dbg [[DBG170]] // CHECK5-NEXT: store i32 [[DIV]], i32* [[TMP10]], align 4, !dbg [[DBG170]]
// CHECK5-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB28]], i32 [[TMP4]]), !dbg [[DBG168]] // CHECK5-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB28]], i32 [[TMP4]]), !dbg [[DBG168]]
// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG168]] // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG168]]
// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG168]] // CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG168]]
// CHECK5: omp_if.end: // CHECK5: omp_if.end:
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clang/test/OpenMP/target_codegen_global_capture.cpp

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// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double* // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float* // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
// CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8 // CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
// CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00 // CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
// CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8 // CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
// CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float // CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
// CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 8 // CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
// CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
// CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: land.lhs.true: // CHECK1: land.lhs.true:
// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
// CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
// CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 // CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] // CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK1: land.lhs.true17: // CHECK1: land.lhs.true17:
// CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
// CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double // CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
// CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 // CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.else: // CHECK1: omp_if.else:
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
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// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double* // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float* // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
// CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8 // CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
// CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00 // CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
// CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8 // CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
// CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float // CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
// CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 8 // CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
// CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
// CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: land.lhs.true: // CHECK1: land.lhs.true:
// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
// CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
// CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 // CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] // CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK1: land.lhs.true17: // CHECK1: land.lhs.true17:
// CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
// CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double // CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
// CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 // CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.else: // CHECK1: omp_if.else:
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
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// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double* // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float* // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
// CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8 // CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
// CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00 // CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
// CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8 // CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
// CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float // CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
// CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 8 // CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
// CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
// CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: land.lhs.true: // CHECK1: land.lhs.true:
// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
// CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
// CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 // CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] // CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK1: land.lhs.true17: // CHECK1: land.lhs.true17:
// CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
// CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double // CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
// CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 // CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.else: // CHECK1: omp_if.else:
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
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// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double* // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float* // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32 // CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 // CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
// CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8 // CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK2-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
// CHECK2-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00 // CHECK2-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
// CHECK2-NEXT: store double [[ADD11]], double* [[CONV1]], align 8 // CHECK2-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double // CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
// CHECK2-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 // CHECK2-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK2-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float // CHECK2-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
// CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 8 // CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
// CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00 // CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
// CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: land.lhs.true: // CHECK2: land.lhs.true:
// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
// CHECK2-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32 // CHECK2-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
// CHECK2-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 // CHECK2-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK2-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] // CHECK2-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK2: land.lhs.true17: // CHECK2: land.lhs.true17:
// CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
// CHECK2-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double // CHECK2-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
// CHECK2-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 // CHECK2-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] // CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.else: // CHECK2: omp_if.else:
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
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// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double* // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float* // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32 // CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 // CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
// CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8 // CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK2-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
// CHECK2-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00 // CHECK2-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
// CHECK2-NEXT: store double [[ADD11]], double* [[CONV1]], align 8 // CHECK2-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double // CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
// CHECK2-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 // CHECK2-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK2-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float // CHECK2-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
// CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 8 // CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
// CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00 // CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
// CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: land.lhs.true: // CHECK2: land.lhs.true:
// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
// CHECK2-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32 // CHECK2-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
// CHECK2-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 // CHECK2-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK2-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] // CHECK2-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK2: land.lhs.true17: // CHECK2: land.lhs.true17:
// CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
// CHECK2-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double // CHECK2-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
// CHECK2-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 // CHECK2-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] // CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.else: // CHECK2: omp_if.else:
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
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// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double* // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float* // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32 // CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 // CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
// CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8 // CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK2-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
// CHECK2-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00 // CHECK2-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
// CHECK2-NEXT: store double [[ADD11]], double* [[CONV1]], align 8 // CHECK2-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double // CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
// CHECK2-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 // CHECK2-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK2-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float // CHECK2-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
// CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 8 // CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
// CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00 // CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
// CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: land.lhs.true: // CHECK2: land.lhs.true:
// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
// CHECK2-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32 // CHECK2-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
// CHECK2-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 // CHECK2-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK2-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] // CHECK2-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK2: land.lhs.true17: // CHECK2: land.lhs.true17:
// CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
// CHECK2-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double // CHECK2-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
// CHECK2-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 // CHECK2-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] // CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.else: // CHECK2: omp_if.else:
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
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// CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
// CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float* // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
// CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
// CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8 // CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8
// CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
// CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8 // CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8
// CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8 // CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
// CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8 // CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8
// CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32 // CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
// CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8 // CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
// CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00 // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
// CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8 // CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8
// CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
// CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double // CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
// CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float // CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
// CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4 // CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
// CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8 // CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
// CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
// CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: land.lhs.true: // CHECK3: land.lhs.true:
// CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
// CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 // CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] // CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK3: land.lhs.true17: // CHECK3: land.lhs.true17:
// CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
// CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double // CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
// CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 // CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] // CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
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// CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
// CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float* // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
// CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
// CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8 // CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8
// CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
// CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8 // CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8
// CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8 // CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
// CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8 // CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8
// CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32 // CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
// CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8 // CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
// CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00 // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
// CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8 // CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8
// CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
// CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double // CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
// CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float // CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
// CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4 // CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
// CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8 // CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
// CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
// CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: land.lhs.true: // CHECK3: land.lhs.true:
// CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
// CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 // CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] // CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK3: land.lhs.true17: // CHECK3: land.lhs.true17:
// CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
// CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double // CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
// CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 // CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] // CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
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// CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
// CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float* // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
// CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
// CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8 // CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8
// CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
// CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8 // CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8
// CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8 // CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
// CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8 // CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8
// CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32 // CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
// CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8 // CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
// CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00 // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
// CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8 // CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8
// CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
// CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double // CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
// CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float // CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
// CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4 // CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
// CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8 // CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
// CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
// CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: land.lhs.true: // CHECK3: land.lhs.true:
// CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
// CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 // CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] // CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK3: land.lhs.true17: // CHECK3: land.lhs.true17:
// CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
// CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double // CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
// CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 // CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] // CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
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// CHECK4-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
// CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float* // CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
// CHECK4-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
// CHECK4-NEXT: store double [[TMP4]], double* [[GB6]], align 8 // CHECK4-NEXT: store double [[TMP4]], double* [[GB6]], align 8
// CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
// CHECK4-NEXT: store double [[TMP5]], double* [[GC7]], align 8 // CHECK4-NEXT: store double [[TMP5]], double* [[GC7]], align 8
// CHECK4-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8 // CHECK4-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
// CHECK4-NEXT: store double [[TMP6]], double* [[GD8]], align 8 // CHECK4-NEXT: store double [[TMP6]], double* [[GD8]], align 8
// CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32 // CHECK4-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK4-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 // CHECK4-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
// CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8 // CHECK4-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
// CHECK4-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00 // CHECK4-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
// CHECK4-NEXT: store double [[ADD11]], double* [[GB6]], align 8 // CHECK4-NEXT: store double [[ADD11]], double* [[GB6]], align 8
// CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
// CHECK4-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double // CHECK4-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
// CHECK4-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 // CHECK4-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK4-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float // CHECK4-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
// CHECK4-NEXT: store float [[CONV14]], float* [[CONV1]], align 4 // CHECK4-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
// CHECK4-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8 // CHECK4-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
// CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00 // CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
// CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: land.lhs.true: // CHECK4: land.lhs.true:
// CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK4-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32 // CHECK4-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
// CHECK4-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 // CHECK4-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK4-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] // CHECK4-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK4: land.lhs.true17: // CHECK4: land.lhs.true17:
// CHECK4-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4 // CHECK4-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
// CHECK4-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double // CHECK4-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
// CHECK4-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 // CHECK4-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK4-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] // CHECK4-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
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// CHECK4-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
// CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float* // CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
// CHECK4-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
// CHECK4-NEXT: store double [[TMP4]], double* [[GB6]], align 8 // CHECK4-NEXT: store double [[TMP4]], double* [[GB6]], align 8
// CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
// CHECK4-NEXT: store double [[TMP5]], double* [[GC7]], align 8 // CHECK4-NEXT: store double [[TMP5]], double* [[GC7]], align 8
// CHECK4-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8 // CHECK4-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
// CHECK4-NEXT: store double [[TMP6]], double* [[GD8]], align 8 // CHECK4-NEXT: store double [[TMP6]], double* [[GD8]], align 8
// CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32 // CHECK4-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK4-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 // CHECK4-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
// CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8 // CHECK4-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
// CHECK4-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00 // CHECK4-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
// CHECK4-NEXT: store double [[ADD11]], double* [[GB6]], align 8 // CHECK4-NEXT: store double [[ADD11]], double* [[GB6]], align 8
// CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
// CHECK4-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double // CHECK4-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
// CHECK4-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 // CHECK4-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK4-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float // CHECK4-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
// CHECK4-NEXT: store float [[CONV14]], float* [[CONV1]], align 4 // CHECK4-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
// CHECK4-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8 // CHECK4-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
// CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00 // CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
// CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: land.lhs.true: // CHECK4: land.lhs.true:
// CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK4-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32 // CHECK4-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
// CHECK4-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 // CHECK4-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK4-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] // CHECK4-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK4: land.lhs.true17: // CHECK4: land.lhs.true17:
// CHECK4-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4 // CHECK4-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
// CHECK4-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double // CHECK4-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
// CHECK4-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 // CHECK4-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK4-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] // CHECK4-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
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// CHECK4-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
// CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float* // CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
// CHECK4-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
// CHECK4-NEXT: store double [[TMP4]], double* [[GB6]], align 8 // CHECK4-NEXT: store double [[TMP4]], double* [[GB6]], align 8
// CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
// CHECK4-NEXT: store double [[TMP5]], double* [[GC7]], align 8 // CHECK4-NEXT: store double [[TMP5]], double* [[GC7]], align 8
// CHECK4-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8 // CHECK4-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
// CHECK4-NEXT: store double [[TMP6]], double* [[GD8]], align 8 // CHECK4-NEXT: store double [[TMP6]], double* [[GD8]], align 8
// CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32 // CHECK4-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK4-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 // CHECK4-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
// CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8 // CHECK4-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
// CHECK4-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00 // CHECK4-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
// CHECK4-NEXT: store double [[ADD11]], double* [[GB6]], align 8 // CHECK4-NEXT: store double [[ADD11]], double* [[GB6]], align 8
// CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
// CHECK4-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double // CHECK4-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
// CHECK4-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00 // CHECK4-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK4-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float // CHECK4-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
// CHECK4-NEXT: store float [[CONV14]], float* [[CONV1]], align 4 // CHECK4-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
// CHECK4-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8 // CHECK4-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
// CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00 // CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
// CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: land.lhs.true: // CHECK4: land.lhs.true:
// CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK4-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32 // CHECK4-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
// CHECK4-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0 // CHECK4-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK4-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]] // CHECK4-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK4: land.lhs.true17: // CHECK4: land.lhs.true17:
// CHECK4-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4 // CHECK4-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
// CHECK4-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double // CHECK4-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
// CHECK4-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00 // CHECK4-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK4-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]] // CHECK4-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
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clang/test/OpenMP/target_parallel_codegen.cpp

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// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK1-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK1-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK1-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK1: .cancel.exit: // CHECK1: .cancel.exit:
// CHECK1-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK1-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK1-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK1-NEXT: br label [[DOTCANCEL_CONTINUE]]
// CHECK1: .cancel.continue: // CHECK1: .cancel.continue:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
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// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK2-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK2-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK2-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK2-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK2: .cancel.exit: // CHECK2: .cancel.exit:
// CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK2-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK2-NEXT: br label [[DOTCANCEL_CONTINUE]]
// CHECK2: .cancel.continue: // CHECK2: .cancel.continue:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
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// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK2-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK2-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK2-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK2-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK2-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK2-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK2-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK2-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK2-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK2-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK2-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK2-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK2-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK3-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK3-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK3-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK3: .cancel.exit: // CHECK3: .cancel.exit:
// CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK3-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK3-NEXT: br label [[DOTCANCEL_CONTINUE]]
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// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// //
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK4-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK4-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK4-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK4-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK4-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK4: .cancel.exit: // CHECK4: .cancel.exit:
// CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK4-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK4-NEXT: br label [[DOTCANCEL_CONTINUE]]
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// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK4-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK4-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK4-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK4-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK4-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK4-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK4-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK9-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK9-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK9-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK9-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK9-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK9: .cancel.exit: // CHECK9: .cancel.exit:
// CHECK9-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK9-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK9-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK9-NEXT: br label [[DOTCANCEL_CONTINUE]]
// CHECK9: .cancel.continue: // CHECK9: .cancel.continue:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK9-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK9-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK9-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK9-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK9-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
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// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK9-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK9-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK9-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
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// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK10-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK10-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK10-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK10-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK10-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK10-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK10: .cancel.exit: // CHECK10: .cancel.exit:
// CHECK10-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK10-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK10-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK10-NEXT: br label [[DOTCANCEL_CONTINUE]]
// CHECK10: .cancel.continue: // CHECK10: .cancel.continue:
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK10-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK10-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK10-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK10-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK10-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK10-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK10-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK10-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK10-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK10-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK10-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK10-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK10-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK10-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
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// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK11-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK11-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK11-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK11-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK11-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK11: .cancel.exit: // CHECK11: .cancel.exit:
// CHECK11-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK11-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK11-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK11-NEXT: br label [[DOTCANCEL_CONTINUE]]
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// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
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// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
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// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK12-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK12-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK12-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK12-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK12-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK12-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK12: .cancel.exit: // CHECK12: .cancel.exit:
// CHECK12-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK12-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK12-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK12-NEXT: br label [[DOTCANCEL_CONTINUE]]
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// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK12-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
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// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK12-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_Z3fooi // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi
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// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK17-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK17-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK17-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK17-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK17: .cancel.exit: // CHECK17: .cancel.exit:
// CHECK17-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK17-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK17-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK17-NEXT: br label [[DOTCANCEL_CONTINUE]]
// CHECK17: .cancel.continue: // CHECK17: .cancel.continue:
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7
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// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK17-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK17-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK17-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK17-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK17-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK17-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK17-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK17-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK17-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK17-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK17-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK18-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK18-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK18-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK18-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK18-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK18: .cancel.exit: // CHECK18: .cancel.exit:
// CHECK18-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK18-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK18-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK18-NEXT: br label [[DOTCANCEL_CONTINUE]]
// CHECK18: .cancel.continue: // CHECK18: .cancel.continue:
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7
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// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK18-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK18-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK18-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK18-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK18-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK18-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK18-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK18-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK18-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK18-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK18-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK18-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK19-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK19-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK19-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK19-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK19-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK19: .cancel.exit: // CHECK19: .cancel.exit:
// CHECK19-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK19-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK19-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK19-NEXT: br label [[DOTCANCEL_CONTINUE]]
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// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK19-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK19-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// //
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK20-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK20-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK20-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK20-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK20-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK20: .cancel.exit: // CHECK20: .cancel.exit:
// CHECK20-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK20-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK20-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK20-NEXT: br label [[DOTCANCEL_CONTINUE]]
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// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK20-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK20-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK25-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK25-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK25-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK25-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK25-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK25-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK25: .cancel.exit: // CHECK25: .cancel.exit:
// CHECK25-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK25-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK25-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK25-NEXT: br label [[DOTCANCEL_CONTINUE]]
// CHECK25: .cancel.continue: // CHECK25: .cancel.continue:
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK25-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK25-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK25-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK25-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK25-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK25-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK25-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
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// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK25-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK25-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK25-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK25-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK25-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK25-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
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// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK26-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK26-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK26-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK26-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK26-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK26-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK26: .cancel.exit: // CHECK26: .cancel.exit:
// CHECK26-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK26-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK26-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK26-NEXT: br label [[DOTCANCEL_CONTINUE]]
// CHECK26: .cancel.continue: // CHECK26: .cancel.continue:
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK26-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK26-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK26-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK26-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK26-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK26-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK26-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
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// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK26-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK26-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK26-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK26-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK26-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK26-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
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// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK27-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK27-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK27-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK27-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK27-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK27: .cancel.exit: // CHECK27: .cancel.exit:
// CHECK27-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK27-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK27-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK27-NEXT: br label [[DOTCANCEL_CONTINUE]]
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// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK27-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
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// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
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// //
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
// CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK28-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) // CHECK28-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
// CHECK28-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK28-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK28-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] // CHECK28-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
// CHECK28: .cancel.exit: // CHECK28: .cancel.exit:
// CHECK28-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) // CHECK28-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]])
// CHECK28-NEXT: br label [[DOTCANCEL_CONTINUE]] // CHECK28-NEXT: br label [[DOTCANCEL_CONTINUE]]
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// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
// CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK28-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
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// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //

clang/test/OpenMP/target_parallel_debug_codegen.cpp

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// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META113:![0-9]+]], metadata !DIExpression()), !dbg [[DBG108]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META113:![0-9]+]], metadata !DIExpression()), !dbg [[DBG108]]
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG114:![0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG114:![0-9]+]]
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG114]] // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG114]] // CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG114]] // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG114]] // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG114]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG114]] // CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG114]] // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP7:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG114]] // CHECK1-NEXT: [[TMP7:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG114]] // CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP5]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG114]] // CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP5]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast i8* [[TMP8]] to i8 addrspace(1)*, !dbg [[DBG114]] // CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast i8* [[TMP8]] to i8 addrspace(1)*, !dbg [[DBG114]]
// CHECK1-NEXT: call void @__omp_outlined___debug__(i32* [[TMP3]], i32* [[TMP4]], [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP9]], i32 [[TMP6]], [10 x [10 x i32]]* [[TMP7]], i8 addrspace(1)* [[TMP10]]) #[[ATTR3:[0-9]+]], !dbg [[DBG114]] // CHECK1-NEXT: call void @__omp_outlined___debug__(i32* [[TMP3]], i32* [[TMP4]], [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP9]], i32 [[TMP6]], [10 x [10 x i32]]* [[TMP7]], i8 addrspace(1)* [[TMP10]]) #[[ATTR3:[0-9]+]], !dbg [[DBG114]]
// CHECK1-NEXT: ret void, !dbg [[DBG114]] // CHECK1-NEXT: ret void, !dbg [[DBG114]]
// //
// //
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// CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META121:![0-9]+]], metadata !DIExpression()), !dbg [[DBG119]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META121:![0-9]+]], metadata !DIExpression()), !dbg [[DBG119]]
// CHECK1-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8 // CHECK1-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8
// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META122:![0-9]+]], metadata !DIExpression()), !dbg [[DBG119]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META122:![0-9]+]], metadata !DIExpression()), !dbg [[DBG119]]
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG123:![0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG123:![0-9]+]]
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG123]] // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG123]]
// CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG123]] // CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG123]]
// CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG123]] // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG123]]
// CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG123]] // CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG123]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG123]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG123]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG123]] // CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG123]]
// CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG123]] // CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG123]]
// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG123]] // CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG123]]
// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast i8* [[TMP6]] to i8 addrspace(1)*, !dbg [[DBG123]] // CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast i8* [[TMP6]] to i8 addrspace(1)*, !dbg [[DBG123]]
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug__([10 x [10 x [10 x i32]]] addrspace(1)* [[TMP7]], i32 [[TMP4]], [10 x [10 x i32]]* [[TMP5]], i8 addrspace(1)* [[TMP8]]) #[[ATTR3]], !dbg [[DBG123]] // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug__([10 x [10 x [10 x i32]]] addrspace(1)* [[TMP7]], i32 [[TMP4]], [10 x [10 x i32]]* [[TMP5]], i8 addrspace(1)* [[TMP8]]) #[[ATTR3]], !dbg [[DBG123]]
// CHECK1-NEXT: ret void, !dbg [[DBG123]] // CHECK1-NEXT: ret void, !dbg [[DBG123]]
// //
// //
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// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META190:![0-9]+]], metadata !DIExpression()), !dbg [[DBG185]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META190:![0-9]+]], metadata !DIExpression()), !dbg [[DBG185]]
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG191:![0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG191:![0-9]+]]
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG191]] // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG191]] // CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG191]] // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG191]] // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG191]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG191]] // CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG191]] // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP7:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG191]] // CHECK1-NEXT: [[TMP7:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG191]] // CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP5]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG191]] // CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP5]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast [10 x [10 x i32]]* [[TMP7]] to [10 x [10 x i32]] addrspace(1)*, !dbg [[DBG191]] // CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast [10 x [10 x i32]]* [[TMP7]] to [10 x [10 x i32]] addrspace(1)*, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast i8* [[TMP8]] to i8 addrspace(1)*, !dbg [[DBG191]] // CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast i8* [[TMP8]] to i8 addrspace(1)*, !dbg [[DBG191]]
// CHECK1-NEXT: call void @__omp_outlined___debug__1(i32* [[TMP3]], i32* [[TMP4]], [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP9]], i32 [[TMP6]], [10 x [10 x i32]] addrspace(1)* [[TMP10]], i8 addrspace(1)* [[TMP11]]) #[[ATTR3]], !dbg [[DBG191]] // CHECK1-NEXT: call void @__omp_outlined___debug__1(i32* [[TMP3]], i32* [[TMP4]], [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP9]], i32 [[TMP6]], [10 x [10 x i32]] addrspace(1)* [[TMP10]], i8 addrspace(1)* [[TMP11]]) #[[ATTR3]], !dbg [[DBG191]]
// CHECK1-NEXT: ret void, !dbg [[DBG191]] // CHECK1-NEXT: ret void, !dbg [[DBG191]]
// //
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// CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META196:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META196:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194]]
// CHECK1-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8 // CHECK1-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8
// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META197:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META197:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194]]
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG198:![0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG198:![0-9]+]]
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG198]] // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG198]]
// CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG198]] // CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG198]]
// CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG198]] // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG198]]
// CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG198]] // CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG198]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG198]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG198]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG198]] // CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG198]]
// CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG198]] // CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG198]]
// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG198]] // CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG198]]
// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast [10 x [10 x i32]]* [[TMP5]] to [10 x [10 x i32]] addrspace(1)*, !dbg [[DBG198]] // CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast [10 x [10 x i32]]* [[TMP5]] to [10 x [10 x i32]] addrspace(1)*, !dbg [[DBG198]]
// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast i8* [[TMP6]] to i8 addrspace(1)*, !dbg [[DBG198]] // CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast i8* [[TMP6]] to i8 addrspace(1)*, !dbg [[DBG198]]
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug__([10 x [10 x [10 x i32]]] addrspace(1)* [[TMP7]], i32 [[TMP4]], [10 x [10 x i32]] addrspace(1)* [[TMP8]], i8 addrspace(1)* [[TMP9]]) #[[ATTR3]], !dbg [[DBG198]] // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug__([10 x [10 x [10 x i32]]] addrspace(1)* [[TMP7]], i32 [[TMP4]], [10 x [10 x i32]] addrspace(1)* [[TMP8]], i8 addrspace(1)* [[TMP9]]) #[[ATTR3]], !dbg [[DBG198]]
// CHECK1-NEXT: ret void, !dbg [[DBG198]] // CHECK1-NEXT: ret void, !dbg [[DBG198]]
// //
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clang/test/OpenMP/target_parallel_for_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 // CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
// CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 // CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
// CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 // CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 // CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !12 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
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// CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK1-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
// CHECK1-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK1-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK1-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK1-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK1-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK1-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK1-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 // CHECK1-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
// CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 // CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK1-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK1-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK1-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 // CHECK1-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK1: omp.inner.for.end: // CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit: // CHECK1: omp.loop.exit:
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK1: .omp.linear.pu: // CHECK1: .omp.linear.pu:
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
// CHECK1-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8 // CHECK1-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK1: .omp.linear.pu.done: // CHECK1: .omp.linear.pu.done:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK1-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 // CHECK1-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK1-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK1-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 // CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
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// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK1: omp.dispatch.cond: // CHECK1: omp.dispatch.cond:
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK1-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
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// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] // CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 // CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK1-NEXT: store double [[INC]], double* [[A5]], align 8 // CHECK1-NEXT: store double [[INC]], double* [[A5]], align 8
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// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK1-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK1-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
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// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 // CHECK2-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
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// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
// CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 // CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
// CHECK2-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 // CHECK2-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
// CHECK2-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 // CHECK2-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK2-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 // CHECK2-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !12 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
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// CHECK2-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK2-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK2-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK2-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK2-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK2-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK2-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
// CHECK2-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK2-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK2-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK2-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK2-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK2-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK2-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK2-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK2-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 // CHECK2-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
// CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 // CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK2-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK2-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK2-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 // CHECK2-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK2: omp.inner.for.end: // CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit: // CHECK2: omp.loop.exit:
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK2-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK2: .omp.linear.pu: // CHECK2: .omp.linear.pu:
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
// CHECK2-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8 // CHECK2-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK2: .omp.linear.pu.done: // CHECK2: .omp.linear.pu.done:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map.
// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK2-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 // CHECK2-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK2-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK2-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 // CHECK2-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
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// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK2: omp.dispatch.cond: // CHECK2: omp.dispatch.cond:
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK2-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 // CHECK2-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 // CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
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// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK2-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] // CHECK2-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK2-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK2-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK2-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 // CHECK2-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK2-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 // CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK2-NEXT: store double [[INC]], double* [[A5]], align 8 // CHECK2-NEXT: store double [[INC]], double* [[A5]], align 8
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// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK2-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK2-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK2-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
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// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
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// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
// CHECK3-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK3-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK3-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK3-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK3-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK3-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK3-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 // CHECK3-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
// CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
// CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK3-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK3-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK3-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 // CHECK3-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK3-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK3-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK3-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
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// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK4-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
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// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
// CHECK4-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK4-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK4-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK4-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK4-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK4-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK4-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK4-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK4-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 // CHECK4-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
// CHECK4-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
// CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK4-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK4-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK4-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 // CHECK4-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK4-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 // CHECK4-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK4-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK4-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK4-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK4-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
▲ Show 20 Lines • Show All 614 Lines • ▼ Show 20 Lines
// CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK4-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK4-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK4-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
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// CHECK9-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK9-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK9-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK9-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK9-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK9-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
// CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK9-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK9-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK9-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK9-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK9-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK9-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK9-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 // CHECK9-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
// CHECK9-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK9-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK9-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK9-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK9-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 // CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK9: omp.body.continue: // CHECK9: omp.body.continue:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK9-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK9-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK9-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK9: omp.inner.for.end: // CHECK9: omp.inner.for.end:
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK9: omp.loop.exit: // CHECK9: omp.loop.exit:
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK9-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK9-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK9: .omp.linear.pu: // CHECK9: .omp.linear.pu:
// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8 // CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8 // CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK9: .omp.linear.pu.done: // CHECK9: .omp.linear.pu.done:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv // CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv
// CHECK9-SAME: () #[[ATTR3:[0-9]+]] { // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: ret i64 0 // CHECK9-NEXT: ret i64 0
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK9-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 // CHECK9-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK9-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK9-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK9-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK9-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK9-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 // CHECK9-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK9: omp.body.continue: // CHECK9: omp.body.continue:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK9-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK9: omp.dispatch.cond: // CHECK9: omp.dispatch.cond:
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK9-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK9-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 // CHECK9-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
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// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK9-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK9-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] // CHECK9-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 // CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 // CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK9-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK9-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK9-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK9-NEXT: store double [[INC]], double* [[A5]], align 8 // CHECK9-NEXT: store double [[INC]], double* [[A5]], align 8
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// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK9-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK9: omp.body.continue: // CHECK9: omp.body.continue:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
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// CHECK10-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK10-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK10-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK10-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK10-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK10-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK10-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK10-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK10-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
// CHECK10-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK10-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK10-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK10-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK10-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK10-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK10-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK10-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK10-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 // CHECK10-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
// CHECK10-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK10-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK10-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK10-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK10-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK10-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 // CHECK10-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK10: omp.body.continue: // CHECK10: omp.body.continue:
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK10-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK10-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK10-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK10: omp.inner.for.end: // CHECK10: omp.inner.for.end:
// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK10: omp.loop.exit: // CHECK10: omp.loop.exit:
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK10-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK10-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK10-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK10: .omp.linear.pu: // CHECK10: .omp.linear.pu:
// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8 // CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8 // CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK10-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK10-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK10: .omp.linear.pu.done: // CHECK10: .omp.linear.pu.done:
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@_Z7get_valv // CHECK10-LABEL: define {{[^@]+}}@_Z7get_valv
// CHECK10-SAME: () #[[ATTR3:[0-9]+]] { // CHECK10-SAME: () #[[ATTR3:[0-9]+]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: ret i64 0 // CHECK10-NEXT: ret i64 0
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK10-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK10-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK10-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 // CHECK10-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK10-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK10-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK10-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK10-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK10-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 // CHECK10-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK10: omp.body.continue: // CHECK10: omp.body.continue:
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK10-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK10: omp.dispatch.cond: // CHECK10: omp.dispatch.cond:
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK10-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 // CHECK10-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 // CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK10-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 // CHECK10-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
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// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK10-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK10-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] // CHECK10-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK10-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 // CHECK10-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK10-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK10-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK10-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 // CHECK10-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK10-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK10-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK10-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 // CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
// CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK10-NEXT: store double [[INC]], double* [[A5]], align 8 // CHECK10-NEXT: store double [[INC]], double* [[A5]], align 8
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// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK10-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK10-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK10-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK10: omp.body.continue: // CHECK10: omp.body.continue:
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
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// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK11-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
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// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
// CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK11-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK11-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK11-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK11-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK11-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK11-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK11-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 // CHECK11-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
// CHECK11-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK11-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue: // CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK11: omp.inner.for.inc: // CHECK11: omp.inner.for.inc:
// CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK11-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK11-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK11-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 // CHECK11-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK11-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK11-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK11-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK11-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK11-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK11-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue: // CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK11: omp.inner.for.inc: // CHECK11: omp.inner.for.inc:
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK11: omp.inner.for.body: // CHECK11: omp.inner.for.body:
// CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK11-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK11-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK11-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue: // CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK11: omp.inner.for.inc: // CHECK11: omp.inner.for.inc:
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// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK12-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
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// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
// CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK12-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK12-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK12-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK12-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK12-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK12-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK12-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 // CHECK12-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
// CHECK12-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK12-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK12-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK12-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK12-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK12: omp.body.continue: // CHECK12: omp.body.continue:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK12: omp.inner.for.inc: // CHECK12: omp.inner.for.inc:
// CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK12-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK12-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK12-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 // CHECK12-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK12-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 // CHECK12-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK12-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK12-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK12-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK12-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK12-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK12: omp.body.continue: // CHECK12: omp.body.continue:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK12: omp.inner.for.inc: // CHECK12: omp.inner.for.inc:
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK12: omp.inner.for.body: // CHECK12: omp.inner.for.body:
// CHECK12-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK12-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK12-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK12-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK12-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK12: omp.body.continue: // CHECK12: omp.body.continue:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK12: omp.inner.for.inc: // CHECK12: omp.inner.for.inc:
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// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 // CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
// CHECK17-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
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// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
// CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 // CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
// CHECK17-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 // CHECK17-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
// CHECK17-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 // CHECK17-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK17-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 // CHECK17-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !12 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
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// CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
// CHECK17-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK17-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK17-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK17-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 // CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
// CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 // CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK17-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK17-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK17-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 // CHECK17-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK17: omp.inner.for.end: // CHECK17: omp.inner.for.end:
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK17: omp.loop.exit: // CHECK17: omp.loop.exit:
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK17: .omp.linear.pu: // CHECK17: .omp.linear.pu:
// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8 // CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
// CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8 // CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK17: .omp.linear.pu.done: // CHECK17: .omp.linear.pu.done:
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map.
// CHECK17-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK17-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
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// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 // CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 // CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7
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// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK17: omp.dispatch.cond: // CHECK17: omp.dispatch.cond:
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 // CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 // CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
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// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] // CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 // CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK17-NEXT: store double [[INC]], double* [[A5]], align 8 // CHECK17-NEXT: store double [[INC]], double* [[A5]], align 8
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// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
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// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 // CHECK18-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
// CHECK18-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
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// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
// CHECK18-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12 // CHECK18-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
// CHECK18-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 // CHECK18-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
// CHECK18-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 // CHECK18-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK18-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12 // CHECK18-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !12 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 // CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
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// CHECK18-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
// CHECK18-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK18-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK18-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK18-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK18-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK18-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK18-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK18-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK18-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 // CHECK18-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
// CHECK18-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK18-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 // CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK18-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK18-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK18-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK18-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 // CHECK18-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK18: omp.inner.for.end: // CHECK18: omp.inner.for.end:
// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK18: omp.loop.exit: // CHECK18: omp.loop.exit:
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK18-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK18-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK18-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK18: .omp.linear.pu: // CHECK18: .omp.linear.pu:
// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8 // CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
// CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8 // CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK18: .omp.linear.pu.done: // CHECK18: .omp.linear.pu.done:
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map. // CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map.
// CHECK18-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK18-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
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// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK18-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK18-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK18-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 // CHECK18-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK18-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK18-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK18-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK18-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 // CHECK18-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7
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// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK18: omp.dispatch.cond: // CHECK18: omp.dispatch.cond:
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK18-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 // CHECK18-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 // CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 // CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
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// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK18-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] // CHECK18-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
// CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 // CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 // CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK18-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 // CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK18-NEXT: store double [[INC]], double* [[A5]], align 8 // CHECK18-NEXT: store double [[INC]], double* [[A5]], align 8
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// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK18-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK18-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
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// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
// CHECK19-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK19-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK19-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK19-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 // CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
// CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue: // CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK19: omp.inner.for.inc: // CHECK19: omp.inner.for.inc:
// CHECK19-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK19-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK19-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK19-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK19-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 // CHECK19-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK19-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue: // CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK19: omp.inner.for.inc: // CHECK19: omp.inner.for.inc:
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
▲ Show 20 Lines • Show All 614 Lines • ▼ Show 20 Lines
// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK19: omp.inner.for.body: // CHECK19: omp.inner.for.body:
// CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK19-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK19-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue: // CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK19: omp.inner.for.inc: // CHECK19: omp.inner.for.inc:
▲ Show 20 Lines • Show All 521 Lines • ▼ Show 20 Lines
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
// CHECK20-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK20-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK20-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK20-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK20-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK20-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK20-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK20-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK20-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 // CHECK20-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
// CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue: // CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK20: omp.inner.for.inc: // CHECK20: omp.inner.for.inc:
// CHECK20-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK20-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK20-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK20-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK20-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 // CHECK20-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]]
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK20-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 // CHECK20-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK20-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK20-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK20-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue: // CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK20: omp.inner.for.inc: // CHECK20: omp.inner.for.inc:
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]]
▲ Show 20 Lines • Show All 614 Lines • ▼ Show 20 Lines
// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
// CHECK20: omp.inner.for.body: // CHECK20: omp.inner.for.body:
// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK20-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK20-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue: // CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK20: omp.inner.for.inc: // CHECK20: omp.inner.for.inc:
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
// CHECK25-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK25-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK25-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK25-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK25-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK25-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK25-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 // CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
// CHECK25-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK25-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK25-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK25-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK25-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK25-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK25-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK25-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK25-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK25-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK25-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 // CHECK25-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
// CHECK25-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK25-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK25-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK25-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK25-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 // CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK25: omp.body.continue: // CHECK25: omp.body.continue:
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK25: omp.inner.for.inc: // CHECK25: omp.inner.for.inc:
// CHECK25-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK25-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK25-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK25-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK25-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 // CHECK25-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK25: omp.inner.for.end: // CHECK25: omp.inner.for.end:
// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK25: omp.loop.exit: // CHECK25: omp.loop.exit:
// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK25-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK25-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK25-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK25-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK25: .omp.linear.pu: // CHECK25: .omp.linear.pu:
// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK25-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8 // CHECK25-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK25-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 // CHECK25-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
// CHECK25-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8 // CHECK25-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK25-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK25-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK25: .omp.linear.pu.done: // CHECK25: .omp.linear.pu.done:
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@_Z7get_valv // CHECK25-LABEL: define {{[^@]+}}@_Z7get_valv
// CHECK25-SAME: () #[[ATTR3:[0-9]+]] { // CHECK25-SAME: () #[[ATTR3:[0-9]+]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: ret i64 0 // CHECK25-NEXT: ret i64 0
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK25: omp.inner.for.body: // CHECK25: omp.inner.for.body:
// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK25-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK25-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK25-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 // CHECK25-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK25-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK25-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK25-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK25-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK25-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 // CHECK25-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK25: omp.body.continue: // CHECK25: omp.body.continue:
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK25: omp.inner.for.inc: // CHECK25: omp.inner.for.inc:
// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK25-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK25-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK25-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK25-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK25-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK25-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK25: omp.dispatch.cond: // CHECK25: omp.dispatch.cond:
// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK25-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK25-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK25-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK25: omp.inner.for.body: // CHECK25: omp.inner.for.body:
// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK25-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 // CHECK25-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK25-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 // CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK25-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 // CHECK25-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
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// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK25-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK25-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK25-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] // CHECK25-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
// CHECK25-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK25: omp.inner.for.body: // CHECK25: omp.inner.for.body:
// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 // CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 // CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK25-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK25-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK25-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 // CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK25-NEXT: store double [[INC]], double* [[A5]], align 8 // CHECK25-NEXT: store double [[INC]], double* [[A5]], align 8
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// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK25: omp.inner.for.body: // CHECK25: omp.inner.for.body:
// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK25-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK25-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK25-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK25-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK25: omp.body.continue: // CHECK25: omp.body.continue:
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK25: omp.inner.for.inc: // CHECK25: omp.inner.for.inc:
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// CHECK26-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK26-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK26-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK26-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK26-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK26-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK26-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4 // CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
// CHECK26-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK26-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK26-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK26-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK26-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK26-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK26-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK26-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK26-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK26-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK26-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4 // CHECK26-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
// CHECK26-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK26-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK26-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK26-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK26-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8 // CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK26: omp.body.continue: // CHECK26: omp.body.continue:
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK26: omp.inner.for.inc: // CHECK26: omp.inner.for.inc:
// CHECK26-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK26-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK26-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK26-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK26-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8 // CHECK26-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK26: omp.inner.for.end: // CHECK26: omp.inner.for.end:
// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK26: omp.loop.exit: // CHECK26: omp.loop.exit:
// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK26-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK26-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK26-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK26-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK26: .omp.linear.pu: // CHECK26: .omp.linear.pu:
// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK26-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8 // CHECK26-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK26-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4 // CHECK26-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
// CHECK26-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8 // CHECK26-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK26-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK26-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK26: .omp.linear.pu.done: // CHECK26: .omp.linear.pu.done:
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@_Z7get_valv // CHECK26-LABEL: define {{[^@]+}}@_Z7get_valv
// CHECK26-SAME: () #[[ATTR3:[0-9]+]] { // CHECK26-SAME: () #[[ATTR3:[0-9]+]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: ret i64 0 // CHECK26-NEXT: ret i64 0
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK26: omp.inner.for.body: // CHECK26: omp.inner.for.body:
// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK26-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK26-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK26-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2 // CHECK26-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK26-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK26-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK26-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK26-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK26-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK26-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK26-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8 // CHECK26-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK26: omp.body.continue: // CHECK26: omp.body.continue:
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK26: omp.inner.for.inc: // CHECK26: omp.inner.for.inc:
// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK26-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK26-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK26-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK26-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK26-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK26-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK26: omp.dispatch.cond: // CHECK26: omp.dispatch.cond:
// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK26-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK26-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK26-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK26-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK26: omp.inner.for.body: // CHECK26: omp.inner.for.body:
// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK26-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1 // CHECK26-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK26-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4 // CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK26-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4 // CHECK26-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
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// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK26-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK26-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK26-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] // CHECK26-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
// CHECK26-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK26-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK26: omp.inner.for.body: // CHECK26: omp.inner.for.body:
// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 // CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8 // CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK26-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK26-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK26-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8 // CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK26-NEXT: store double [[INC]], double* [[A5]], align 8 // CHECK26-NEXT: store double [[INC]], double* [[A5]], align 8
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// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK26: omp.inner.for.body: // CHECK26: omp.inner.for.body:
// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK26-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK26-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK26-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK26-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK26: omp.body.continue: // CHECK26: omp.body.continue:
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK26: omp.inner.for.inc: // CHECK26: omp.inner.for.inc:
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// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK27-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 // CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
// CHECK27-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK27-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK27-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK27-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK27-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK27-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK27-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK27-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK27-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK27-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK27-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 // CHECK27-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
// CHECK27-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK27-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK27-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK27-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK27-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK27-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK27: omp.body.continue: // CHECK27: omp.body.continue:
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK27: omp.inner.for.inc: // CHECK27: omp.inner.for.inc:
// CHECK27-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK27-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK27-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK27-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK27-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 // CHECK27-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK27-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 // CHECK27-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK27-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK27-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK27-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK27-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK27-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK27-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK27-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK27: omp.body.continue: // CHECK27: omp.body.continue:
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK27: omp.inner.for.inc: // CHECK27: omp.inner.for.inc:
// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK27-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK27-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK27-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]]
▲ Show 20 Lines • Show All 205 Lines • ▼ Show 20 Lines
// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4
▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
// CHECK27: omp.inner.for.body: // CHECK27: omp.inner.for.body:
// CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK27-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK27-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK27-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK27-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK27: omp.body.continue: // CHECK27: omp.body.continue:
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK27: omp.inner.for.inc: // CHECK27: omp.inner.for.inc:
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK28-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 // CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
// CHECK28-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK28-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK28-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8 // CHECK28-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
// CHECK28-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK28-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK28-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK28-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK28-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK28-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK28-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4 // CHECK28-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
// CHECK28-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK28-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK28-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK28-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK28-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK28-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK28: omp.body.continue: // CHECK28: omp.body.continue:
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK28: omp.inner.for.inc: // CHECK28: omp.inner.for.inc:
// CHECK28-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK28-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK28-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK28-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK28-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8 // CHECK28-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK28-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2 // CHECK28-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK28-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK28-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK28-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK28-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK28-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK28-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK28-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK28: omp.body.continue: // CHECK28: omp.body.continue:
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK28: omp.inner.for.inc: // CHECK28: omp.inner.for.inc:
// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK28-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK28-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK28-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK28: omp.inner.for.body: // CHECK28: omp.inner.for.body:
// CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK28-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK28-NEXT: store i64 [[ADD]], i64* [[I]], align 8 // CHECK28-NEXT: store i64 [[ADD]], i64* [[I]], align 8
// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK28-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK28: omp.body.continue: // CHECK28: omp.body.continue:
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK28: omp.inner.for.inc: // CHECK28: omp.inner.for.inc:
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clang/test/OpenMP/target_parallel_for_debug_codegen.cpp

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// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META121:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META121:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116]]
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG122:![0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG122:![0-9]+]]
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG122]] // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG122]] // CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG122]] // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG122]] // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG122]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG122]] // CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG122]] // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP7:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG122]] // CHECK1-NEXT: [[TMP7:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG122]] // CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP5]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG122]] // CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP5]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast i8* [[TMP8]] to i8 addrspace(1)*, !dbg [[DBG122]] // CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast i8* [[TMP8]] to i8 addrspace(1)*, !dbg [[DBG122]]
// CHECK1-NEXT: call void @__omp_outlined___debug__(i32* [[TMP3]], i32* [[TMP4]], [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP9]], i32 [[TMP6]], [10 x [10 x i32]]* [[TMP7]], i8 addrspace(1)* [[TMP10]]) #[[ATTR3:[0-9]+]], !dbg [[DBG122]] // CHECK1-NEXT: call void @__omp_outlined___debug__(i32* [[TMP3]], i32* [[TMP4]], [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP9]], i32 [[TMP6]], [10 x [10 x i32]]* [[TMP7]], i8 addrspace(1)* [[TMP10]]) #[[ATTR3:[0-9]+]], !dbg [[DBG122]]
// CHECK1-NEXT: ret void, !dbg [[DBG122]] // CHECK1-NEXT: ret void, !dbg [[DBG122]]
// //
// //
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// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i64* [[DOTCAPTURE_EXPR__ADDR]], metadata [[META131:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i64* [[DOTCAPTURE_EXPR__ADDR]], metadata [[META131:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127]]
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG132:![0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG132:![0-9]+]]
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG132]] // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG132]]
// CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG132]] // CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG132]]
// CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG132]] // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG132]]
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*, !dbg [[DBG132]] // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*, !dbg [[DBG132]]
// CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG132]] // CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG132]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG132]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG132]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG132]] // CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG132]]
// CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG132]] // CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG132]]
// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 8, !dbg [[DBG132]] // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1, !dbg [[DBG132]]
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1, !dbg [[DBG132]] // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1, !dbg [[DBG132]]
// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG132]] // CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG132]]
// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast i8* [[TMP6]] to i8 addrspace(1)*, !dbg [[DBG132]] // CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast i8* [[TMP6]] to i8 addrspace(1)*, !dbg [[DBG132]]
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug__([10 x [10 x [10 x i32]]] addrspace(1)* [[TMP8]], i32 [[TMP4]], [10 x [10 x i32]]* [[TMP5]], i8 addrspace(1)* [[TMP9]], i1 [[TOBOOL]]) #[[ATTR3]], !dbg [[DBG132]] // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug__([10 x [10 x [10 x i32]]] addrspace(1)* [[TMP8]], i32 [[TMP4]], [10 x [10 x i32]]* [[TMP5]], i8 addrspace(1)* [[TMP9]], i1 [[TOBOOL]]) #[[ATTR3]], !dbg [[DBG132]]
// CHECK1-NEXT: ret void, !dbg [[DBG132]] // CHECK1-NEXT: ret void, !dbg [[DBG132]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__ // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__
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// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META212:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META212:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207]]
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG213:![0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG213:![0-9]+]]
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG213]] // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG213]] // CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG213]] // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG213]] // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG213]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG213]] // CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG213]] // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP7:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG213]] // CHECK1-NEXT: [[TMP7:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG213]] // CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP5]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG213]] // CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP5]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast [10 x [10 x i32]]* [[TMP7]] to [10 x [10 x i32]] addrspace(1)*, !dbg [[DBG213]] // CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast [10 x [10 x i32]]* [[TMP7]] to [10 x [10 x i32]] addrspace(1)*, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast i8* [[TMP8]] to i8 addrspace(1)*, !dbg [[DBG213]] // CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast i8* [[TMP8]] to i8 addrspace(1)*, !dbg [[DBG213]]
// CHECK1-NEXT: call void @__omp_outlined___debug__1(i32* [[TMP3]], i32* [[TMP4]], [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP9]], i32 [[TMP6]], [10 x [10 x i32]] addrspace(1)* [[TMP10]], i8 addrspace(1)* [[TMP11]]) #[[ATTR3]], !dbg [[DBG213]] // CHECK1-NEXT: call void @__omp_outlined___debug__1(i32* [[TMP3]], i32* [[TMP4]], [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP9]], i32 [[TMP6]], [10 x [10 x i32]] addrspace(1)* [[TMP10]], i8 addrspace(1)* [[TMP11]]) #[[ATTR3]], !dbg [[DBG213]]
// CHECK1-NEXT: ret void, !dbg [[DBG213]] // CHECK1-NEXT: ret void, !dbg [[DBG213]]
// //
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// CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META220:![0-9]+]], metadata !DIExpression()), !dbg [[DBG218]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META220:![0-9]+]], metadata !DIExpression()), !dbg [[DBG218]]
// CHECK1-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8 // CHECK1-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8
// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META221:![0-9]+]], metadata !DIExpression()), !dbg [[DBG218]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META221:![0-9]+]], metadata !DIExpression()), !dbg [[DBG218]]
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG222:![0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG222:![0-9]+]]
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG222]] // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG222]]
// CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG222]] // CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG222]]
// CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG222]] // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG222]]
// CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG222]] // CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG222]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG222]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG222]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG222]] // CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG222]]
// CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG222]] // CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG222]]
// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG222]] // CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG222]]
// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast [10 x [10 x i32]]* [[TMP5]] to [10 x [10 x i32]] addrspace(1)*, !dbg [[DBG222]] // CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast [10 x [10 x i32]]* [[TMP5]] to [10 x [10 x i32]] addrspace(1)*, !dbg [[DBG222]]
// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast i8* [[TMP6]] to i8 addrspace(1)*, !dbg [[DBG222]] // CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast i8* [[TMP6]] to i8 addrspace(1)*, !dbg [[DBG222]]
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__([10 x [10 x [10 x i32]]] addrspace(1)* [[TMP7]], i32 [[TMP4]], [10 x [10 x i32]] addrspace(1)* [[TMP8]], i8 addrspace(1)* [[TMP9]]) #[[ATTR3]], !dbg [[DBG222]] // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__([10 x [10 x [10 x i32]]] addrspace(1)* [[TMP7]], i32 [[TMP4]], [10 x [10 x i32]] addrspace(1)* [[TMP8]], i8 addrspace(1)* [[TMP9]]) #[[ATTR3]], !dbg [[DBG222]]
// CHECK1-NEXT: ret void, !dbg [[DBG222]] // CHECK1-NEXT: ret void, !dbg [[DBG222]]
// //
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clang/test/OpenMP/target_parallel_for_simd_codegen.cpp

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// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 // CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
// CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
// CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 // CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
// CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 // CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26 // CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
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// CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK1-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29
// CHECK1-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK1-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
// CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
// CHECK1-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK1-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK1-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK1-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK1-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29 // CHECK1-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
// CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29 // CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
// CHECK1-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK1-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK1-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 // CHECK1-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
// CHECK1: omp.inner.for.end: // CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit: // CHECK1: omp.loop.exit:
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK1: .omp.final.then: // CHECK1: .omp.final.then:
// CHECK1-NEXT: store i64 400, i64* [[IT]], align 8 // CHECK1-NEXT: store i64 400, i64* [[IT]], align 8
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK1: .omp.final.done: // CHECK1: .omp.final.done:
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
// CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK1: .omp.linear.pu: // CHECK1: .omp.linear.pu:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK1-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
// CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8 // CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK1: .omp.linear.pu.done: // CHECK1: .omp.linear.pu.done:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK1-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32 // CHECK1-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK1-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK1-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
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// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
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// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK1: omp.dispatch.cond: // CHECK1: omp.dispatch.cond:
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK1-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
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// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38
// CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] // CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38 // CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
// CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !38 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !38
// CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !38 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !38
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK1-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !38 // CHECK1-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !38
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// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !41 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !41
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK1-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !41 // CHECK1-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !41
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !41 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !41
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !41 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !41
// CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !41 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !41
// CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !41 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !41
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
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// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 // CHECK2-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
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// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
// CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26 // CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
// CHECK2-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 // CHECK2-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
// CHECK2-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 // CHECK2-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK2-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26 // CHECK2-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
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// CHECK2-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK2-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK2-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK2-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK2-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK2-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK2-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29
// CHECK2-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK2-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
// CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
// CHECK2-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK2-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK2-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK2-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK2-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK2-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK2-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29 // CHECK2-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
// CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29 // CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29 // CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
// CHECK2-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK2-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK2-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 // CHECK2-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
// CHECK2: omp.inner.for.end: // CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit: // CHECK2: omp.loop.exit:
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK2-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK2: .omp.final.then: // CHECK2: .omp.final.then:
// CHECK2-NEXT: store i64 400, i64* [[IT]], align 8 // CHECK2-NEXT: store i64 400, i64* [[IT]], align 8
// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK2: .omp.final.done: // CHECK2: .omp.final.done:
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK2-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
// CHECK2-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK2: .omp.linear.pu: // CHECK2: .omp.linear.pu:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK2-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
// CHECK2-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8 // CHECK2-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK2: .omp.linear.pu.done: // CHECK2: .omp.linear.pu.done:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK2-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32 // CHECK2-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK2-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK2-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK2-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK2-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
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// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
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// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK2: omp.dispatch.cond: // CHECK2: omp.dispatch.cond:
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK2-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35 // CHECK2-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35 // CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
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// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38
// CHECK2-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] // CHECK2-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK2-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK2-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK2-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38 // CHECK2-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
// CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !38 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !38
// CHECK2-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !38 // CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !38
// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK2-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !38 // CHECK2-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !38
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// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !41 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !41
// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK2-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !41 // CHECK2-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !41
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !41 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !41
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !41 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !41
// CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !41 // CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !41
// CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !41 // CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !41
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK2-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
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// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
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// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30
// CHECK3-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK3-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
// CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
// CHECK3-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK3-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK3-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK3-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK3-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30 // CHECK3-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
// CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
// CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
// CHECK3-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK3-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK3-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 // CHECK3-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
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// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK3-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
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// CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK3-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !42 // CHECK3-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !42
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !42 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
// CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !42 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !42
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !42 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !42
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
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// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK4-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
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// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30
// CHECK4-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK4-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
// CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
// CHECK4-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK4-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK4-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK4-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK4-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK4-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK4-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30 // CHECK4-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
// CHECK4-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK4-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
// CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 // CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
// CHECK4-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK4-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK4-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 // CHECK4-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
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// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK4-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33 // CHECK4-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK4-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK4-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK4-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK4-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK4-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK4-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
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// CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK4-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !42 // CHECK4-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !42
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !42 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
// CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !42 // CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !42
// CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !42 // CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !42
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK4-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
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// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 // CHECK5-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
// CHECK5-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
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// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
// CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26 // CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26
// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
// CHECK5-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 // CHECK5-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
// CHECK5-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 // CHECK5-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK5-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26 // CHECK5-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue: // CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc: // CHECK5: omp.inner.for.inc:
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
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// CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK5-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK5-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK5-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK5-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK5-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK5-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK5-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK5-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK5-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK5-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29
// CHECK5-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK5-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
// CHECK5-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK5-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK5-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK5-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK5-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK5-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK5-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29 // CHECK5-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
// CHECK5-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29 // CHECK5-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK5-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK5-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK5-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29 // CHECK5-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue: // CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc: // CHECK5: omp.inner.for.inc:
// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
// CHECK5-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK5-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK5-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 // CHECK5-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
// CHECK5: omp.inner.for.end: // CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK5: omp.loop.exit: // CHECK5: omp.loop.exit:
// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK5-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK5-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK5-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK5-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK5: .omp.final.then: // CHECK5: .omp.final.then:
// CHECK5-NEXT: store i64 400, i64* [[IT]], align 8 // CHECK5-NEXT: store i64 400, i64* [[IT]], align 8
// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK5: .omp.final.done: // CHECK5: .omp.final.done:
// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
// CHECK5-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK5-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK5: .omp.linear.pu: // CHECK5: .omp.linear.pu:
// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK5-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8 // CHECK5-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
// CHECK5-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8 // CHECK5-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK5: .omp.linear.pu.done: // CHECK5: .omp.linear.pu.done:
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK5-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK5-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK5-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32 // CHECK5-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK5-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK5-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK5-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK5-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK5-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK5-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue: // CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc: // CHECK5: omp.inner.for.inc:
// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
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// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK5-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7
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// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK5-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK5: omp.dispatch.cond: // CHECK5: omp.dispatch.cond:
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK5-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35 // CHECK5-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK5-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK5-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK5-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK5-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK5-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK5-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK5-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK5-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35 // CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
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// CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK5-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 // CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK5-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK5-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK5-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK5-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK5: omp_if.then: // CHECK5: omp_if.then:
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]])
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK5: omp_if.else: // CHECK5: omp_if.else:
// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) // CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK5-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK5-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK5: omp_if.then: // CHECK5: omp_if.then:
// CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
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// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38
// CHECK5-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] // CHECK5-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
// CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK5-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38 // CHECK5-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
// CHECK5-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double // CHECK5-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00 // CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !39, !llvm.access.group !38 // CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !39, !llvm.access.group !38
// CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK5-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38 // CHECK5-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38
// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 // CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
// CHECK5-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38 // CHECK5-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38
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// CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK5-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] // CHECK5-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
// CHECK5-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]] // CHECK5-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]]
// CHECK5: omp.inner.for.body17: // CHECK5: omp.inner.for.body17:
// CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK5-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400 // CHECK5-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400
// CHECK5-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]] // CHECK5-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
// CHECK5-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8 // CHECK5-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8
// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double // CHECK5-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
// CHECK5-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00 // CHECK5-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
// CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK5-NEXT: store double [[ADD21]], double* [[A22]], align 8 // CHECK5-NEXT: store double [[ADD21]], double* [[A22]], align 8
// CHECK5-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK5-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8 // CHECK5-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8
// CHECK5-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00 // CHECK5-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00
// CHECK5-NEXT: store double [[INC24]], double* [[A23]], align 8 // CHECK5-NEXT: store double [[INC24]], double* [[A23]], align 8
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// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK5-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK5-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !44 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !44
// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK5-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !44 // CHECK5-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !44
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !44 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK5-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !44 // CHECK5-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !44 // CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK5-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 // CHECK5-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue: // CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc: // CHECK5: omp.inner.for.inc:
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// CHECK6-NEXT: entry: // CHECK6-NEXT: entry:
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 // CHECK6-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
// CHECK6-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 // CHECK6-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
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// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
// CHECK6-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26 // CHECK6-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26
// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26 // CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
// CHECK6-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 // CHECK6-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
// CHECK6-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 // CHECK6-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] // CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK6-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26 // CHECK6-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK6-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue: // CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK6: omp.inner.for.inc: // CHECK6: omp.inner.for.inc:
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 // CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
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// CHECK6-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK6-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK6-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK6-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK6-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK6-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK6-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK6-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK6-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK6-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK6-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK6-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29
// CHECK6-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK6-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 // CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29 // CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
// CHECK6-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK6-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK6-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK6-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK6-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK6-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK6-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29 // CHECK6-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
// CHECK6-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29 // CHECK6-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK6-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK6-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK6-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29 // CHECK6-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue: // CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK6: omp.inner.for.inc: // CHECK6: omp.inner.for.inc:
// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 // CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
// CHECK6-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK6-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK6-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 // CHECK6-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
// CHECK6: omp.inner.for.end: // CHECK6: omp.inner.for.end:
// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK6: omp.loop.exit: // CHECK6: omp.loop.exit:
// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK6-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK6-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK6-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK6: .omp.final.then: // CHECK6: .omp.final.then:
// CHECK6-NEXT: store i64 400, i64* [[IT]], align 8 // CHECK6-NEXT: store i64 400, i64* [[IT]], align 8
// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK6: .omp.final.done: // CHECK6: .omp.final.done:
// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK6-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
// CHECK6-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK6-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK6: .omp.linear.pu: // CHECK6: .omp.linear.pu:
// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK6-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8 // CHECK6-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
// CHECK6-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8 // CHECK6-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK6-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK6-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK6: .omp.linear.pu.done: // CHECK6: .omp.linear.pu.done:
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK6-NEXT: entry: // CHECK6-NEXT: entry:
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK6-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK6-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK6-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32 // CHECK6-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK6-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK6-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK6-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK6-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK6-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK6-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK6-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue: // CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK6: omp.inner.for.inc: // CHECK6: omp.inner.for.inc:
// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
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// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK6-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7
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// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK6-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK6: omp.dispatch.cond: // CHECK6: omp.dispatch.cond:
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK6-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35 // CHECK6-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK6-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK6-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK6-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK6-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK6-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK6-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK6-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK6-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK6-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK6-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK6-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35 // CHECK6-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
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// CHECK6-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK6-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK6-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4
// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 // CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 // CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK6-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK6-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK6-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK6-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK6-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK6-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK6: omp_if.then: // CHECK6: omp_if.then:
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]])
// CHECK6-NEXT: br label [[OMP_IF_END:%.*]] // CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK6: omp_if.else: // CHECK6: omp_if.else:
// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) // CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK6-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK6-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK6: omp_if.then: // CHECK6: omp_if.then:
// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK6-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) // CHECK6-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK6-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 // CHECK6-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
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// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38 // CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38
// CHECK6-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] // CHECK6-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
// CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38 // CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 // CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
// CHECK6-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK6-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK6-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38 // CHECK6-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
// CHECK6-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double // CHECK6-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00 // CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !39, !llvm.access.group !38 // CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !39, !llvm.access.group !38
// CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK6-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38 // CHECK6-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38
// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 // CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
// CHECK6-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38 // CHECK6-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38
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// CHECK6-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK6-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK6-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] // CHECK6-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
// CHECK6-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]] // CHECK6-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]]
// CHECK6: omp.inner.for.body17: // CHECK6: omp.inner.for.body17:
// CHECK6-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK6-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK6-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400 // CHECK6-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400
// CHECK6-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]] // CHECK6-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
// CHECK6-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8 // CHECK6-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8
// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double // CHECK6-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
// CHECK6-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00 // CHECK6-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
// CHECK6-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK6-NEXT: store double [[ADD21]], double* [[A22]], align 8 // CHECK6-NEXT: store double [[ADD21]], double* [[A22]], align 8
// CHECK6-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK6-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8 // CHECK6-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8
// CHECK6-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00 // CHECK6-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00
// CHECK6-NEXT: store double [[INC24]], double* [[A23]], align 8 // CHECK6-NEXT: store double [[INC24]], double* [[A23]], align 8
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// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK6-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK6-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !44 // CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !44
// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44 // CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK6-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !44 // CHECK6-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !44
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !44 // CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK6-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !44 // CHECK6-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK6-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK6-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK6-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK6-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !44 // CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK6-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 // CHECK6-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue: // CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK6: omp.inner.for.inc: // CHECK6: omp.inner.for.inc:
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// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK7-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK7-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
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// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30
// CHECK7-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK7-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 // CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
// CHECK7-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30 // CHECK7-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
// CHECK7-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK7-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK7-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK7-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK7-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK7-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK7-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30 // CHECK7-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
// CHECK7-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK7-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK7-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK7-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK7-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK7-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK7-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK7-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue: // CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc: // CHECK7: omp.inner.for.inc:
// CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 // CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
// CHECK7-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK7-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK7-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 // CHECK7-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
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// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK7-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33 // CHECK7-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK7-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK7-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK7-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK7-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK7-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK7-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK7-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue: // CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc: // CHECK7: omp.inner.for.inc:
// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
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// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
// CHECK7-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 // CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
// CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK7-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK7-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK7: omp_if.then: // CHECK7: omp_if.then:
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]])
// CHECK7-NEXT: br label [[OMP_IF_END:%.*]] // CHECK7-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK7: omp_if.else: // CHECK7: omp_if.else:
// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) // CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
// CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK7-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK7-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK7: omp_if.then: // CHECK7: omp_if.then:
// CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK7-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
// CHECK7-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
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// CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK7-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK7-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK7: omp.inner.for.body: // CHECK7: omp.inner.for.body:
// CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK7-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !45 // CHECK7-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !45
// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45 // CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !45 // CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue: // CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc: // CHECK7: omp.inner.for.inc:
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// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK8-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK8-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK8-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK8-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK8-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK8-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
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// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30
// CHECK8-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK8-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK8-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 // CHECK8-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
// CHECK8-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30 // CHECK8-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
// CHECK8-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK8-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK8-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK8-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK8-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK8-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK8-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30 // CHECK8-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
// CHECK8-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK8-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK8-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK8-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK8-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK8-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK8-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK8-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK8: omp.body.continue: // CHECK8: omp.body.continue:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK8: omp.inner.for.inc: // CHECK8: omp.inner.for.inc:
// CHECK8-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 // CHECK8-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
// CHECK8-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK8-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK8-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 // CHECK8-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
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// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK8-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33 // CHECK8-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK8-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK8-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK8-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK8-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK8-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK8-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK8-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK8-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK8: omp.body.continue: // CHECK8: omp.body.continue:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK8: omp.inner.for.inc: // CHECK8: omp.inner.for.inc:
// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
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// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
// CHECK8-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 // CHECK8-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 // CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 // CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
// CHECK8-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK8-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK8-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK8-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK8-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK8-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK8: omp_if.then: // CHECK8: omp_if.then:
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]])
// CHECK8-NEXT: br label [[OMP_IF_END:%.*]] // CHECK8-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK8: omp_if.else: // CHECK8: omp_if.else:
// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) // CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
// CHECK8-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 // CHECK8-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK8-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK8-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK8-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK8: omp_if.then: // CHECK8: omp_if.then:
// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK8-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) // CHECK8-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
// CHECK8-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK8-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK8-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 // CHECK8-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
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// CHECK8-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK8-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK8-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK8-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK8-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14
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// CHECK8: omp.inner.for.body: // CHECK8: omp.inner.for.body:
// CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45 // CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK8-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !45 // CHECK8-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !45
// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45 // CHECK8-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45 // CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK8-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK8-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !45 // CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 // CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK8: omp.body.continue: // CHECK8: omp.body.continue:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK8: omp.inner.for.inc: // CHECK8: omp.inner.for.inc:
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// CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17
// CHECK17-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK17-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
// CHECK17-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK17-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17 // CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
// CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17 // CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17 // CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
// CHECK17-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK17-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK17-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 // CHECK17-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
// CHECK17: omp.inner.for.end: // CHECK17: omp.inner.for.end:
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK17: omp.loop.exit: // CHECK17: omp.loop.exit:
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK17: .omp.final.then: // CHECK17: .omp.final.then:
// CHECK17-NEXT: store i64 400, i64* [[IT]], align 8 // CHECK17-NEXT: store i64 400, i64* [[IT]], align 8
// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK17: .omp.final.done: // CHECK17: .omp.final.done:
// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
// CHECK17-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK17-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK17: .omp.linear.pu: // CHECK17: .omp.linear.pu:
// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK17-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8 // CHECK17-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
// CHECK17-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8 // CHECK17-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK17: .omp.linear.pu.done: // CHECK17: .omp.linear.pu.done:
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv
// CHECK17-SAME: () #[[ATTR3:[0-9]+]] { // CHECK17-SAME: () #[[ATTR3:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: ret i64 0 // CHECK17-NEXT: ret i64 0
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20 // CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !20
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !20
// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20 // CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 // CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
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// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK17: omp.dispatch.cond: // CHECK17: omp.dispatch.cond:
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23 // CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
// CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23 // CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
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// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26
// CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] // CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26 // CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !26 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !26
// CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !26 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !26
// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK17-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !26 // CHECK17-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !26
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// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29
// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !29 // CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !29
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !29 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !29
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !29 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !29
// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !29 // CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !29
// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !29 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !29
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !29 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !29
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !29 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !29
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
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// CHECK18-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17
// CHECK18-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK18-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17 // CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
// CHECK18-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK18-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK18-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK18-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK18-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK18-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK18-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17 // CHECK18-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
// CHECK18-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17 // CHECK18-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17 // CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 // CHECK18-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
// CHECK18-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK18-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK18-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 // CHECK18-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
// CHECK18: omp.inner.for.end: // CHECK18: omp.inner.for.end:
// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK18: omp.loop.exit: // CHECK18: omp.loop.exit:
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK18-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK18-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK18-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK18: .omp.final.then: // CHECK18: .omp.final.then:
// CHECK18-NEXT: store i64 400, i64* [[IT]], align 8 // CHECK18-NEXT: store i64 400, i64* [[IT]], align 8
// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK18: .omp.final.done: // CHECK18: .omp.final.done:
// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK18-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
// CHECK18-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK18-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK18: .omp.linear.pu: // CHECK18: .omp.linear.pu:
// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK18-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8 // CHECK18-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
// CHECK18-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8 // CHECK18-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK18: .omp.linear.pu.done: // CHECK18: .omp.linear.pu.done:
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@_Z7get_valv // CHECK18-LABEL: define {{[^@]+}}@_Z7get_valv
// CHECK18-SAME: () #[[ATTR3:[0-9]+]] { // CHECK18-SAME: () #[[ATTR3:[0-9]+]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: ret i64 0 // CHECK18-NEXT: ret i64 0
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK18-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK18-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK18-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20 // CHECK18-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !20
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !20
// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20 // CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK18-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK18-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK18-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK18-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK18-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20 // CHECK18-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 // CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
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// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK18: omp.dispatch.cond: // CHECK18: omp.dispatch.cond:
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK18-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23 // CHECK18-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23 // CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23 // CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
// CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23 // CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
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// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26 // CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26
// CHECK18-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] // CHECK18-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
// CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
// CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 // CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26 // CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !26 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !26
// CHECK18-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !26 // CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !26
// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK18-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !26 // CHECK18-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !26
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// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29 // CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29
// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK18-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !29 // CHECK18-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !29
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !29 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !29
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !29 // CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !29
// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !29 // CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !29
// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !29 // CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !29
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !29 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !29
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !29 // CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !29
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
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// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
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// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18
// CHECK19-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK19-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
// CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
// CHECK19-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK19-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18 // CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
// CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18 // CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18 // CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue: // CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK19: omp.inner.for.inc: // CHECK19: omp.inner.for.inc:
// CHECK19-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 // CHECK19-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
// CHECK19-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK19-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK19-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 // CHECK19-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
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// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK19-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21 // CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue: // CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK19: omp.inner.for.inc: // CHECK19: omp.inner.for.inc:
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
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// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK19: omp.inner.for.body: // CHECK19: omp.inner.for.body:
// CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK19-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !30 // CHECK19-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !30
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !30 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !30
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !30 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !30
// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !30 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !30
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !30 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !30
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue: // CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK19: omp.inner.for.inc: // CHECK19: omp.inner.for.inc:
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// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
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// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18
// CHECK20-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK20-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 // CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18 // CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
// CHECK20-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK20-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK20-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK20-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK20-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK20-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK20-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18 // CHECK20-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
// CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18 // CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18 // CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue: // CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK20: omp.inner.for.inc: // CHECK20: omp.inner.for.inc:
// CHECK20-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 // CHECK20-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
// CHECK20-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK20-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK20-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 // CHECK20-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
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// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK20-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21 // CHECK20-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21 // CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21 // CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK20-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK20-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK20-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK20-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21 // CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue: // CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK20: omp.inner.for.inc: // CHECK20: omp.inner.for.inc:
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
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// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK20: omp.inner.for.body: // CHECK20: omp.inner.for.body:
// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 // CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK20-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !30 // CHECK20-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !30
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !30 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !30
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !30 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !30
// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !30 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !30
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !30 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !30
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue: // CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK20: omp.inner.for.inc: // CHECK20: omp.inner.for.inc:
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// CHECK21-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK21-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK21-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK21-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK21-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK21-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK21-NEXT: ret void // CHECK21-NEXT: ret void
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK21-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK21-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK21-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK21-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK21-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK21-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK21-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17
// CHECK21-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK21-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK21-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 // CHECK21-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
// CHECK21-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17 // CHECK21-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
// CHECK21-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK21-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK21-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK21-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK21-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK21-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK21-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17 // CHECK21-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
// CHECK21-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17 // CHECK21-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK21-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK21-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK21-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK21-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK21-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17 // CHECK21-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK21: omp.body.continue: // CHECK21: omp.body.continue:
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK21: omp.inner.for.inc: // CHECK21: omp.inner.for.inc:
// CHECK21-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 // CHECK21-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
// CHECK21-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK21-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK21-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 // CHECK21-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
// CHECK21: omp.inner.for.end: // CHECK21: omp.inner.for.end:
// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK21: omp.loop.exit: // CHECK21: omp.loop.exit:
// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK21-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK21-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK21-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK21-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK21: .omp.final.then: // CHECK21: .omp.final.then:
// CHECK21-NEXT: store i64 400, i64* [[IT]], align 8 // CHECK21-NEXT: store i64 400, i64* [[IT]], align 8
// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK21: .omp.final.done: // CHECK21: .omp.final.done:
// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK21-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK21-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
// CHECK21-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK21-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK21: .omp.linear.pu: // CHECK21: .omp.linear.pu:
// CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK21-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8 // CHECK21-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
// CHECK21-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8 // CHECK21-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK21-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK21-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK21: .omp.linear.pu.done: // CHECK21: .omp.linear.pu.done:
// CHECK21-NEXT: ret void // CHECK21-NEXT: ret void
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@_Z7get_valv // CHECK21-LABEL: define {{[^@]+}}@_Z7get_valv
// CHECK21-SAME: () #[[ATTR3:[0-9]+]] { // CHECK21-SAME: () #[[ATTR3:[0-9]+]] {
// CHECK21-NEXT: entry: // CHECK21-NEXT: entry:
// CHECK21-NEXT: ret i64 0 // CHECK21-NEXT: ret i64 0
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
// CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK21-NEXT: entry: // CHECK21-NEXT: entry:
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK21-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK21-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK21-NEXT: ret void // CHECK21-NEXT: ret void
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK21: omp.inner.for.body: // CHECK21: omp.inner.for.body:
// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK21-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK21-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK21-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20 // CHECK21-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !20
// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK21-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20 // CHECK21-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !20
// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20 // CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK21-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK21-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK21-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK21-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK21-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20 // CHECK21-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK21: omp.body.continue: // CHECK21: omp.body.continue:
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK21: omp.inner.for.inc: // CHECK21: omp.inner.for.inc:
// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
// CHECK21-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK21-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK21-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 // CHECK21-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
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// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK21-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK21-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK21-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK21-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK21-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK21-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK21-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK21-NEXT: ret void // CHECK21-NEXT: ret void
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK21-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK21-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK21-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK21-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK21: omp.dispatch.cond: // CHECK21: omp.dispatch.cond:
// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK21-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK21-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK21-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK21: omp.inner.for.body: // CHECK21: omp.inner.for.body:
// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK21-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK21-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK21-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23 // CHECK21-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
// CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK21-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23 // CHECK21-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK21-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23 // CHECK21-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
// CHECK21-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK21-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK21-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK21-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK21-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK21-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK21-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23 // CHECK21-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
// CHECK21-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK21-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK21-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23 // CHECK21-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
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// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK21-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK21-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK21-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK21-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK21-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK21-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK21-NEXT: ret void // CHECK21-NEXT: ret void
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK21-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK21-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK21-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK21-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK21-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4 // CHECK21-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4
// CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK21-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK21-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK21-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 // CHECK21-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
// CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK21-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK21-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK21-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK21-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK21-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK21-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK21: omp_if.then: // CHECK21: omp_if.then:
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]])
// CHECK21-NEXT: br label [[OMP_IF_END:%.*]] // CHECK21-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK21: omp_if.else: // CHECK21: omp_if.else:
// CHECK21-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) // CHECK21-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
// CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK21-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK21-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK21-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK21-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK21: omp_if.then: // CHECK21: omp_if.then:
// CHECK21-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK21-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK21-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
// CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
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// CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26
// CHECK21-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] // CHECK21-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
// CHECK21-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK21: omp.inner.for.body: // CHECK21: omp.inner.for.body:
// CHECK21-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
// CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 // CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
// CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK21-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26 // CHECK21-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK21-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double // CHECK21-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00 // CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !27, !llvm.access.group !26 // CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !27, !llvm.access.group !26
// CHECK21-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK21-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK21-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26 // CHECK21-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26
// CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 // CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
// CHECK21-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26 // CHECK21-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26
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// CHECK21-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK21-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK21-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] // CHECK21-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
// CHECK21-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]] // CHECK21-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]]
// CHECK21: omp.inner.for.body17: // CHECK21: omp.inner.for.body17:
// CHECK21-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK21-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK21-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400 // CHECK21-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400
// CHECK21-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]] // CHECK21-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
// CHECK21-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8 // CHECK21-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8
// CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double // CHECK21-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
// CHECK21-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00 // CHECK21-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
// CHECK21-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK21-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK21-NEXT: store double [[ADD21]], double* [[A22]], align 8 // CHECK21-NEXT: store double [[ADD21]], double* [[A22]], align 8
// CHECK21-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK21-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK21-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8 // CHECK21-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8
// CHECK21-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00 // CHECK21-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00
// CHECK21-NEXT: store double [[INC24]], double* [[A23]], align 8 // CHECK21-NEXT: store double [[INC24]], double* [[A23]], align 8
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// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK21-NEXT: ret void // CHECK21-NEXT: ret void
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !32 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !32
// CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK21: omp.inner.for.body: // CHECK21: omp.inner.for.body:
// CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK21-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK21-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !32 // CHECK21-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !32
// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK21-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK21-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK21-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK21-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK21-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK21-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !32 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !32
// CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK21-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !32 // CHECK21-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !32
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK21: omp.body.continue: // CHECK21: omp.body.continue:
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK21: omp.inner.for.inc: // CHECK21: omp.inner.for.inc:
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// CHECK22-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK22-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK22-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 // CHECK22-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* // CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 // CHECK22-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 // CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK22-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
// CHECK22-NEXT: ret void // CHECK22-NEXT: ret void
// //
// //
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK22-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 // CHECK22-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* // CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 // CHECK22-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK22-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK22-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK22-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK22-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
// CHECK22-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK22-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK22-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK22-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK22-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK22-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK22-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17 // CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17
// CHECK22-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 // CHECK22-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
// CHECK22-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 // CHECK22-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
// CHECK22-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17 // CHECK22-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
// CHECK22-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK22-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK22-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] // CHECK22-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK22-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 // CHECK22-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK22-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17 // CHECK22-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
// CHECK22-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17 // CHECK22-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK22-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 // CHECK22-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK22-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK22-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK22-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK22-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK22-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17 // CHECK22-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK22: omp.body.continue: // CHECK22: omp.body.continue:
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK22: omp.inner.for.inc: // CHECK22: omp.inner.for.inc:
// CHECK22-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 // CHECK22-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
// CHECK22-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 // CHECK22-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
// CHECK22-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 // CHECK22-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
// CHECK22: omp.inner.for.end: // CHECK22: omp.inner.for.end:
// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK22: omp.loop.exit: // CHECK22: omp.loop.exit:
// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK22-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK22-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
// CHECK22-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK22-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK22: .omp.final.then: // CHECK22: .omp.final.then:
// CHECK22-NEXT: store i64 400, i64* [[IT]], align 8 // CHECK22-NEXT: store i64 400, i64* [[IT]], align 8
// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK22: .omp.final.done: // CHECK22: .omp.final.done:
// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK22-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK22-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
// CHECK22-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK22-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK22: .omp.linear.pu: // CHECK22: .omp.linear.pu:
// CHECK22-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 // CHECK22-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
// CHECK22-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8 // CHECK22-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 // CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
// CHECK22-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8 // CHECK22-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK22-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK22-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK22: .omp.linear.pu.done: // CHECK22: .omp.linear.pu.done:
// CHECK22-NEXT: ret void // CHECK22-NEXT: ret void
// //
// //
// CHECK22-LABEL: define {{[^@]+}}@_Z7get_valv // CHECK22-LABEL: define {{[^@]+}}@_Z7get_valv
// CHECK22-SAME: () #[[ATTR3:[0-9]+]] { // CHECK22-SAME: () #[[ATTR3:[0-9]+]] {
// CHECK22-NEXT: entry: // CHECK22-NEXT: entry:
// CHECK22-NEXT: ret i64 0 // CHECK22-NEXT: ret i64 0
// //
// //
// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
// CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK22-NEXT: entry: // CHECK22-NEXT: entry:
// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK22-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK22-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK22-NEXT: ret void // CHECK22-NEXT: ret void
// //
// //
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK22: omp.inner.for.body: // CHECK22: omp.inner.for.body:
// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 // CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK22-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 // CHECK22-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK22-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20 // CHECK22-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !20
// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK22-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20 // CHECK22-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !20
// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20 // CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK22-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 // CHECK22-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK22-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 // CHECK22-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
// CHECK22-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20 // CHECK22-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK22: omp.body.continue: // CHECK22: omp.body.continue:
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK22: omp.inner.for.inc: // CHECK22: omp.inner.for.inc:
// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 // CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
// CHECK22-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK22-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK22-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 // CHECK22-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
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// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK22-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK22-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK22-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK22-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK22-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK22-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK22-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK22-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK22-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK22-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK22-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK22-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK22-NEXT: ret void // CHECK22-NEXT: ret void
// //
// //
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK22-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK22-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK22-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK22-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK22-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 // CHECK22-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK22-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK22-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK22-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK22-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK22: omp.dispatch.cond: // CHECK22: omp.dispatch.cond:
// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 // CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK22-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK22-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK22-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK22-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK22: omp.inner.for.body: // CHECK22: omp.inner.for.body:
// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 // CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] // CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK22-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 // CHECK22-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK22-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23 // CHECK22-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23 // CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK22-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23 // CHECK22-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK22-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23 // CHECK22-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
// CHECK22-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK22-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK22-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK22-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK22-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK22-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK22-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23 // CHECK22-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
// CHECK22-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK22-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK22-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23 // CHECK22-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
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// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK22-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK22-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK22-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK22-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK22-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK22-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK22-NEXT: ret void // CHECK22-NEXT: ret void
// //
// //
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK22-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK22-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK22-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK22-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK22-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4 // CHECK22-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4
// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK22-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK22-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 // CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK22-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK22-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK22-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 // CHECK22-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
// CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK22-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK22-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK22-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK22-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK22-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK22-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK22: omp_if.then: // CHECK22: omp_if.then:
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]])
// CHECK22-NEXT: br label [[OMP_IF_END:%.*]] // CHECK22-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK22: omp_if.else: // CHECK22: omp_if.else:
// CHECK22-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) // CHECK22-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
// CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK22-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK22-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK22-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK22-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK22-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK22-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK22-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK22-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK22-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK22-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK22: omp_if.then: // CHECK22: omp_if.then:
// CHECK22-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK22-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK22-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) // CHECK22-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
// CHECK22-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK22-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK22-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 // CHECK22-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
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// CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26 // CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26
// CHECK22-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] // CHECK22-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
// CHECK22-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK22-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK22: omp.inner.for.body: // CHECK22: omp.inner.for.body:
// CHECK22-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 // CHECK22-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
// CHECK22-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 // CHECK22-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
// CHECK22-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] // CHECK22-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK22-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26 // CHECK22-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26 // CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK22-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double // CHECK22-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00 // CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !27, !llvm.access.group !26 // CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !27, !llvm.access.group !26
// CHECK22-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK22-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK22-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26 // CHECK22-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26
// CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 // CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
// CHECK22-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26 // CHECK22-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26
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// CHECK22-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK22-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK22-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] // CHECK22-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
// CHECK22-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]] // CHECK22-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]]
// CHECK22: omp.inner.for.body17: // CHECK22: omp.inner.for.body17:
// CHECK22-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK22-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK22-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400 // CHECK22-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400
// CHECK22-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]] // CHECK22-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
// CHECK22-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8 // CHECK22-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8
// CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double // CHECK22-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
// CHECK22-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00 // CHECK22-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
// CHECK22-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK22-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK22-NEXT: store double [[ADD21]], double* [[A22]], align 8 // CHECK22-NEXT: store double [[ADD21]], double* [[A22]], align 8
// CHECK22-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK22-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK22-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8 // CHECK22-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8
// CHECK22-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00 // CHECK22-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00
// CHECK22-NEXT: store double [[INC24]], double* [[A23]], align 8 // CHECK22-NEXT: store double [[INC24]], double* [[A23]], align 8
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// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK22-NEXT: ret void // CHECK22-NEXT: ret void
// //
// //
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK22-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !32 // CHECK22-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !32
// CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] // CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK22: omp.inner.for.body: // CHECK22: omp.inner.for.body:
// CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32 // CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK22-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK22-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK22-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !32 // CHECK22-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !32
// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK22-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK22-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK22-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK22-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK22-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK22-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !32 // CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !32
// CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK22-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !32 // CHECK22-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !32
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK22: omp.body.continue: // CHECK22: omp.body.continue:
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK22: omp.inner.for.inc: // CHECK22: omp.inner.for.inc:
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// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK23-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK23-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK23-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK23-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK23-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
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// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18
// CHECK23-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK23-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK23-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 // CHECK23-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
// CHECK23-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18 // CHECK23-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
// CHECK23-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK23-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK23-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK23-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK23-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK23-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK23-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18 // CHECK23-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
// CHECK23-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18 // CHECK23-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK23-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK23-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK23-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK23-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK23-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK23-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK23-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18 // CHECK23-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK23: omp.body.continue: // CHECK23: omp.body.continue:
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK23: omp.inner.for.inc: // CHECK23: omp.inner.for.inc:
// CHECK23-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 // CHECK23-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
// CHECK23-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK23-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK23-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 // CHECK23-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
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// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK23-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK23-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK23-NEXT: ret void // CHECK23-NEXT: ret void
// //
// //
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK23-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21 // CHECK23-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK23-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21 // CHECK23-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
// CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21 // CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK23-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK23-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK23-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK23-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK23-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21 // CHECK23-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK23: omp.body.continue: // CHECK23: omp.body.continue:
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK23: omp.inner.for.inc: // CHECK23: omp.inner.for.inc:
// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK23-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK23-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
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// CHECK23-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK23-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK23-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK23-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK23-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK23-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK23-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK23-NEXT: ret void // CHECK23-NEXT: ret void
// //
// //
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK23-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
// CHECK23-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4 // CHECK23-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 // CHECK23-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK23-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK23-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK23-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 // CHECK23-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
// CHECK23-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK23-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK23-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK23-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK23-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK23-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK23: omp_if.then: // CHECK23: omp_if.then:
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]])
// CHECK23-NEXT: br label [[OMP_IF_END:%.*]] // CHECK23-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK23: omp_if.else: // CHECK23: omp_if.else:
// CHECK23-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) // CHECK23-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
// CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
// CHECK23-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 // CHECK23-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK23-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK23-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK23-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK23-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK23-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK23-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK23: omp_if.then: // CHECK23: omp_if.then:
// CHECK23-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK23-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK23-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
// CHECK23-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
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// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK23-NEXT: ret void // CHECK23-NEXT: ret void
// //
// //
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK23: omp.inner.for.body: // CHECK23: omp.inner.for.body:
// CHECK23-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK23-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK23-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK23-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !33 // CHECK23-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !33
// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK23-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 // CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK23: omp.body.continue: // CHECK23: omp.body.continue:
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK23: omp.inner.for.inc: // CHECK23: omp.inner.for.inc:
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// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK24-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK24-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 // CHECK24-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK24-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 // CHECK24-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 // CHECK24-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
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// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18 // CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18
// CHECK24-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 // CHECK24-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
// CHECK24-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 // CHECK24-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
// CHECK24-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18 // CHECK24-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
// CHECK24-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] // CHECK24-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK24-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] // CHECK24-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK24-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 // CHECK24-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK24-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18 // CHECK24-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
// CHECK24-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18 // CHECK24-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK24-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 // CHECK24-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK24-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK24-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK24-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK24-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK24-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18 // CHECK24-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK24: omp.body.continue: // CHECK24: omp.body.continue:
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK24: omp.inner.for.inc: // CHECK24: omp.inner.for.inc:
// CHECK24-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 // CHECK24-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
// CHECK24-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 // CHECK24-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
// CHECK24-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 // CHECK24-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
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// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK24-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK24-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK24-NEXT: ret void // CHECK24-NEXT: ret void
// //
// //
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 // CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK24-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21 // CHECK24-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK24-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21 // CHECK24-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
// CHECK24-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21 // CHECK24-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK24-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK24-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK24-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK24-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK24-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK24-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK24-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21 // CHECK24-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK24: omp.body.continue: // CHECK24: omp.body.continue:
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK24: omp.inner.for.inc: // CHECK24: omp.inner.for.inc:
// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK24-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK24-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK24-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK24-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
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// CHECK24-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK24-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK24-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK24-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK24-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK24-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK24-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK24-NEXT: ret void // CHECK24-NEXT: ret void
// //
// //
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK24-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK24-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
// CHECK24-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4 // CHECK24-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 // CHECK24-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK24-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK24-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 // CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK24-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK24-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK24-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 // CHECK24-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
// CHECK24-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK24-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK24-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK24-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK24-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK24-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK24: omp_if.then: // CHECK24: omp_if.then:
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]])
// CHECK24-NEXT: br label [[OMP_IF_END:%.*]] // CHECK24-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK24: omp_if.else: // CHECK24: omp_if.else:
// CHECK24-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) // CHECK24-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
// CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
// CHECK24-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 // CHECK24-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK24-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK24-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
// CHECK24-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 // CHECK24-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK24-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 // CHECK24-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK24-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK24-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK24: omp_if.then: // CHECK24: omp_if.then:
// CHECK24-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK24-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK24-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) // CHECK24-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
// CHECK24-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK24-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
// CHECK24-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 // CHECK24-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
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// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK24-NEXT: ret void // CHECK24-NEXT: ret void
// //
// //
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK24: omp.inner.for.body: // CHECK24: omp.inner.for.body:
// CHECK24-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33 // CHECK24-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 // CHECK24-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK24-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] // CHECK24-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK24-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !33 // CHECK24-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !33
// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK24-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK24-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK24-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 // CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 // CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK24: omp.body.continue: // CHECK24: omp.body.continue:
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK24: omp.inner.for.inc: // CHECK24: omp.inner.for.inc:
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clang/test/OpenMP/target_parallel_if_codegen.cpp

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// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.else: // CHECK1: omp_if.else:
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
// CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.else: // CHECK1: omp_if.else:
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.else: // CHECK1: omp_if.else:
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
// CHECK1-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR3]] // CHECK1-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR3]]
// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
// CHECK1-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK1-SAME: () #[[ATTR4:[0-9]+]] { // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @__tgt_register_requires(i64 1) // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.else: // CHECK2: omp_if.else:
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
// CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.else: // CHECK2: omp_if.else:
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.else: // CHECK2: omp_if.else:
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
// CHECK2-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR3]] // CHECK2-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR3]]
// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
// CHECK2-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK2-SAME: () #[[ATTR4:[0-9]+]] { // CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
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// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK3: omp_if.else: // CHECK3: omp_if.else:
// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK3: omp_if.else: // CHECK3: omp_if.else:
// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK3: omp_if.else: // CHECK3: omp_if.else:
// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.else: // CHECK4: omp_if.else:
// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.else: // CHECK4: omp_if.else:
// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.else: // CHECK4: omp_if.else:
// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK4-SAME: () #[[ATTR4:[0-9]+]] { // CHECK4-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: call void @__tgt_register_requires(i64 1) // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then: // CHECK9: omp_if.then:
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK9: omp_if.else: // CHECK9: omp_if.else:
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then: // CHECK9: omp_if.then:
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK9: omp_if.else: // CHECK9: omp_if.else:
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK9-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then: // CHECK9: omp_if.then:
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK9: omp_if.else: // CHECK9: omp_if.else:
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
// CHECK9-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] // CHECK9-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]]
// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then: // CHECK10: omp_if.then:
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK10: omp_if.else: // CHECK10: omp_if.else:
// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then: // CHECK10: omp_if.then:
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK10: omp_if.else: // CHECK10: omp_if.else:
// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK10-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then: // CHECK10: omp_if.then:
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK10: omp_if.else: // CHECK10: omp_if.else:
// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
// CHECK10-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] // CHECK10-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]]
// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then: // CHECK11: omp_if.then:
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK11: omp_if.else: // CHECK11: omp_if.else:
// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then: // CHECK11: omp_if.then:
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK11: omp_if.else: // CHECK11: omp_if.else:
// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then: // CHECK11: omp_if.then:
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK11: omp_if.else: // CHECK11: omp_if.else:
// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then: // CHECK12: omp_if.then:
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] // CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK12: omp_if.else: // CHECK12: omp_if.else:
// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then: // CHECK12: omp_if.then:
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] // CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK12: omp_if.else: // CHECK12: omp_if.else:
// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then: // CHECK12: omp_if.then:
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] // CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK12: omp_if.else: // CHECK12: omp_if.else:
// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_Z3bari // CHECK17-LABEL: define {{[^@]+}}@_Z3bari
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// CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK17: omp_if.then: // CHECK17: omp_if.then:
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] // CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK17: omp_if.else: // CHECK17: omp_if.else:
// CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK17-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK17: omp_if.then: // CHECK17: omp_if.then:
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] // CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK17: omp_if.else: // CHECK17: omp_if.else:
// CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK17-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK17: omp_if.then: // CHECK17: omp_if.then:
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK17-NEXT: br label [[OMP_IF_END:%.*]] // CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK17: omp_if.else: // CHECK17: omp_if.else:
// CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
// CHECK17-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR3]] // CHECK17-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR3]]
// CHECK17-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK17-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
// CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK17-SAME: () #[[ATTR4:[0-9]+]] { // CHECK17-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) // CHECK17-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
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// CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK18: omp_if.then: // CHECK18: omp_if.then:
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] // CHECK18-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK18: omp_if.else: // CHECK18: omp_if.else:
// CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK18-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK18: omp_if.then: // CHECK18: omp_if.then:
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] // CHECK18-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK18: omp_if.else: // CHECK18: omp_if.else:
// CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK18-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK18: omp_if.then: // CHECK18: omp_if.then:
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK18-NEXT: br label [[OMP_IF_END:%.*]] // CHECK18-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK18: omp_if.else: // CHECK18: omp_if.else:
// CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
// CHECK18-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR3]] // CHECK18-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR3]]
// CHECK18-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK18-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
// CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK18-SAME: () #[[ATTR4:[0-9]+]] { // CHECK18-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) // CHECK18-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
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// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK19: omp_if.then: // CHECK19: omp_if.then:
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] // CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK19: omp_if.else: // CHECK19: omp_if.else:
// CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK19-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK19: omp_if.then: // CHECK19: omp_if.then:
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] // CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK19: omp_if.else: // CHECK19: omp_if.else:
// CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK19-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK19: omp_if.then: // CHECK19: omp_if.then:
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK19-NEXT: br label [[OMP_IF_END:%.*]] // CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK19: omp_if.else: // CHECK19: omp_if.else:
// CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK20: omp_if.then: // CHECK20: omp_if.then:
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] // CHECK20-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK20: omp_if.else: // CHECK20: omp_if.else:
// CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK20-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK20: omp_if.then: // CHECK20: omp_if.then:
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] // CHECK20-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK20: omp_if.else: // CHECK20: omp_if.else:
// CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK20-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK20: omp_if.then: // CHECK20: omp_if.then:
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK20-NEXT: br label [[OMP_IF_END:%.*]] // CHECK20-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK20: omp_if.else: // CHECK20: omp_if.else:
// CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK20-SAME: () #[[ATTR4:[0-9]+]] { // CHECK20-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) // CHECK20-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK25-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK25: omp_if.then: // CHECK25: omp_if.then:
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK25-NEXT: br label [[OMP_IF_END:%.*]] // CHECK25-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK25: omp_if.else: // CHECK25: omp_if.else:
// CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK25-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK25: omp_if.then: // CHECK25: omp_if.then:
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
// CHECK25-NEXT: br label [[OMP_IF_END:%.*]] // CHECK25-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK25: omp_if.else: // CHECK25: omp_if.else:
// CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK25-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK25: omp_if.then: // CHECK25: omp_if.then:
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK25-NEXT: br label [[OMP_IF_END:%.*]] // CHECK25-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK25: omp_if.else: // CHECK25: omp_if.else:
// CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK25-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 // CHECK25-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
// CHECK25-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] // CHECK25-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]]
// CHECK25-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK25-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
// CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK26-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK26: omp_if.then: // CHECK26: omp_if.then:
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK26-NEXT: br label [[OMP_IF_END:%.*]] // CHECK26-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK26: omp_if.else: // CHECK26: omp_if.else:
// CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK26-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK26: omp_if.then: // CHECK26: omp_if.then:
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
// CHECK26-NEXT: br label [[OMP_IF_END:%.*]] // CHECK26-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK26: omp_if.else: // CHECK26: omp_if.else:
// CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK26-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK26: omp_if.then: // CHECK26: omp_if.then:
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK26-NEXT: br label [[OMP_IF_END:%.*]] // CHECK26-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK26: omp_if.else: // CHECK26: omp_if.else:
// CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
// CHECK26-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 // CHECK26-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
// CHECK26-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] // CHECK26-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]]
// CHECK26-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK26-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
// CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK27-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK27: omp_if.then: // CHECK27: omp_if.then:
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK27-NEXT: br label [[OMP_IF_END:%.*]] // CHECK27-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK27: omp_if.else: // CHECK27: omp_if.else:
// CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK27-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK27: omp_if.then: // CHECK27: omp_if.then:
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
// CHECK27-NEXT: br label [[OMP_IF_END:%.*]] // CHECK27-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK27: omp_if.else: // CHECK27: omp_if.else:
// CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK27-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK27: omp_if.then: // CHECK27: omp_if.then:
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK27-NEXT: br label [[OMP_IF_END:%.*]] // CHECK27-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK27: omp_if.else: // CHECK27: omp_if.else:
// CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK28-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK28: omp_if.then: // CHECK28: omp_if.then:
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK28-NEXT: br label [[OMP_IF_END:%.*]] // CHECK28-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK28: omp_if.else: // CHECK28: omp_if.else:
// CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK28-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 // CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK28: omp_if.then: // CHECK28: omp_if.then:
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
// CHECK28-NEXT: br label [[OMP_IF_END:%.*]] // CHECK28-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK28: omp_if.else: // CHECK28: omp_if.else:
// CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK28-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK28: omp_if.then: // CHECK28: omp_if.then:
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
// CHECK28-NEXT: br label [[OMP_IF_END:%.*]] // CHECK28-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK28: omp_if.else: // CHECK28: omp_if.else:
// CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //

clang/test/OpenMP/target_parallel_num_threads_codegen.cpp

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// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK1-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK1-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK1-SAME: () #[[ATTR4:[0-9]+]] { // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @__tgt_register_requires(i64 1) // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK2-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK2-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK2-SAME: () #[[ATTR4:[0-9]+]] { // CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
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// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK3-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK4-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK4-SAME: () #[[ATTR4:[0-9]+]] { // CHECK4-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: call void @__tgt_register_requires(i64 1) // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
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// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
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// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
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// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
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// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_Z3bari // CHECK17-LABEL: define {{[^@]+}}@_Z3bari
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// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
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// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK17-SAME: () #[[ATTR4:[0-9]+]] { // CHECK17-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) // CHECK17-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
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// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
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// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK18-SAME: () #[[ATTR4:[0-9]+]] { // CHECK18-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) // CHECK18-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
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// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK20-SAME: () #[[ATTR4:[0-9]+]] { // CHECK20-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) // CHECK20-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
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// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) // CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
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// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
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// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
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// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) // CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //

clang/test/OpenMP/target_teams_codegen.cpp

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// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
// CHECK1-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12
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// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
// CHECK1-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15
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// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..22 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..22
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// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..24 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..24
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// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..27 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..27
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK2-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK2-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK2-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK2-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK2-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK2-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK2-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
// CHECK2-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12
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// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
// CHECK2-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15
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// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..22 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..22
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// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK2-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK2-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK2-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..24 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..24
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// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK2-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK2-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK2-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..27 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..27
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..24 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..24
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// CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..27 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..27
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// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..24 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..24
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// CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK4-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK4-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK4-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK4-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK4-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK4-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..27 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..27
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// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK4-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
Show All 11 Lines
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK9-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK9-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK9-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK9-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK9-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
// CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
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// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
// CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
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// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10
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// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK9-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK9-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK9-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
// CHECK10-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
Show All 11 Lines
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK10-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK10-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK10-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK10-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK10-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK10-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK10-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK10-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK10-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
// CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
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// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
// CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK10-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK10-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK10-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK10-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK10-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK10-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
// CHECK11-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
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// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
// CHECK12-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK12-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
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// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK12-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_Z3fooi // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi
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// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK17-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK17-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK17-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK17-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK17-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK17-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK17-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
// CHECK17-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12
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// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
// CHECK17-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..15 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..15
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// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..22 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..22
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// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK17-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK17-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..24 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..24
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// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK17-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK17-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..27 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..27
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK18-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK18-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK18-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK18-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK18-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK18-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK18-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
// CHECK18-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12
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// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
// CHECK18-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..15 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..15
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// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..22 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..22
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// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK18-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK18-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK18-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..24 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..24
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// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK18-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK18-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..27 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..27
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..24 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..24
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// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK19-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK19-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..27 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..27
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// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..24 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..24
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// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK20-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK20-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..27 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..27
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// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK25-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK25-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK25-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK25-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK25-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK25-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
// CHECK25-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
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// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
// CHECK25-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK25-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
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// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..10 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..10
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// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK25-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK25-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK25-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK25-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK25-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK25-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
// CHECK26-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined.
Show All 11 Lines
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 // CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
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// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 // CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double // CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
// CHECK26-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 // CHECK26-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
// CHECK26-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float // CHECK26-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
// CHECK26-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 // CHECK26-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 // CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
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// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
// CHECK26-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
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// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
// CHECK26-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 // CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 // CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 // CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 // CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 // CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 // CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
// CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 // CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK26-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
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// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..10 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..10
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// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double // CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK26-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK26-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK26-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 // CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
// CHECK26-NEXT: store double [[INC]], double* [[A4]], align 8 // CHECK26-NEXT: store double [[INC]], double* [[A4]], align 8
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// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK26-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
// CHECK27-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK27-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
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// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
// CHECK28-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK28-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
// CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
// CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
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// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 // CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 // CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 // CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 // CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
// CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 // CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK28-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
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// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //

clang/test/OpenMP/target_teams_distribute_codegen.cpp

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// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK1-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK1: omp.inner.for.end: // CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit: // CHECK1: omp.loop.exit:
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK1: omp.dispatch.cond: // CHECK1: omp.dispatch.cond:
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
// CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK1-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !22 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22
// CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22
// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !22 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !22
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// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK1-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK1-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: store double [[ADD5]], double* [[A]], align 8 // CHECK1-NEXT: store double [[ADD5]], double* [[A]], align 8
// CHECK1-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK1-NEXT: store double [[INC]], double* [[A6]], align 8 // CHECK1-NEXT: store double [[INC]], double* [[A6]], align 8
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// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK1-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK1-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK1-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK1-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK1-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK1-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK1-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK1-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK1-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 // CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
// CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK1-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK1-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK1-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK1-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK1-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK1-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 // CHECK1-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK1-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
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// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
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// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK2-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK2: omp.inner.for.end: // CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit: // CHECK2: omp.loop.exit:
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK2: omp.dispatch.cond: // CHECK2: omp.dispatch.cond:
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
// CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK2-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !22 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22
// CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22 // CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22
// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !22 // CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !22
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// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK2-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK2-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: store double [[ADD5]], double* [[A]], align 8 // CHECK2-NEXT: store double [[ADD5]], double* [[A]], align 8
// CHECK2-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 // CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8
// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK2-NEXT: store double [[INC]], double* [[A6]], align 8 // CHECK2-NEXT: store double [[INC]], double* [[A6]], align 8
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// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK2-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK2-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK2-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK2-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK2-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK2-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK2-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK2-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK2-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 // CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
// CHECK2-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK2-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK2-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK2-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK2-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK2-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK2-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK2-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 // CHECK2-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK2-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
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// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK2-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
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// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK3-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK3-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK3-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4
// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK3-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK3-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK3-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK3-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK3-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 // CHECK3-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK3-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK3-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
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// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
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// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK4-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK4-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK4-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK4-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK4-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK4-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK4-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4
// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK4-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK4-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK4-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK4-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK4-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 // CHECK4-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK4-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK4-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
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// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK4-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
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// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK9: omp.body.continue: // CHECK9: omp.body.continue:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK9: omp.body.continue: // CHECK9: omp.body.continue:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK9-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK9: omp.dispatch.cond: // CHECK9: omp.dispatch.cond:
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK9-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK9-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13 // CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK9-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !13 // CHECK9-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !13
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// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK9-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK9-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK9-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK9-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK9-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK9-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK9-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK9-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK9-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK9-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK9-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK9-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 // CHECK9-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK9-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 // CHECK9-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK9-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK9-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK9-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK9-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 // CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
// CHECK9-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK9-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK9-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK9-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK9-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK9-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 // CHECK9-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK9-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK9: omp.body.continue: // CHECK9: omp.body.continue:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
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// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK9-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK9-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK9-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK9-NEXT: store double [[ADD5]], double* [[A]], align 8 // CHECK9-NEXT: store double [[ADD5]], double* [[A]], align 8
// CHECK9-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK9-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8
// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK9-NEXT: store double [[INC]], double* [[A6]], align 8 // CHECK9-NEXT: store double [[INC]], double* [[A6]], align 8
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// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK9-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK9: omp.body.continue: // CHECK9: omp.body.continue:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
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// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK10: omp.body.continue: // CHECK10: omp.body.continue:
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK10: omp.body.continue: // CHECK10: omp.body.continue:
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK10-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK10: omp.dispatch.cond: // CHECK10: omp.dispatch.cond:
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK10-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK10-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13 // CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13 // CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK10-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !13 // CHECK10-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !13
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// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK10-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK10-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK10-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK10-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK10-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK10-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK10-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK10-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK10-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK10-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK10-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK10-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK10-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK10-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 // CHECK10-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK10-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 // CHECK10-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK10-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK10-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK10-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK10-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK10-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 // CHECK10-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
// CHECK10-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK10-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK10-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK10-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK10-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK10-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK10-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK10-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 // CHECK10-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK10-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK10-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK10: omp.body.continue: // CHECK10: omp.body.continue:
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK10-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK10-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK10-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK10-NEXT: store double [[ADD5]], double* [[A]], align 8 // CHECK10-NEXT: store double [[ADD5]], double* [[A]], align 8
// CHECK10-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK10-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 // CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8
// CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK10-NEXT: store double [[INC]], double* [[A6]], align 8 // CHECK10-NEXT: store double [[INC]], double* [[A6]], align 8
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// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK10-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK10: omp.body.continue: // CHECK10: omp.body.continue:
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
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// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK11: omp.inner.for.body: // CHECK11: omp.inner.for.body:
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK11-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue: // CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK11: omp.inner.for.inc: // CHECK11: omp.inner.for.inc:
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK11: omp.inner.for.body: // CHECK11: omp.inner.for.body:
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue: // CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK11: omp.inner.for.inc: // CHECK11: omp.inner.for.inc:
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK11-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK11-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK11-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK11-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK11-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK11-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK11-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 // CHECK11-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4
// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK11-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK11-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK11-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK11-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK11-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK11-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK11-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK11-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK11-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK11-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK11-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 // CHECK11-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK11-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue: // CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK11: omp.inner.for.inc: // CHECK11: omp.inner.for.inc:
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// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK11: omp.inner.for.body: // CHECK11: omp.inner.for.body:
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK11-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue: // CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK11: omp.inner.for.inc: // CHECK11: omp.inner.for.inc:
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// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK12: omp.inner.for.body: // CHECK12: omp.inner.for.body:
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK12-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK12: omp.body.continue: // CHECK12: omp.body.continue:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK12: omp.inner.for.inc: // CHECK12: omp.inner.for.inc:
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK12: omp.inner.for.body: // CHECK12: omp.inner.for.body:
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK12: omp.body.continue: // CHECK12: omp.body.continue:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK12: omp.inner.for.inc: // CHECK12: omp.inner.for.inc:
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK12-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK12-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK12-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK12-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK12-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK12-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK12-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 // CHECK12-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4
// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK12-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK12-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK12-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK12-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK12-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK12-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK12-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK12-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK12-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK12-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK12-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK12-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK12-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK12-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 // CHECK12-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK12-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK12-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK12: omp.body.continue: // CHECK12: omp.body.continue:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK12: omp.inner.for.inc: // CHECK12: omp.inner.for.inc:
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// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK12: omp.inner.for.body: // CHECK12: omp.inner.for.body:
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK12-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK12: omp.body.continue: // CHECK12: omp.body.continue:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK12: omp.inner.for.inc: // CHECK12: omp.inner.for.inc:
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// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK17-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 4
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK17: omp.inner.for.end: // CHECK17: omp.inner.for.end:
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK17: omp.loop.exit: // CHECK17: omp.loop.exit:
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK17-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK17: omp.dispatch.cond: // CHECK17: omp.dispatch.cond:
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK17-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !22 // CHECK17-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22 // CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !22 // CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !22
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// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK17-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK17-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: store double [[ADD5]], double* [[A]], align 8 // CHECK17-NEXT: store double [[ADD5]], double* [[A]], align 8
// CHECK17-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8
// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK17-NEXT: store double [[INC]], double* [[A6]], align 8 // CHECK17-NEXT: store double [[INC]], double* [[A6]], align 8
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// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK17-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK17-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK17-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK17-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK17-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK17-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK17-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK17-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK17-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK17-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 // CHECK17-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK17-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK17-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 // CHECK17-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 // CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
// CHECK17-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK17-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK17-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK17-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK17-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK17-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK17-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK17-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK17-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 // CHECK17-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK17-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 // CHECK17-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
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// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
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// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK18-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 4
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK18: omp.inner.for.end: // CHECK18: omp.inner.for.end:
// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK18: omp.loop.exit: // CHECK18: omp.loop.exit:
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK18-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK18-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK18: omp.dispatch.cond: // CHECK18: omp.dispatch.cond:
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK18-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !22 // CHECK18-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22 // CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22 // CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !22 // CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !22
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// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK18-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
// CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK18-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK18-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: store double [[ADD5]], double* [[A]], align 8 // CHECK18-NEXT: store double [[ADD5]], double* [[A]], align 8
// CHECK18-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 // CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8
// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK18-NEXT: store double [[INC]], double* [[A6]], align 8 // CHECK18-NEXT: store double [[INC]], double* [[A6]], align 8
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// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK18-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK18-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK18-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK18-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK18-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK18-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK18-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK18-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK18-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK18-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK18-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK18-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 // CHECK18-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK18-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK18-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 // CHECK18-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 // CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
// CHECK18-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK18-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK18-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK18-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK18-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK18-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK18-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK18-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK18-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 // CHECK18-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK18-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 // CHECK18-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
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// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
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// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK19: omp.inner.for.body: // CHECK19: omp.inner.for.body:
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK19-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue: // CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK19: omp.inner.for.inc: // CHECK19: omp.inner.for.inc:
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK19: omp.inner.for.body: // CHECK19: omp.inner.for.body:
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue: // CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK19: omp.inner.for.inc: // CHECK19: omp.inner.for.inc:
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK19-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK19-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK19-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK19-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 // CHECK19-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4
// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK19-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK19-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK19-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK19-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK19-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK19-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK19-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK19-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK19-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 // CHECK19-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK19-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK19-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 // CHECK19-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue: // CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK19: omp.inner.for.inc: // CHECK19: omp.inner.for.inc:
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// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK19: omp.inner.for.body: // CHECK19: omp.inner.for.body:
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue: // CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK19: omp.inner.for.inc: // CHECK19: omp.inner.for.inc:
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// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK20: omp.inner.for.body: // CHECK20: omp.inner.for.body:
// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK20-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue: // CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK20: omp.inner.for.inc: // CHECK20: omp.inner.for.inc:
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK20: omp.inner.for.body: // CHECK20: omp.inner.for.body:
// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue: // CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK20: omp.inner.for.inc: // CHECK20: omp.inner.for.inc:
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK20-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK20-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK20-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK20-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK20-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK20-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 // CHECK20-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4
// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK20-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK20-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK20-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK20-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK20-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK20-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK20-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK20-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK20-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK20-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 // CHECK20-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK20-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK20-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 // CHECK20-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue: // CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK20: omp.inner.for.inc: // CHECK20: omp.inner.for.inc:
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// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK20: omp.inner.for.body: // CHECK20: omp.inner.for.body:
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue: // CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK20: omp.inner.for.inc: // CHECK20: omp.inner.for.inc:
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// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK25: omp.inner.for.body: // CHECK25: omp.inner.for.body:
// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK25-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK25-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK25: omp.body.continue: // CHECK25: omp.body.continue:
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK25: omp.inner.for.inc: // CHECK25: omp.inner.for.inc:
// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK25-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK25: omp.inner.for.body: // CHECK25: omp.inner.for.body:
// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK25: omp.body.continue: // CHECK25: omp.body.continue:
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK25: omp.inner.for.inc: // CHECK25: omp.inner.for.inc:
// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK25-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK25-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 // CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK25-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK25-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK25: omp.dispatch.cond: // CHECK25: omp.dispatch.cond:
// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 // CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 // CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
// CHECK25-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK25-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK25-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK25: omp.inner.for.body: // CHECK25: omp.inner.for.body:
// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 // CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK25-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK25-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13 // CHECK25-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13
// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13 // CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13
// CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK25-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !13 // CHECK25-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !13
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// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK25-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK25-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK25-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK25-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK25-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK25-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK25-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK25-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK25-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK25-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK25-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK25-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK25-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK25-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK25-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK25-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK25: omp.inner.for.body: // CHECK25: omp.inner.for.body:
// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK25-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK25-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK25-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK25-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK25-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 // CHECK25-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK25-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK25-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 // CHECK25-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
// CHECK25-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK25-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK25-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK25-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK25-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK25-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 // CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
// CHECK25-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK25-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK25-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK25-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK25-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK25-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK25-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK25-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK25-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 // CHECK25-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK25-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK25: omp.body.continue: // CHECK25: omp.body.continue:
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK25: omp.inner.for.inc: // CHECK25: omp.inner.for.inc:
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// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK25-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK25-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
// CHECK25-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK25: omp.inner.for.body: // CHECK25: omp.inner.for.body:
// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK25-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK25-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK25-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK25-NEXT: store double [[ADD5]], double* [[A]], align 8 // CHECK25-NEXT: store double [[ADD5]], double* [[A]], align 8
// CHECK25-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK25-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 // CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8
// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK25-NEXT: store double [[INC]], double* [[A6]], align 8 // CHECK25-NEXT: store double [[INC]], double* [[A6]], align 8
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// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK25: omp.inner.for.body: // CHECK25: omp.inner.for.body:
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK25-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK25: omp.body.continue: // CHECK25: omp.body.continue:
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK25: omp.inner.for.inc: // CHECK25: omp.inner.for.inc:
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// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK26-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK26-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK26-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK26-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK26: omp.inner.for.body: // CHECK26: omp.inner.for.body:
// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK26-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK26-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK26: omp.body.continue: // CHECK26: omp.body.continue:
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK26: omp.inner.for.inc: // CHECK26: omp.inner.for.inc:
// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK26-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK26: omp.inner.for.body: // CHECK26: omp.inner.for.body:
// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK26: omp.body.continue: // CHECK26: omp.body.continue:
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK26: omp.inner.for.inc: // CHECK26: omp.inner.for.inc:
// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK26-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 // CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 // CHECK26-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 // CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) // CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
// CHECK26-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK26-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK26: omp.dispatch.cond: // CHECK26: omp.dispatch.cond:
// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 // CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 // CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
// CHECK26-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK26-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK26-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK26-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK26: omp.inner.for.body: // CHECK26: omp.inner.for.body:
// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 // CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
// CHECK26-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK26-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13 // CHECK26-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13
// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double // CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
// CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 // CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
// CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float // CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
// CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13 // CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13
// CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK26-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !13 // CHECK26-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !13
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// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK26-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK26-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK26-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK26-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK26-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK26-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK26-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK26-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK26-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK26-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK26-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK26-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK26-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK26-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK26-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK26-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK26-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK26-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK26: omp.inner.for.body: // CHECK26: omp.inner.for.body:
// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK26-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK26-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK26-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK26-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK26-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 // CHECK26-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK26-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK26-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8 // CHECK26-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
// CHECK26-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK26-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK26-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK26-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK26-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK26-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8 // CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
// CHECK26-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK26-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK26-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK26-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK26-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK26-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK26-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK26-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK26-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8 // CHECK26-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK26-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK26: omp.body.continue: // CHECK26: omp.body.continue:
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK26: omp.inner.for.inc: // CHECK26: omp.inner.for.inc:
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// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK26-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK26-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
// CHECK26-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK26-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK26: omp.inner.for.body: // CHECK26: omp.inner.for.body:
// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK26-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK26-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK26-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK26-NEXT: store double [[ADD5]], double* [[A]], align 8 // CHECK26-NEXT: store double [[ADD5]], double* [[A]], align 8
// CHECK26-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK26-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 // CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8
// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK26-NEXT: store double [[INC]], double* [[A6]], align 8 // CHECK26-NEXT: store double [[INC]], double* [[A6]], align 8
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// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK26: omp.inner.for.body: // CHECK26: omp.inner.for.body:
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8 // CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK26-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK26: omp.body.continue: // CHECK26: omp.body.continue:
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK26: omp.inner.for.inc: // CHECK26: omp.inner.for.inc:
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// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK27: omp.inner.for.body: // CHECK27: omp.inner.for.body:
// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK27-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK27: omp.body.continue: // CHECK27: omp.body.continue:
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK27: omp.inner.for.inc: // CHECK27: omp.inner.for.inc:
// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK27-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK27-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK27-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK27: omp.inner.for.body: // CHECK27: omp.inner.for.body:
// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK27: omp.body.continue: // CHECK27: omp.body.continue:
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK27: omp.inner.for.inc: // CHECK27: omp.inner.for.inc:
// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK27-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK27-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK27-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK27-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK27-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK27-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK27-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK27-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK27-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 // CHECK27-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4
// CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK27-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK27-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK27-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK27-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK27-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK27-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK27-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK27-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK27-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK27-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK27-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK27-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK27-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK27-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK27-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK27-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 // CHECK27-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK27-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK27-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK27-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK27: omp.body.continue: // CHECK27: omp.body.continue:
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK27: omp.inner.for.inc: // CHECK27: omp.inner.for.inc:
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// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK27: omp.inner.for.body: // CHECK27: omp.inner.for.body:
// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK27-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK27: omp.body.continue: // CHECK27: omp.body.continue:
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK27: omp.inner.for.inc: // CHECK27: omp.inner.for.inc:
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// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
// CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK28: omp.inner.for.body: // CHECK28: omp.inner.for.body:
// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK28-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK28: omp.body.continue: // CHECK28: omp.body.continue:
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK28: omp.inner.for.inc: // CHECK28: omp.inner.for.inc:
// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK28-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK28-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK28-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK28: omp.inner.for.body: // CHECK28: omp.inner.for.body:
// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK28: omp.body.continue: // CHECK28: omp.body.continue:
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK28: omp.inner.for.inc: // CHECK28: omp.inner.for.inc:
// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK28-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK28-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK28-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK28-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK28-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK28-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK28-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK28-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK28-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 // CHECK28-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4
// CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK28-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK28-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK28-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK28-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK28-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK28-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK28-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK28-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK28-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK28-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK28-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK28-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK28-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK28-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK28-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK28-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4 // CHECK28-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK28-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK28-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK28-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK28: omp.body.continue: // CHECK28: omp.body.continue:
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK28: omp.inner.for.inc: // CHECK28: omp.inner.for.inc:
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// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK28: omp.inner.for.body: // CHECK28: omp.inner.for.body:
// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4 // CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK28-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK28: omp.body.continue: // CHECK28: omp.body.continue:
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK28: omp.inner.for.inc: // CHECK28: omp.inner.for.inc:
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clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp

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// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 // CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
// CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 // CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 // CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 // CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
// CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 // CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
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clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp

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// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK9: omp.precond.then: // CHECK9: omp.precond.then:
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK9: omp.dispatch.cond: // CHECK9: omp.dispatch.cond:
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
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// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK10: omp.precond.then: // CHECK10: omp.precond.then:
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK10: omp.dispatch.cond: // CHECK10: omp.dispatch.cond:
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
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clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp

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// CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]]
// CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8*
// CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* // CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1
// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]]
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// CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]]
// CHECK2-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK2-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8*
// CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* // CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1
// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
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// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]]
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// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4
// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8
// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
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// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 // CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4
// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8
// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8
// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8
// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
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clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp

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// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[G_CASTED]] to double* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[G_CASTED]] to double*
// CHECK1-NEXT: store double [[TMP0]], double* [[CONV4]], align 8 // CHECK1-NEXT: store double [[TMP0]], double* [[CONV4]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load volatile double, double* [[TMP2]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load volatile double, double* [[TMP2]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[G1_CASTED]] to double* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK1-NEXT: store double [[TMP3]], double* [[CONV5]], align 8 // CHECK1-NEXT: store double [[TMP3]], double* [[CONV5]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV6]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 4
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float* // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK1-NEXT: store float [[TMP7]], float* [[CONV7]], align 4 // CHECK1-NEXT: store float [[TMP7]], float* [[CONV7]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK1: .omp.lastprivate.then: // CHECK1: .omp.lastprivate.then:
// CHECK1-NEXT: [[TMP18:%.*]] = load double, double* [[G5]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load double, double* [[G5]], align 8
// CHECK1-NEXT: store volatile double [[TMP18]], double* [[CONV]], align 8 // CHECK1-NEXT: store volatile double [[TMP18]], double* [[CONV]], align 8
// CHECK1-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP7]], align 8
// CHECK1-NEXT: [[TMP20:%.*]] = load double, double* [[TMP19]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load double, double* [[TMP19]], align 8
// CHECK1-NEXT: store volatile double [[TMP20]], double* [[TMP0]], align 8 // CHECK1-NEXT: store volatile double [[TMP20]], double* [[TMP0]], align 8
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK1-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8 // CHECK1-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR9]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR9]], align 4
// CHECK1-NEXT: store float [[TMP22]], float* [[CONV3]], align 8 // CHECK1-NEXT: store float [[TMP22]], float* [[CONV3]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done: // CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK1-SAME: () #[[ATTR4:[0-9]+]] { // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[G_CASTED]] to double* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[G_CASTED]] to double*
// CHECK2-NEXT: store double [[TMP0]], double* [[CONV4]], align 8 // CHECK2-NEXT: store double [[TMP0]], double* [[CONV4]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load volatile double, double* [[TMP2]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load volatile double, double* [[TMP2]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[G1_CASTED]] to double* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK2-NEXT: store double [[TMP3]], double* [[CONV5]], align 8 // CHECK2-NEXT: store double [[TMP3]], double* [[CONV5]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV6]], align 4 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 4
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float* // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK2-NEXT: store float [[TMP7]], float* [[CONV7]], align 4 // CHECK2-NEXT: store float [[TMP7]], float* [[CONV7]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-NEXT: br i1 [[TMP17]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP17]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK2: .omp.lastprivate.then: // CHECK2: .omp.lastprivate.then:
// CHECK2-NEXT: [[TMP18:%.*]] = load double, double* [[G5]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load double, double* [[G5]], align 8
// CHECK2-NEXT: store volatile double [[TMP18]], double* [[CONV]], align 8 // CHECK2-NEXT: store volatile double [[TMP18]], double* [[CONV]], align 8
// CHECK2-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP7]], align 8
// CHECK2-NEXT: [[TMP20:%.*]] = load double, double* [[TMP19]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load double, double* [[TMP19]], align 8
// CHECK2-NEXT: store volatile double [[TMP20]], double* [[TMP0]], align 8 // CHECK2-NEXT: store volatile double [[TMP20]], double* [[TMP0]], align 8
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK2-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8 // CHECK2-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR9]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR9]], align 4
// CHECK2-NEXT: store float [[TMP22]], float* [[CONV3]], align 8 // CHECK2-NEXT: store float [[TMP22]], float* [[CONV3]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done: // CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK2-SAME: () #[[ATTR4:[0-9]+]] { // CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK9-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 // CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
// CHECK9-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK9-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK9: .omp.lastprivate.then: // CHECK9: .omp.lastprivate.then:
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4
// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK9-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK9-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* // CHECK9-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false)
// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* // CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S*
// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2
// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP27]] // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP27]]
// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK9: omp.arraycpy.body: // CHECK9: omp.arraycpy.body:
// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK9-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK9-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
// CHECK9-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK9-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false)
// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]]
// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]]
// CHECK9: omp.arraycpy.done14: // CHECK9: omp.arraycpy.done14:
// CHECK9-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8
// CHECK9-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP3]] to i8* // CHECK9-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP3]] to i8*
// CHECK9-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8* // CHECK9-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false)
// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 8 // CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 4
// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK9: .omp.lastprivate.done: // CHECK9: .omp.lastprivate.done:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2
// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK9: arraydestroy.body: // CHECK9: arraydestroy.body:
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
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// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 // CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
// CHECK9-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK9-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK9: .omp.lastprivate.then: // CHECK9: .omp.lastprivate.then:
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4
// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK9-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK9-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* // CHECK9-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false)
// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* // CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2
// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP27]] // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP27]]
// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
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// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK10-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 // CHECK10-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 // CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 // CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
// CHECK10-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK10-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK10: .omp.lastprivate.then: // CHECK10: .omp.lastprivate.then:
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4
// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK10-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK10-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* // CHECK10-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false)
// CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 // CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* // CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S*
// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 // CHECK10-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2
// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP27]] // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP27]]
// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK10: omp.arraycpy.body: // CHECK10: omp.arraycpy.body:
// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK10-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK10-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
// CHECK10-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK10-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false)
// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]]
// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]]
// CHECK10: omp.arraycpy.done14: // CHECK10: omp.arraycpy.done14:
// CHECK10-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8
// CHECK10-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP3]] to i8* // CHECK10-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[TMP3]] to i8*
// CHECK10-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8* // CHECK10-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false)
// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 8 // CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 4
// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK10: .omp.lastprivate.done: // CHECK10: .omp.lastprivate.done:
// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
// CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
// CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2
// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK10: arraydestroy.body: // CHECK10: arraydestroy.body:
// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
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// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
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// CHECK10-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]]) // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 // CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
// CHECK10-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK10-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK10: .omp.lastprivate.then: // CHECK10: .omp.lastprivate.then:
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4
// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK10-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK10-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* // CHECK10-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false) // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false)
// CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 // CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* // CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
// CHECK10-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK10-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2
// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP27]] // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP27]]
// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
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clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp

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// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]])
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8
// CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]])
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
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// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK2-NEXT: store i32 0, i32* [[I]], align 4 // CHECK2-NEXT: store i32 0, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]])
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK2-NEXT: store i32 0, i32* [[I]], align 4 // CHECK2-NEXT: store i32 0, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8
// CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
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// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK2-NEXT: store i32 0, i32* [[I]], align 4 // CHECK2-NEXT: store i32 0, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]])
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
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// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK2-NEXT: store i32 0, i32* [[I]], align 4 // CHECK2-NEXT: store i32 0, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK3-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK3-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK3-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 // CHECK3-NEXT: store i32 0, i32* [[I]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK3-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK3-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK3-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK3-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK3-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK3-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK3-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]])
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 // CHECK3-NEXT: store i32 0, i32* [[I]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8
// CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8
// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
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// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 // CHECK3-NEXT: store i32 0, i32* [[I]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK3-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK3-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK3-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK3-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK3-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK3-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK3-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK3-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK3-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]])
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
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// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK3-NEXT: store i32 0, i32* [[I]], align 4 // CHECK3-NEXT: store i32 0, i32* [[I]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 // CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]])
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8
// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
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// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 // CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]])
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
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// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK11-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK11-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK11-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK11-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK11-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK11: omp.inner.for.body: // CHECK11: omp.inner.for.body:
// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK11-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK11-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK11-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK11-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK11-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 // CHECK11-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]])
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK11: omp.inner.for.inc: // CHECK11: omp.inner.for.inc:
// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK11-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK11-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK11-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK11-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8
// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8
// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK11-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
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// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK11: omp.inner.for.body: // CHECK11: omp.inner.for.body:
// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK11-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK11-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK11-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK11-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK11-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 // CHECK11-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]])
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK11: omp.inner.for.inc: // CHECK11: omp.inner.for.inc:
// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
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// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK11-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK11-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK11-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK11-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK11-NEXT: store i32 0, i32* [[I]], align 4 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp

Show First 20 Lines • Show All 1,111 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 // CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
// CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 // CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
Show All 38 Lines
// CHECK9: omp.inner.for.cond: // CHECK9: omp.inner.for.cond:
// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
// CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] // CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
// CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8
// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4 // CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4
// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* // CHECK9-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4 // CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4
// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8 // CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 // CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8
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// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 // CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
// CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 // CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 // CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 // CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
// CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 // CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
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// CHECK10: omp.inner.for.cond: // CHECK10: omp.inner.for.cond:
// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
// CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] // CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
// CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8
// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4 // CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4
// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* // CHECK10-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4 // CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4
// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8 // CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
// CHECK10-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 // CHECK10-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 // CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 // CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
// CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 // CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
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clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,627 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK9: omp.precond.then: // CHECK9: omp.precond.then:
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
// CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK9: cond.true: // CHECK9: cond.true:
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// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK9-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK9-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]
// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 // CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4
// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 // CHECK9-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4
// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]])
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15
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// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK9: cond.true: // CHECK9: cond.true:
// CHECK9-NEXT: br label [[COND_END:%.*]] // CHECK9-NEXT: br label [[COND_END:%.*]]
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// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK10: omp.precond.then: // CHECK10: omp.precond.then:
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK10: cond.true: // CHECK10: cond.true:
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// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK10-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK10-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]
// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 // CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4
// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 // CHECK10-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4
// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]])
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15
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// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK10: cond.true: // CHECK10: cond.true:
// CHECK10-NEXT: br label [[COND_END:%.*]] // CHECK10-NEXT: br label [[COND_END:%.*]]
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// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp

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// CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]])
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
// CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
// CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 // CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]])
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
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// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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// CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 // CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]])
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
// CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
// CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
// CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* // CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
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// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 // CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]])
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
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// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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// CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 // CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK5-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 // CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK5-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 // CHECK5-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4
// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 // CHECK5-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 // CHECK5-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc: // CHECK5: omp.inner.for.inc:
// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK5-NEXT: store i32 1, i32* [[CONV]], align 8 // CHECK5-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 // CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
// CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 // CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 // CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8
// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
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// CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 // CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK6-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 // CHECK6-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK6-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 // CHECK6-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4
// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 // CHECK6-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 // CHECK6-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK6: omp.inner.for.inc: // CHECK6: omp.inner.for.inc:
// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK6-NEXT: store i32 1, i32* [[CONV]], align 8 // CHECK6-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 // CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
// CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 // CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 // CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8
// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
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// CHECK13-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK13-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK13-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK13-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK13-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK13-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK13-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK13: omp.inner.for.cond.cleanup: // CHECK13: omp.inner.for.cond.cleanup:
// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK13-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 // CHECK13-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 // CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]])
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK13: omp.inner.for.cond.cleanup: // CHECK13: omp.inner.for.cond.cleanup:
// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK13-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 // CHECK13-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
// CHECK13-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK13-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
// CHECK13-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* // CHECK13-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] // CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
// CHECK13-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 // CHECK13-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4
// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK13: omp.body.continue: // CHECK13: omp.body.continue:
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
// CHECK13-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK13-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK13-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK13-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK13: omp.inner.for.cond.cleanup: // CHECK13: omp.inner.for.cond.cleanup:
// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 // CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK13-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 // CHECK13-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]])
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
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// CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK13: omp.inner.for.cond.cleanup: // CHECK13: omp.inner.for.cond.cleanup:
// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK13-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 // CHECK13-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
// CHECK13-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 // CHECK13-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
// CHECK13-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK13-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
// CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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// CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK14-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK14: omp.inner.for.cond.cleanup: // CHECK14: omp.inner.for.cond.cleanup:
// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK14-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 // CHECK14-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 // CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]])
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK14-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK14: omp.inner.for.cond.cleanup: // CHECK14: omp.inner.for.cond.cleanup:
// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK14-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 // CHECK14-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK14-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK14-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
// CHECK14-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK14-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
// CHECK14-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK14-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
// CHECK14-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* // CHECK14-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] // CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
// CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 // CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4
// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK14: omp.body.continue: // CHECK14: omp.body.continue:
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
// CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK14-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK14-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
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// CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK14: omp.inner.for.cond.cleanup: // CHECK14: omp.inner.for.cond.cleanup:
// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 // CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK14-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 // CHECK14-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]])
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
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// CHECK14-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK14: omp.inner.for.cond.cleanup: // CHECK14: omp.inner.for.cond.cleanup:
// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK14-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 // CHECK14-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
// CHECK14-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 // CHECK14-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
// CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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// CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK17-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK17-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK17-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK17-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK17-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK17-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 // CHECK17-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK17-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 // CHECK17-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 // CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 // CHECK17-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
// CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK17-NEXT: store i32 1, i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK17-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 // CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
// CHECK17-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK17-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
// CHECK17-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 // CHECK17-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1
// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2
// CHECK17-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 // CHECK17-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8
// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]] // CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]]
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clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp

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// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90
// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.else: // CHECK1: omp_if.else:
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68
// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.else: // CHECK1: omp_if.else:
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 747 Lines • ▼ Show 20 Lines
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90
// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
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// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.else: // CHECK2: omp_if.else:
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 425 Lines • ▼ Show 20 Lines
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68
// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.else: // CHECK2: omp_if.else:
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 747 Lines • ▼ Show 20 Lines
// //
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90
// CHECK5-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK5-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK5: omp_if.then: // CHECK5: omp_if.then:
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK5: omp_if.else: // CHECK5: omp_if.else:
// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK5-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 425 Lines • ▼ Show 20 Lines
// //
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68
// CHECK5-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK5-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
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// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK5: omp_if.then: // CHECK5: omp_if.then:
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK5: omp_if.else: // CHECK5: omp_if.else:
// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK5-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 747 Lines • ▼ Show 20 Lines
// //
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90
// CHECK6-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK6-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK6-NEXT: entry: // CHECK6-NEXT: entry:
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK6: omp_if.then: // CHECK6: omp_if.then:
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK6-NEXT: br label [[OMP_IF_END:%.*]] // CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK6: omp_if.else: // CHECK6: omp_if.else:
// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK6-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 425 Lines • ▼ Show 20 Lines
// //
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68
// CHECK6-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK6-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK6-NEXT: entry: // CHECK6-NEXT: entry:
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK6: omp_if.then: // CHECK6: omp_if.then:
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK6-NEXT: br label [[OMP_IF_END:%.*]] // CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK6: omp_if.else: // CHECK6: omp_if.else:
// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK6-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 747 Lines • ▼ Show 20 Lines
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90
// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then: // CHECK9: omp_if.then:
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK9: omp_if.else: // CHECK9: omp_if.else:
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68
// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
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// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then: // CHECK9: omp_if.then:
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK9: omp_if.else: // CHECK9: omp_if.else:
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90
// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then: // CHECK10: omp_if.then:
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK10: omp_if.else: // CHECK10: omp_if.else:
// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 425 Lines • ▼ Show 20 Lines
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68
// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then: // CHECK10: omp_if.then:
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK10: omp_if.else: // CHECK10: omp_if.else:
// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 747 Lines • ▼ Show 20 Lines
// //
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90
// CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
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// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK13: omp_if.then: // CHECK13: omp_if.then:
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK13-NEXT: br label [[OMP_IF_END:%.*]] // CHECK13-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK13: omp_if.else: // CHECK13: omp_if.else:
// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// //
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68
// CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
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// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK13: omp_if.then: // CHECK13: omp_if.then:
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK13-NEXT: br label [[OMP_IF_END:%.*]] // CHECK13-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK13: omp_if.else: // CHECK13: omp_if.else:
// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// //
// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90
// CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK14-NEXT: entry: // CHECK14-NEXT: entry:
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK14-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
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// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK14: omp_if.then: // CHECK14: omp_if.then:
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK14-NEXT: br label [[OMP_IF_END:%.*]] // CHECK14-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK14: omp_if.else: // CHECK14: omp_if.else:
// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 425 Lines • ▼ Show 20 Lines
// //
// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68
// CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK14-NEXT: entry: // CHECK14-NEXT: entry:
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK14-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
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// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK14: omp_if.then: // CHECK14: omp_if.then:
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK14-NEXT: br label [[OMP_IF_END:%.*]] // CHECK14-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK14: omp_if.else: // CHECK14: omp_if.else:
// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp

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// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double*
// CHECK1-NEXT: store double* [[CONV]], double** [[TMP]], align 8 // CHECK1-NEXT: store double* [[CONV]], double** [[TMP]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile double, double* [[TMP0]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile double, double* [[TMP0]], align 8
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK1-NEXT: store double [[TMP1]], double* [[CONV4]], align 8 // CHECK1-NEXT: store double [[TMP1]], double* [[CONV4]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK1-NEXT: store float [[TMP5]], float* [[CONV6]], align 4 // CHECK1-NEXT: store float [[TMP5]], float* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load double, double* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load double, double* [[CONV3]], align 8
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[G_CASTED]] to double* // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[G_CASTED]] to double*
// CHECK1-NEXT: store double [[TMP7]], double* [[CONV7]], align 8 // CHECK1-NEXT: store double [[TMP7]], double* [[CONV7]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]])
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// CHECK1-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK1: .omp.lastprivate.then: // CHECK1: .omp.lastprivate.then:
// CHECK1-NEXT: [[TMP25:%.*]] = load double, double* [[G5]], align 8 // CHECK1-NEXT: [[TMP25:%.*]] = load double, double* [[G5]], align 8
// CHECK1-NEXT: store volatile double [[TMP25]], double* [[CONV3]], align 8 // CHECK1-NEXT: store volatile double [[TMP25]], double* [[CONV3]], align 8
// CHECK1-NEXT: [[TMP26:%.*]] = load double*, double** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP26:%.*]] = load double*, double** [[_TMP7]], align 8
// CHECK1-NEXT: [[TMP27:%.*]] = load double, double* [[TMP26]], align 8 // CHECK1-NEXT: [[TMP27:%.*]] = load double, double* [[TMP26]], align 8
// CHECK1-NEXT: store volatile double [[TMP27]], double* [[TMP0]], align 8 // CHECK1-NEXT: store volatile double [[TMP27]], double* [[TMP0]], align 8
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK1-NEXT: store i32 [[TMP28]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[TMP28]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP29:%.*]] = load float, float* [[SFVAR9]], align 4 // CHECK1-NEXT: [[TMP29:%.*]] = load float, float* [[SFVAR9]], align 4
// CHECK1-NEXT: store float [[TMP29]], float* [[CONV2]], align 8 // CHECK1-NEXT: store float [[TMP29]], float* [[CONV2]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done: // CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK1: .omp.lastprivate.then: // CHECK1: .omp.lastprivate.then:
// CHECK1-NEXT: [[TMP20:%.*]] = load double, double* [[G7]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load double, double* [[G7]], align 8
// CHECK1-NEXT: store volatile double [[TMP20]], double* [[CONV3]], align 8 // CHECK1-NEXT: store volatile double [[TMP20]], double* [[CONV3]], align 8
// CHECK1-NEXT: [[TMP21:%.*]] = load double*, double** [[_TMP9]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load double*, double** [[_TMP9]], align 8
// CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8
// CHECK1-NEXT: store volatile double [[TMP22]], double* [[TMP2]], align 8 // CHECK1-NEXT: store volatile double [[TMP22]], double* [[TMP2]], align 8
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR10]], align 4 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR10]], align 4
// CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR11]], align 4 // CHECK1-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR11]], align 4
// CHECK1-NEXT: store float [[TMP24]], float* [[CONV2]], align 8 // CHECK1-NEXT: store float [[TMP24]], float* [[CONV2]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done: // CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK1-SAME: () #[[ATTR4:[0-9]+]] { // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double*
// CHECK2-NEXT: store double* [[CONV]], double** [[TMP]], align 8 // CHECK2-NEXT: store double* [[CONV]], double** [[TMP]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load volatile double, double* [[TMP0]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile double, double* [[TMP0]], align 8
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK2-NEXT: store double [[TMP1]], double* [[CONV4]], align 8 // CHECK2-NEXT: store double [[TMP1]], double* [[CONV4]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK2-NEXT: store float [[TMP5]], float* [[CONV6]], align 4 // CHECK2-NEXT: store float [[TMP5]], float* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load double, double* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load double, double* [[CONV3]], align 8
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[G_CASTED]] to double* // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[G_CASTED]] to double*
// CHECK2-NEXT: store double [[TMP7]], double* [[CONV7]], align 8 // CHECK2-NEXT: store double [[TMP7]], double* [[CONV7]], align 8
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]])
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// CHECK2-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK2: .omp.lastprivate.then: // CHECK2: .omp.lastprivate.then:
// CHECK2-NEXT: [[TMP25:%.*]] = load double, double* [[G5]], align 8 // CHECK2-NEXT: [[TMP25:%.*]] = load double, double* [[G5]], align 8
// CHECK2-NEXT: store volatile double [[TMP25]], double* [[CONV3]], align 8 // CHECK2-NEXT: store volatile double [[TMP25]], double* [[CONV3]], align 8
// CHECK2-NEXT: [[TMP26:%.*]] = load double*, double** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP26:%.*]] = load double*, double** [[_TMP7]], align 8
// CHECK2-NEXT: [[TMP27:%.*]] = load double, double* [[TMP26]], align 8 // CHECK2-NEXT: [[TMP27:%.*]] = load double, double* [[TMP26]], align 8
// CHECK2-NEXT: store volatile double [[TMP27]], double* [[TMP0]], align 8 // CHECK2-NEXT: store volatile double [[TMP27]], double* [[TMP0]], align 8
// CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK2-NEXT: store i32 [[TMP28]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[TMP28]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP29:%.*]] = load float, float* [[SFVAR9]], align 4 // CHECK2-NEXT: [[TMP29:%.*]] = load float, float* [[SFVAR9]], align 4
// CHECK2-NEXT: store float [[TMP29]], float* [[CONV2]], align 8 // CHECK2-NEXT: store float [[TMP29]], float* [[CONV2]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done: // CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK2: .omp.lastprivate.then: // CHECK2: .omp.lastprivate.then:
// CHECK2-NEXT: [[TMP20:%.*]] = load double, double* [[G7]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load double, double* [[G7]], align 8
// CHECK2-NEXT: store volatile double [[TMP20]], double* [[CONV3]], align 8 // CHECK2-NEXT: store volatile double [[TMP20]], double* [[CONV3]], align 8
// CHECK2-NEXT: [[TMP21:%.*]] = load double*, double** [[_TMP9]], align 8 // CHECK2-NEXT: [[TMP21:%.*]] = load double*, double** [[_TMP9]], align 8
// CHECK2-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8 // CHECK2-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8
// CHECK2-NEXT: store volatile double [[TMP22]], double* [[TMP2]], align 8 // CHECK2-NEXT: store volatile double [[TMP22]], double* [[TMP2]], align 8
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR10]], align 4 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR10]], align 4
// CHECK2-NEXT: store i32 [[TMP23]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[TMP23]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR11]], align 4 // CHECK2-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR11]], align 4
// CHECK2-NEXT: store float [[TMP24]], float* [[CONV2]], align 8 // CHECK2-NEXT: store float [[TMP24]], float* [[CONV2]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done: // CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK2-SAME: () #[[ATTR4:[0-9]+]] { // CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 // CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 // CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK5-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 // CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
// CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then: // CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4
// CHECK5-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 8 // CHECK5-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* // CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false)
// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* // CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S*
// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2
// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP30]] // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP30]]
// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK5: omp.arraycpy.body: // CHECK5: omp.arraycpy.body:
// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
// CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false)
// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]]
// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]]
// CHECK5: omp.arraycpy.done13: // CHECK5: omp.arraycpy.done13:
// CHECK5-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 // CHECK5-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8
// CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP3]] to i8* // CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP3]] to i8*
// CHECK5-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8* // CHECK5-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false)
// CHECK5-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK5-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK5-NEXT: store i32 [[TMP36]], i32* [[CONV1]], align 8 // CHECK5-NEXT: store i32 [[TMP36]], i32* [[CONV1]], align 4
// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK5: .omp.lastprivate.done: // CHECK5: .omp.lastprivate.done:
// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
// CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
// CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK5: arraydestroy.body: // CHECK5: arraydestroy.body:
// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
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// CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK5-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 // CHECK5-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
// CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then: // CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR5]], align 4 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR5]], align 4
// CHECK5-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8 // CHECK5-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8* // CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
// CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR7]] to %struct.S* // CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR7]] to %struct.S*
// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2
// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN15]], [[TMP29]] // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN15]], [[TMP29]]
// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE16:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE16:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK5: omp.arraycpy.body: // CHECK5: omp.arraycpy.body:
// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN15]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN15]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
// CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false)
// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE16]], label [[OMP_ARRAYCPY_BODY]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE16]], label [[OMP_ARRAYCPY_BODY]]
// CHECK5: omp.arraycpy.done16: // CHECK5: omp.arraycpy.done16:
// CHECK5-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8 // CHECK5-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8
// CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8* // CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8*
// CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* // CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
// CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR10]], align 4 // CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR10]], align 4
// CHECK5-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 8 // CHECK5-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 4
// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK5: .omp.lastprivate.done: // CHECK5: .omp.lastprivate.done:
// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]]
// CHECK5-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0
// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2
// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK5: arraydestroy.body: // CHECK5: arraydestroy.body:
// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
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// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
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// CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4
// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 // CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
// CHECK5-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK5-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then: // CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4
// CHECK5-NEXT: store i32 [[TMP24]], i32* [[CONV]], align 8 // CHECK5-NEXT: store i32 [[TMP24]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK5-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* // CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false)
// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* // CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2
// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP28]] // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP28]]
// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
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// CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK5-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 // CHECK5-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
// CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then: // CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR4]], align 4 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR4]], align 4
// CHECK5-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8 // CHECK5-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8* // CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
// CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR6]] to %struct.S.0* // CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR6]] to %struct.S.0*
// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2
// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN13]], [[TMP29]] // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN13]], [[TMP29]]
// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
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// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 // CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 // CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4 // CHECK6-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK6-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 // CHECK6-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
// CHECK6-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK6-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then: // CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4
// CHECK6-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 8 // CHECK6-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* // CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false)
// CHECK6-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 // CHECK6-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* // CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S*
// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK6-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2
// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP30]] // CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP30]]
// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK6: omp.arraycpy.body: // CHECK6: omp.arraycpy.body:
// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
// CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false)
// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]] // CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]]
// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]]
// CHECK6: omp.arraycpy.done13: // CHECK6: omp.arraycpy.done13:
// CHECK6-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 // CHECK6-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8
// CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP3]] to i8* // CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP3]] to i8*
// CHECK6-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8* // CHECK6-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false)
// CHECK6-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK6-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK6-NEXT: store i32 [[TMP36]], i32* [[CONV1]], align 8 // CHECK6-NEXT: store i32 [[TMP36]], i32* [[CONV1]], align 4
// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK6: .omp.lastprivate.done: // CHECK6: .omp.lastprivate.done:
// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
// CHECK6-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK6-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
// CHECK6-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK6-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK6: arraydestroy.body: // CHECK6: arraydestroy.body:
// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
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// CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 // CHECK6-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
// CHECK6-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK6-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then: // CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR5]], align 4 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR5]], align 4
// CHECK6-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8 // CHECK6-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8* // CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
// CHECK6-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 // CHECK6-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR7]] to %struct.S* // CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR7]] to %struct.S*
// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK6-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2
// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN15]], [[TMP29]] // CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN15]], [[TMP29]]
// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE16:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE16:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK6: omp.arraycpy.body: // CHECK6: omp.arraycpy.body:
// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN15]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN15]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK6-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK6-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
// CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false)
// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] // CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE16]], label [[OMP_ARRAYCPY_BODY]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE16]], label [[OMP_ARRAYCPY_BODY]]
// CHECK6: omp.arraycpy.done16: // CHECK6: omp.arraycpy.done16:
// CHECK6-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8 // CHECK6-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8
// CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8* // CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8*
// CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* // CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR10]], align 4 // CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR10]], align 4
// CHECK6-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 8 // CHECK6-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 4
// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK6: .omp.lastprivate.done: // CHECK6: .omp.lastprivate.done:
// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]] // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]]
// CHECK6-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0 // CHECK6-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0
// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 // CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2
// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK6: arraydestroy.body: // CHECK6: arraydestroy.body:
// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
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// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
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// CHECK6-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4
// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 // CHECK6-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
// CHECK6-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK6-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then: // CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4
// CHECK6-NEXT: store i32 [[TMP24]], i32* [[CONV]], align 8 // CHECK6-NEXT: store i32 [[TMP24]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK6-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* // CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false)
// CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 // CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* // CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 // CHECK6-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2
// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP28]] // CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP28]]
// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
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// CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 // CHECK6-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
// CHECK6-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK6-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then: // CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR4]], align 4 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR4]], align 4
// CHECK6-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8 // CHECK6-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8* // CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
// CHECK6-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 // CHECK6-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR6]] to %struct.S.0* // CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR6]] to %struct.S.0*
// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK6-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2
// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN13]], [[TMP29]] // CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN13]], [[TMP29]]
// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
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clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp

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// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK13: omp.precond.then: // CHECK13: omp.precond.then:
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK13-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK13-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
// CHECK13-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK13-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK13: cond.true: // CHECK13: cond.true:
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// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK13-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK13-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]
// CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK13-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 // CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4
// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 // CHECK13-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4
// CHECK13-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]])
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8
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// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK13-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4 // CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4 // CHECK13-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4
// CHECK13-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]])
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK13: omp.precond.then: // CHECK13: omp.precond.then:
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 // CHECK13-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32
// CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK13-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK13-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) // CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]])
// CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK13: omp.dispatch.cond: // CHECK13: omp.dispatch.cond:
// CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..21 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..21
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// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK13: omp.dispatch.cond: // CHECK13: omp.dispatch.cond:
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK13-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..29 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..29
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// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK13: omp.dispatch.cond: // CHECK13: omp.dispatch.cond:
// CHECK13-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK13-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
Show All 36 Lines
// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK14: omp.precond.then: // CHECK14: omp.precond.then:
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK14-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK14-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
// CHECK14-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK14-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK14: cond.true: // CHECK14: cond.true:
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// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK14-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK14-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]
// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK14-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 // CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4
// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 // CHECK14-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4
// CHECK14-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]])
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8
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// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK14-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4 // CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4 // CHECK14-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4
// CHECK14-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]])
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK14: omp.precond.then: // CHECK14: omp.precond.then:
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 // CHECK14-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32
// CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK14-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK14-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) // CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]])
// CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK14: omp.dispatch.cond: // CHECK14: omp.dispatch.cond:
// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK14-NEXT: entry: // CHECK14-NEXT: entry:
// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..21 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..21
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// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK14: omp.dispatch.cond: // CHECK14: omp.dispatch.cond:
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK14-NEXT: entry: // CHECK14-NEXT: entry:
// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..29 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..29
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// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK14: omp.dispatch.cond: // CHECK14: omp.dispatch.cond:
// CHECK14-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK14-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK17: omp.precond.then: // CHECK17: omp.precond.then:
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
// CHECK17-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK17-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK17: cond.true: // CHECK17: cond.true:
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// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK17-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK17-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]
// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK17-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK17-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 // CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4
// CHECK17-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 // CHECK17-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4
// CHECK17-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]])
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8
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// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4 // CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4 // CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4
// CHECK17-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]])
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK17: omp.precond.then: // CHECK17: omp.precond.then:
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 // CHECK17-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32
// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) // CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]])
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK17: omp.dispatch.cond: // CHECK17: omp.dispatch.cond:
// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..21 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..21
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// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK17: omp.dispatch.cond: // CHECK17: omp.dispatch.cond:
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK17-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..29 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..29
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// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK17: omp.dispatch.cond: // CHECK17: omp.dispatch.cond:
// CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK18: omp.precond.then: // CHECK18: omp.precond.then:
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK18-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK18-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
// CHECK18-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK18-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK18: cond.true: // CHECK18: cond.true:
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// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK18-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK18-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]
// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK18-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK18-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK18-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 // CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4
// CHECK18-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 // CHECK18-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4
// CHECK18-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]])
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8
Show All 18 Lines
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
Show All 29 Lines
// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 // CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
Show All 36 Lines
// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
Show All 22 Lines
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4 // CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4 // CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4
// CHECK18-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]])
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK18: omp.precond.then: // CHECK18: omp.precond.then:
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 // CHECK18-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32
// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK18-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK18-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) // CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]])
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK18: omp.dispatch.cond: // CHECK18: omp.dispatch.cond:
// CHECK18-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..21 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..21
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// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK18: omp.dispatch.cond: // CHECK18: omp.dispatch.cond:
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK18-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..29 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..29
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// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK18: omp.dispatch.cond: // CHECK18: omp.dispatch.cond:
// CHECK18-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK18-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp

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// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[I_CASTED]] to i32* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[I_CASTED]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[I_CASTED]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4
// CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32]* [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32]* [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 // CHECK1-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I4]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I4]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[I_CASTED]] to i32* // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[I_CASTED]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[I_CASTED]], align 8
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32]* [[TMP0]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32]* [[TMP0]])
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
// CHECK1-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK1: .omp.final.then: // CHECK1: .omp.final.then:
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0 // CHECK1-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0
// CHECK1-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 // CHECK1-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 4
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK1: .omp.final.done: // CHECK1: .omp.final.done:
// CHECK1-NEXT: br label [[OMP_PRECOND_END]] // CHECK1-NEXT: br label [[OMP_PRECOND_END]]
// CHECK1: omp.precond.end: // CHECK1: omp.precond.end:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 // CHECK1-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I4]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I4]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK1: omp.precond.then: // CHECK1: omp.precond.then:
// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 0 // CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 0
// CHECK1-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ] // CHECK1-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32
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// CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
// CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK1: .omp.final.then: // CHECK1: .omp.final.then:
// CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0 // CHECK1-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0
// CHECK1-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 // CHECK1-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
// CHECK1-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1 // CHECK1-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1
// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]] // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
// CHECK1-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 4
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK1: .omp.final.done: // CHECK1: .omp.final.done:
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 // CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
// CHECK1-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK1: .omp.linear.pu: // CHECK1: .omp.linear.pu:
// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK1: .omp.linear.pu.done: // CHECK1: .omp.linear.pu.done:
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// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8
// CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !11 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !11 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !11
// CHECK1-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !11 // CHECK1-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !11
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]), !llvm.access.group !11 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]), !llvm.access.group !11
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
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// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK1-NEXT: store i32 0, i32* [[I]], align 4 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[I_CASTED]] to i32* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[I_CASTED]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[I_CASTED]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4
// CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32]* [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32]* [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 // CHECK2-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK2-NEXT: store i32 0, i32* [[I4]], align 4 // CHECK2-NEXT: store i32 0, i32* [[I4]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[I_CASTED]] to i32* // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[I_CASTED]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[I_CASTED]], align 8
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 // CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32]* [[TMP0]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32]* [[TMP0]])
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK2-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 // CHECK2-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
// CHECK2-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK2: .omp.final.then: // CHECK2: .omp.final.then:
// CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0 // CHECK2-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0
// CHECK2-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 // CHECK2-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1
// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 4
// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK2: .omp.final.done: // CHECK2: .omp.final.done:
// CHECK2-NEXT: br label [[OMP_PRECOND_END]] // CHECK2-NEXT: br label [[OMP_PRECOND_END]]
// CHECK2: omp.precond.end: // CHECK2: omp.precond.end:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 // CHECK2-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK2-NEXT: store i32 0, i32* [[I4]], align 4 // CHECK2-NEXT: store i32 0, i32* [[I4]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK2: omp.precond.then: // CHECK2: omp.precond.then:
// CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 0 // CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 0
// CHECK2-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ] // CHECK2-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK2-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32
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// CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 // CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
// CHECK2-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK2: .omp.final.then: // CHECK2: .omp.final.then:
// CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0 // CHECK2-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0
// CHECK2-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 // CHECK2-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
// CHECK2-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1 // CHECK2-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1
// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]] // CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
// CHECK2-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 4
// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK2: .omp.final.done: // CHECK2: .omp.final.done:
// CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 // CHECK2-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
// CHECK2-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK2: .omp.linear.pu: // CHECK2: .omp.linear.pu:
// CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK2: .omp.linear.pu.done: // CHECK2: .omp.linear.pu.done:
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// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8
// CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
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// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK2-NEXT: store i32 0, i32* [[I]], align 4 // CHECK2-NEXT: store i32 0, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !11 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !11 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !11
// CHECK2-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !11 // CHECK2-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !11
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]), !llvm.access.group !11 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]), !llvm.access.group !11
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
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// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK2-NEXT: store i32 0, i32* [[I]], align 4 // CHECK2-NEXT: store i32 0, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[I_CASTED]] to i32* // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[I_CASTED]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[I_CASTED]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32]* [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32]* [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 // CHECK9-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I4]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I4]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4
// CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[I_CASTED]] to i32* // CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 // CHECK9-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[I_CASTED]], align 8 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[I_CASTED]], align 8
// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV9:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV9:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 // CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32]* [[TMP0]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32]* [[TMP0]])
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK9-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 // CHECK9-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
// CHECK9-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK9-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK9: .omp.final.then: // CHECK9: .omp.final.then:
// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0 // CHECK9-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0
// CHECK9-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 // CHECK9-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1
// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 4
// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK9: .omp.final.done: // CHECK9: .omp.final.done:
// CHECK9-NEXT: br label [[OMP_PRECOND_END]] // CHECK9-NEXT: br label [[OMP_PRECOND_END]]
// CHECK9: omp.precond.end: // CHECK9: omp.precond.end:
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 // CHECK9-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I4]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I4]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK9: omp.precond.then: // CHECK9: omp.precond.then:
// CHECK9-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 0 // CHECK9-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 0
// CHECK9-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ] // CHECK9-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK9-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32
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// CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 // CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
// CHECK9-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK9-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK9: .omp.final.then: // CHECK9: .omp.final.then:
// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0 // CHECK9-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0
// CHECK9-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 // CHECK9-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
// CHECK9-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1 // CHECK9-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1
// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]] // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
// CHECK9-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 4
// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK9: .omp.final.done: // CHECK9: .omp.final.done:
// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 // CHECK9-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
// CHECK9-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK9-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK9: .omp.linear.pu: // CHECK9: .omp.linear.pu:
// CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK9: .omp.linear.pu.done: // CHECK9: .omp.linear.pu.done:
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// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8
// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12
// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12
// CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12
// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !12 // CHECK9-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !12
// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !12 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !12
// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !12 // CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !12
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]), !llvm.access.group !12 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]), !llvm.access.group !12
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
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// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[I_CASTED]] to i32* // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[I_CASTED]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[I_CASTED]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32]* [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], i64 [[TMP7]], [1000 x i32]* [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 // CHECK10-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I4]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I4]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4
// CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[I_CASTED]] to i32* // CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 // CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[I_CASTED]], align 8 // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[I_CASTED]], align 8
// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 // CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32]* [[TMP0]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], [1000 x i32]* [[TMP0]])
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK10-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 // CHECK10-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
// CHECK10-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK10-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK10: .omp.final.then: // CHECK10: .omp.final.then:
// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0 // CHECK10-NEXT: [[SUB10:%.*]] = sub nsw i32 [[TMP28]], 0
// CHECK10-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1 // CHECK10-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1
// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]] // CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 4
// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK10: .omp.final.done: // CHECK10: .omp.final.done:
// CHECK10-NEXT: br label [[OMP_PRECOND_END]] // CHECK10-NEXT: br label [[OMP_PRECOND_END]]
// CHECK10: omp.precond.end: // CHECK10: omp.precond.end:
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 // CHECK10-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I4]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I4]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK10: omp.precond.then: // CHECK10: omp.precond.then:
// CHECK10-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 0 // CHECK10-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 0
// CHECK10-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ] // CHECK10-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK10-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP8]] to i32
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// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 // CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
// CHECK10-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK10-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK10: .omp.final.then: // CHECK10: .omp.final.then:
// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0 // CHECK10-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP27]], 0
// CHECK10-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 // CHECK10-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
// CHECK10-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1 // CHECK10-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1
// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]] // CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
// CHECK10-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 4
// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK10: .omp.final.done: // CHECK10: .omp.final.done:
// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 // CHECK10-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
// CHECK10-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK10-NEXT: br i1 [[TMP29]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK10: .omp.linear.pu: // CHECK10: .omp.linear.pu:
// CHECK10-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK10-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK10: .omp.linear.pu.done: // CHECK10: .omp.linear.pu.done:
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// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8
// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
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// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12
// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12
// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12
// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !12 // CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !12
// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !12 // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !12
// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !12 // CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !12
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]), !llvm.access.group !12 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]), !llvm.access.group !12
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
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// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp

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Show First 20 Lines • Show All 1,455 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 // CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
// CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 // CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
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// CHECK9: omp.inner.for.cond: // CHECK9: omp.inner.for.cond:
// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5
// CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5 // CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5
// CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] // CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
// CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5
// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK9-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4, !llvm.access.group !5 // CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4, !llvm.access.group !5
// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !5 // CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !5
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8, !llvm.access.group !5 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 4, !llvm.access.group !5
// CHECK9-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* // CHECK9-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4, !llvm.access.group !5 // CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4, !llvm.access.group !5
// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8, !llvm.access.group !5 // CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8, !llvm.access.group !5
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !5 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !5
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5
// CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !llvm.access.group !5 // CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !llvm.access.group !5
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// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 // CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
// CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 // CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 // CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 // CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
// CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 // CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
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// CHECK10: omp.inner.for.cond: // CHECK10: omp.inner.for.cond:
// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5
// CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5 // CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5
// CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] // CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
// CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5 // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5
// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5 // CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK10-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4, !llvm.access.group !5 // CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4, !llvm.access.group !5
// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !5 // CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !5
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8, !llvm.access.group !5 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 4, !llvm.access.group !5
// CHECK10-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* // CHECK10-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4, !llvm.access.group !5 // CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4, !llvm.access.group !5
// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8, !llvm.access.group !5 // CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8, !llvm.access.group !5
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !5 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !5
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 // CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5
// CHECK10-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !llvm.access.group !5 // CHECK10-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !llvm.access.group !5
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 // CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 // CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
// CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 // CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !9 // CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !9 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !9
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !9 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !9
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
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// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !18 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !18
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !18 // CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !18
// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !18 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !18
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !18 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !18
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18
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// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK9: omp.precond.then: // CHECK9: omp.precond.then:
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
// CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK9: cond.true: // CHECK9: cond.true:
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// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK9-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK9-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]
// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !24 // CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !24 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !24
// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !24 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !24 // CHECK9-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24 // CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]), !llvm.access.group !24 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]), !llvm.access.group !24
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
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// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15
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// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK9: cond.true: // CHECK9: cond.true:
// CHECK9-NEXT: br label [[COND_END:%.*]] // CHECK9-NEXT: br label [[COND_END:%.*]]
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// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !42 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42 // CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42 // CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
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// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !9 // CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !9
// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !9 // CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !9
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !9 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !9
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
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// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !18 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !18
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !18 // CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !18
// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !18 // CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !18
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !18 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !18
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18 // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18
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// CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK10: omp.precond.then: // CHECK10: omp.precond.then:
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
// CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK10: cond.true: // CHECK10: cond.true:
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// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK10-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK10-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]
// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !24 // CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !24 // CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !24
// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !24 // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !24 // CHECK10-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24 // CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]), !llvm.access.group !24 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]), !llvm.access.group !24
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 // CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 // CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
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// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15
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// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK10: cond.true: // CHECK10: cond.true:
// CHECK10-NEXT: br label [[COND_END:%.*]] // CHECK10-NEXT: br label [[COND_END:%.*]]
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// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !42 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42 // CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42 // CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp

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// CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
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// CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
// CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
// CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !9 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
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// CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !14 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !14
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14 // CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14
// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14
// CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14 // CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
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// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17 // CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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// CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5 // CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
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// CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 // CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
// CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
// CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* // CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !9 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
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// CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
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// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
// CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
// CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !14 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !14
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14 // CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14
// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14
// CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14 // CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
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// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17 // CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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// CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 // CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK5-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !4 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4 // CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4
// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 // CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK5-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !4 // CHECK5-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4 // CHECK5-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4
// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !4 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4 // CHECK5-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc: // CHECK5: omp.inner.for.inc:
// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
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// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
// CHECK5-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8 // CHECK5-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !8
// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 // CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8
// CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8 // CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8
// CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8 // CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !8
// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8 // CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8
// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 // CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8
// CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8 // CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8
// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8 // CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8
// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8 // CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8
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// CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 // CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK6-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !4 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4 // CHECK6-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4 // CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4
// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 // CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK6-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !4 // CHECK6-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4 // CHECK6-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4 // CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4
// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !4 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4 // CHECK6-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4 // CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK6: omp.inner.for.inc: // CHECK6: omp.inner.for.inc:
// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
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// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
// CHECK6-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8 // CHECK6-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !8
// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 // CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8
// CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8 // CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8
// CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8 // CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !8
// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8 // CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8
// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 // CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8
// CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8 // CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8
// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8 // CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8
// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8 // CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8
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// CHECK13-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK13-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK13-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK13-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK13-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK13-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK13-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK13: omp.inner.for.cond.cleanup: // CHECK13: omp.inner.for.cond.cleanup:
// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
// CHECK13-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK13-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !6 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !6
// CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !6 // CHECK13-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !6
// CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !6 // CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !6
// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !6 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !6
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !6 // CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !6
// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !6 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !6
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !6 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !6
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
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// CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK13: omp.inner.for.cond.cleanup: // CHECK13: omp.inner.for.cond.cleanup:
// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !10 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !10
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK13-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 // CHECK13-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
// CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
// CHECK13-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK13-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
// CHECK13-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* // CHECK13-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !10 // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !10
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !10 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !10
// CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] // CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
// CHECK13-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !10 // CHECK13-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !10
// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK13: omp.body.continue: // CHECK13: omp.body.continue:
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
// CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
// CHECK13-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 // CHECK13-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
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// CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK13-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK13-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK13-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
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// CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK13: omp.inner.for.cond.cleanup: // CHECK13: omp.inner.for.cond.cleanup:
// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !15 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !15
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !15 // CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !15
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !15 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !15
// CHECK13-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !15 // CHECK13-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !15
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !15 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !15
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
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// CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK13: omp.inner.for.cond.cleanup: // CHECK13: omp.inner.for.cond.cleanup:
// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !18 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !18
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK13-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 // CHECK13-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
// CHECK13-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !18 // CHECK13-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !18
// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
// CHECK13-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK13-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
// CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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// CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK14-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK14: omp.inner.for.cond.cleanup: // CHECK14: omp.inner.for.cond.cleanup:
// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6
// CHECK14-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK14-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !6 // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !6
// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !6 // CHECK14-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !6
// CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !6 // CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !6
// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !6 // CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !6
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !6 // CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !6
// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !6 // CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !6
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !6 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !6
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 // CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6
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// CHECK14-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK14: omp.inner.for.cond.cleanup: // CHECK14: omp.inner.for.cond.cleanup:
// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !10 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !10
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK14-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 // CHECK14-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
// CHECK14-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK14-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
// CHECK14-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK14-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
// CHECK14-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK14-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
// CHECK14-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* // CHECK14-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !10 // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !10
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !10 // CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !10
// CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] // CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
// CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !10 // CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !10
// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK14: omp.body.continue: // CHECK14: omp.body.continue:
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 // CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
// CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
// CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 // CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
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// CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK14-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK14-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
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// CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK14: omp.inner.for.cond.cleanup: // CHECK14: omp.inner.for.cond.cleanup:
// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !15 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !15
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !15 // CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !15
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !15 // CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !15
// CHECK14-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !15 // CHECK14-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !15
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !15 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !15
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
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// CHECK14-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK14: omp.inner.for.cond.cleanup: // CHECK14: omp.inner.for.cond.cleanup:
// CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !18 // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !18
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK14-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 // CHECK14-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
// CHECK14-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !18 // CHECK14-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !18
// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
// CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
// CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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// CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK17-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK17-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK17-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK17-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK17-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK17-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 // CHECK17-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !5 // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !5 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !5
// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !5 // CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !5
// CHECK17-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !5 // CHECK17-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !5 // CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !5 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !5
// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !5 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !5 // CHECK17-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !5 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !5
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
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// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
// CHECK17-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !9 // CHECK17-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK17-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !9 // CHECK17-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !9
// CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !9 // CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !9
// CHECK17-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !9 // CHECK17-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !9
// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
// CHECK17-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !9 // CHECK17-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !9
// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1
// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !9 // CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !9
// CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !9 // CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !9
// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2
// CHECK17-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !9 // CHECK17-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !9
// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]], !llvm.access.group !9 // CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]], !llvm.access.group !9
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp

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// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47
// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !9 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !9
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
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// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
// CHECK1-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK1-NEXT: store i32 0, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
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// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !36 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !36
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.else: // CHECK1: omp_if.else:
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36
// CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !36 // CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !36
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// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !54 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !54
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.else: // CHECK1: omp_if.else:
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
// CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54 // CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54
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// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47
// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !9 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !9
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
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// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
// CHECK2-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK2-NEXT: store i32 0, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
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// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
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// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !36 // CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !36
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.else: // CHECK2: omp_if.else:
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36 // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36
// CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !36 // CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !36
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// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
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// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !54 // CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !54
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.else: // CHECK2: omp_if.else:
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54 // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
// CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54 // CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54
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// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45
// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK3-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !nontemporal !10, !llvm.access.group !9 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !nontemporal !10, !llvm.access.group !9
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK3-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
// CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !9 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !9
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
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// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14
// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
// CHECK3-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !10, !llvm.access.group !14 // CHECK3-NEXT: store i32 0, i32* [[CONV]], align 4, !nontemporal !10, !llvm.access.group !14
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
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// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK3-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
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// CHECK3: cond.false: // CHECK3: cond.false:
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: br label [[COND_END]] // CHECK3-NEXT: br label [[COND_END]]
// CHECK3: cond.end: // CHECK3: cond.end:
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond: // CHECK3: omp.inner.for.cond:
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
// CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !34 // CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !34
// CHECK3-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1 // CHECK3-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8 // CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !34 // CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !34
// CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !34 // CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !34
// CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !34 // CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !34
// CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then5: // CHECK3: omp_if.then5:
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !34 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !34
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK3: omp_if.else: // CHECK3: omp_if.else:
// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34 // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34
// CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !34 // CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !34
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// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]] // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]]
// CHECK3: omp.inner.for.body9: // CHECK3: omp.inner.for.body9:
// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK3-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64 // CHECK3-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 // CHECK3-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
// CHECK3-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1 // CHECK3-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK3-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8* // CHECK3-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK3-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8 // CHECK3-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1 // CHECK3-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8 // CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
// CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1 // CHECK3-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK3: omp_if.then15: // CHECK3: omp_if.then15:
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
// CHECK3-NEXT: br label [[OMP_IF_END18:%.*]] // CHECK3-NEXT: br label [[OMP_IF_END18:%.*]]
// CHECK3: omp_if.else16: // CHECK3: omp_if.else16:
// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK3-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
// CHECK3-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
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// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54
// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !54 // CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !54
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK3: omp_if.else: // CHECK3: omp_if.else:
// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54 // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
// CHECK3-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54 // CHECK3-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54
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// //
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45
// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK4-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !nontemporal !10, !llvm.access.group !9 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !nontemporal !10, !llvm.access.group !9
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK4-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
// CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !9 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !9
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
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// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14
// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
// CHECK4-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !10, !llvm.access.group !14 // CHECK4-NEXT: store i32 0, i32* [[CONV]], align 4, !nontemporal !10, !llvm.access.group !14
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
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// //
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK4-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK4-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
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// CHECK4: cond.false: // CHECK4: cond.false:
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK4-NEXT: br label [[COND_END]] // CHECK4-NEXT: br label [[COND_END]]
// CHECK4: cond.end: // CHECK4: cond.end:
// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK4: omp.inner.for.cond: // CHECK4: omp.inner.for.cond:
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
// CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !34 // CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !34
// CHECK4-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1 // CHECK4-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8 // CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !34 // CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !34
// CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !34 // CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !34
// CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !34 // CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !34
// CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then5: // CHECK4: omp_if.then5:
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !34 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !34
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.else: // CHECK4: omp_if.else:
// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34 // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34
// CHECK4-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !34 // CHECK4-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !34
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// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]] // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]]
// CHECK4: omp.inner.for.body9: // CHECK4: omp.inner.for.body9:
// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK4-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64 // CHECK4-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK4-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 // CHECK4-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
// CHECK4-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1 // CHECK4-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK4-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8* // CHECK4-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK4-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8 // CHECK4-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1 // CHECK4-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK4-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8 // CHECK4-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
// CHECK4-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1 // CHECK4-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK4: omp_if.then15: // CHECK4: omp_if.then15:
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
// CHECK4-NEXT: br label [[OMP_IF_END18:%.*]] // CHECK4-NEXT: br label [[OMP_IF_END18:%.*]]
// CHECK4: omp_if.else16: // CHECK4: omp_if.else16:
// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK4-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// //
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
// CHECK4-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK4-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
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// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54
// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !54 // CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !54
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.else: // CHECK4: omp_if.else:
// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54 // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
// CHECK4-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54 // CHECK4-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54
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// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47
// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13 // CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !13 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !13
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
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// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17
// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
// CHECK9-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !17 // CHECK9-NEXT: store i32 0, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK9: omp.body.continue: // CHECK9: omp.body.continue:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
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// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
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// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !40 // CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !40
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then: // CHECK9: omp_if.then:
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK9: omp_if.else: // CHECK9: omp_if.else:
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !40 // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !40
// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !40 // CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !40
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// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
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// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !58 // CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !58
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then: // CHECK9: omp_if.then:
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK9: omp_if.else: // CHECK9: omp_if.else:
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58 // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58 // CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58
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// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47
// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13 // CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !13 // CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !13
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
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// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17
// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
// CHECK10-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !17 // CHECK10-NEXT: store i32 0, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK10: omp.body.continue: // CHECK10: omp.body.continue:
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 // CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
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// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !40 // CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !40
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then: // CHECK10: omp_if.then:
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40
// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK10: omp_if.else: // CHECK10: omp_if.else:
// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !40 // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !40
// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !40 // CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !40
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// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !58 // CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !58
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then: // CHECK10: omp_if.then:
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58
// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK10: omp_if.else: // CHECK10: omp_if.else:
// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58 // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58 // CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58
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// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45
// CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK11-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK11: omp.inner.for.body: // CHECK11: omp.inner.for.body:
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !nontemporal !14, !llvm.access.group !13 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !nontemporal !14, !llvm.access.group !13
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK11-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13 // CHECK11-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
// CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !13 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !13
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK11: omp.inner.for.inc: // CHECK11: omp.inner.for.inc:
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
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// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK11: omp.inner.for.body: // CHECK11: omp.inner.for.body:
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
// CHECK11-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !14, !llvm.access.group !18 // CHECK11-NEXT: store i32 0, i32* [[CONV]], align 4, !nontemporal !14, !llvm.access.group !18
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue: // CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK11: omp.inner.for.inc: // CHECK11: omp.inner.for.inc:
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
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// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK11-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
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// CHECK11: cond.false: // CHECK11: cond.false:
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: br label [[COND_END]] // CHECK11-NEXT: br label [[COND_END]]
// CHECK11: cond.end: // CHECK11: cond.end:
// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK11: omp_if.then: // CHECK11: omp_if.then:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK11: omp.inner.for.cond: // CHECK11: omp.inner.for.cond:
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK11: omp.inner.for.body: // CHECK11: omp.inner.for.body:
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38
// CHECK11-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK11-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
// CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK11-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !38 // CHECK11-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !38
// CHECK11-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1 // CHECK11-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8 // CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !38 // CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !38
// CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !38 // CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !38
// CHECK11-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !38 // CHECK11-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !38
// CHECK11-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK11-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then5: // CHECK11: omp_if.then5:
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !38 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !38
// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK11: omp_if.else: // CHECK11: omp_if.else:
// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38 // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38
// CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38 // CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38
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// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] // CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]] // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]]
// CHECK11: omp.inner.for.body9: // CHECK11: omp.inner.for.body9:
// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK11-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64 // CHECK11-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 // CHECK11-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
// CHECK11-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1 // CHECK11-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK11-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8* // CHECK11-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK11-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8 // CHECK11-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1 // CHECK11-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
// CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1 // CHECK11-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK11: omp_if.then15: // CHECK11: omp_if.then15:
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
// CHECK11-NEXT: br label [[OMP_IF_END18:%.*]] // CHECK11-NEXT: br label [[OMP_IF_END18:%.*]]
// CHECK11: omp_if.else16: // CHECK11: omp_if.else16:
// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK11-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then: // CHECK11: omp_if.then:
// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then: // CHECK11: omp_if.then:
// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
// CHECK11-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
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// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK11: omp.inner.for.body: // CHECK11: omp.inner.for.body:
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK11-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !58 // CHECK11-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !58
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then: // CHECK11: omp_if.then:
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58
// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK11: omp_if.else: // CHECK11: omp_if.else:
// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58 // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58 // CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58
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// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45
// CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK12-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8 // CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK12: omp.inner.for.body: // CHECK12: omp.inner.for.body:
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !nontemporal !14, !llvm.access.group !13 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !nontemporal !14, !llvm.access.group !13
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32* // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK12-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13 // CHECK12-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
// CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !13 // CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !13
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK12: omp.inner.for.inc: // CHECK12: omp.inner.for.inc:
// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
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// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK12: omp.inner.for.body: // CHECK12: omp.inner.for.body:
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
// CHECK12-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !14, !llvm.access.group !18 // CHECK12-NEXT: store i32 0, i32* [[CONV]], align 4, !nontemporal !14, !llvm.access.group !18
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK12: omp.body.continue: // CHECK12: omp.body.continue:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK12: omp.inner.for.inc: // CHECK12: omp.inner.for.inc:
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
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// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK12-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK12-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK12-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
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// CHECK12: cond.false: // CHECK12: cond.false:
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK12-NEXT: br label [[COND_END]] // CHECK12-NEXT: br label [[COND_END]]
// CHECK12: cond.end: // CHECK12: cond.end:
// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK12: omp_if.then: // CHECK12: omp_if.then:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK12: omp.inner.for.cond: // CHECK12: omp.inner.for.cond:
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK12: omp.inner.for.body: // CHECK12: omp.inner.for.body:
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38
// CHECK12-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK12-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
// CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK12-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !38 // CHECK12-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !38
// CHECK12-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1 // CHECK12-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8 // CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !38 // CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !38
// CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !38 // CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !38
// CHECK12-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !38 // CHECK12-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !38
// CHECK12-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK12-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then5: // CHECK12: omp_if.then5:
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !38 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !38
// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] // CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK12: omp_if.else: // CHECK12: omp_if.else:
// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38 // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38
// CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38 // CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38
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// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] // CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]] // CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]]
// CHECK12: omp.inner.for.body9: // CHECK12: omp.inner.for.body9:
// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK12-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64 // CHECK12-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK12-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 // CHECK12-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
// CHECK12-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1 // CHECK12-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK12-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8* // CHECK12-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK12-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8 // CHECK12-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1 // CHECK12-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8 // CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
// CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1 // CHECK12-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK12: omp_if.then15: // CHECK12: omp_if.then15:
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
// CHECK12-NEXT: br label [[OMP_IF_END18:%.*]] // CHECK12-NEXT: br label [[OMP_IF_END18:%.*]]
// CHECK12: omp_if.else16: // CHECK12: omp_if.else16:
// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK12-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK12-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then: // CHECK12: omp_if.then:
// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then: // CHECK12: omp_if.then:
// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70
// CHECK12-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK12-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK12-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1 // CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV1]], align 1
// CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
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// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK12: omp.inner.for.body: // CHECK12: omp.inner.for.body:
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK12-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !58 // CHECK12-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !58
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then: // CHECK12: omp_if.then:
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58
// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] // CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK12: omp_if.else: // CHECK12: omp_if.else:
// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58 // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
// CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58 // CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp

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// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double*
// CHECK1-NEXT: store double* [[CONV]], double** [[TMP]], align 8 // CHECK1-NEXT: store double* [[CONV]], double** [[TMP]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile double, double* [[TMP0]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile double, double* [[TMP0]], align 8
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK1-NEXT: store double [[TMP1]], double* [[CONV4]], align 8 // CHECK1-NEXT: store double [[TMP1]], double* [[CONV4]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK1-NEXT: store float [[TMP5]], float* [[CONV6]], align 4 // CHECK1-NEXT: store float [[TMP5]], float* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load double, double* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load double, double* [[CONV3]], align 8
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[G_CASTED]] to double* // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[G_CASTED]] to double*
// CHECK1-NEXT: store double [[TMP7]], double* [[CONV7]], align 8 // CHECK1-NEXT: store double [[TMP7]], double* [[CONV7]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]])
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// CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK1: .omp.lastprivate.then: // CHECK1: .omp.lastprivate.then:
// CHECK1-NEXT: [[TMP27:%.*]] = load double, double* [[G5]], align 8 // CHECK1-NEXT: [[TMP27:%.*]] = load double, double* [[G5]], align 8
// CHECK1-NEXT: store volatile double [[TMP27]], double* [[CONV3]], align 8 // CHECK1-NEXT: store volatile double [[TMP27]], double* [[CONV3]], align 8
// CHECK1-NEXT: [[TMP28:%.*]] = load double*, double** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP28:%.*]] = load double*, double** [[_TMP7]], align 8
// CHECK1-NEXT: [[TMP29:%.*]] = load double, double* [[TMP28]], align 8 // CHECK1-NEXT: [[TMP29:%.*]] = load double, double* [[TMP28]], align 8
// CHECK1-NEXT: store volatile double [[TMP29]], double* [[TMP0]], align 8 // CHECK1-NEXT: store volatile double [[TMP29]], double* [[TMP0]], align 8
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK1-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP31:%.*]] = load float, float* [[SFVAR9]], align 4 // CHECK1-NEXT: [[TMP31:%.*]] = load float, float* [[SFVAR9]], align 4
// CHECK1-NEXT: store float [[TMP31]], float* [[CONV2]], align 8 // CHECK1-NEXT: store float [[TMP31]], float* [[CONV2]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done: // CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK1: .omp.lastprivate.then: // CHECK1: .omp.lastprivate.then:
// CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[G7]], align 8 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[G7]], align 8
// CHECK1-NEXT: store volatile double [[TMP22]], double* [[CONV3]], align 8 // CHECK1-NEXT: store volatile double [[TMP22]], double* [[CONV3]], align 8
// CHECK1-NEXT: [[TMP23:%.*]] = load double*, double** [[_TMP9]], align 8 // CHECK1-NEXT: [[TMP23:%.*]] = load double*, double** [[_TMP9]], align 8
// CHECK1-NEXT: [[TMP24:%.*]] = load double, double* [[TMP23]], align 8 // CHECK1-NEXT: [[TMP24:%.*]] = load double, double* [[TMP23]], align 8
// CHECK1-NEXT: store volatile double [[TMP24]], double* [[TMP2]], align 8 // CHECK1-NEXT: store volatile double [[TMP24]], double* [[TMP2]], align 8
// CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[SVAR10]], align 4 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[SVAR10]], align 4
// CHECK1-NEXT: store i32 [[TMP25]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[TMP25]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP26:%.*]] = load float, float* [[SFVAR11]], align 4 // CHECK1-NEXT: [[TMP26:%.*]] = load float, float* [[SFVAR11]], align 4
// CHECK1-NEXT: store float [[TMP26]], float* [[CONV2]], align 8 // CHECK1-NEXT: store float [[TMP26]], float* [[CONV2]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done: // CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK1-SAME: () #[[ATTR4:[0-9]+]] { // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double*
// CHECK2-NEXT: store double* [[CONV]], double** [[TMP]], align 8 // CHECK2-NEXT: store double* [[CONV]], double** [[TMP]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load volatile double, double* [[TMP0]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile double, double* [[TMP0]], align 8
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK2-NEXT: store double [[TMP1]], double* [[CONV4]], align 8 // CHECK2-NEXT: store double [[TMP1]], double* [[CONV4]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK2-NEXT: store float [[TMP5]], float* [[CONV6]], align 4 // CHECK2-NEXT: store float [[TMP5]], float* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load double, double* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load double, double* [[CONV3]], align 8
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[G_CASTED]] to double* // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[G_CASTED]] to double*
// CHECK2-NEXT: store double [[TMP7]], double* [[CONV7]], align 8 // CHECK2-NEXT: store double [[TMP7]], double* [[CONV7]], align 8
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]])
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// CHECK2-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK2: .omp.lastprivate.then: // CHECK2: .omp.lastprivate.then:
// CHECK2-NEXT: [[TMP27:%.*]] = load double, double* [[G5]], align 8 // CHECK2-NEXT: [[TMP27:%.*]] = load double, double* [[G5]], align 8
// CHECK2-NEXT: store volatile double [[TMP27]], double* [[CONV3]], align 8 // CHECK2-NEXT: store volatile double [[TMP27]], double* [[CONV3]], align 8
// CHECK2-NEXT: [[TMP28:%.*]] = load double*, double** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP28:%.*]] = load double*, double** [[_TMP7]], align 8
// CHECK2-NEXT: [[TMP29:%.*]] = load double, double* [[TMP28]], align 8 // CHECK2-NEXT: [[TMP29:%.*]] = load double, double* [[TMP28]], align 8
// CHECK2-NEXT: store volatile double [[TMP29]], double* [[TMP0]], align 8 // CHECK2-NEXT: store volatile double [[TMP29]], double* [[TMP0]], align 8
// CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK2-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP31:%.*]] = load float, float* [[SFVAR9]], align 4 // CHECK2-NEXT: [[TMP31:%.*]] = load float, float* [[SFVAR9]], align 4
// CHECK2-NEXT: store float [[TMP31]], float* [[CONV2]], align 8 // CHECK2-NEXT: store float [[TMP31]], float* [[CONV2]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done: // CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK2-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK2: .omp.lastprivate.then: // CHECK2: .omp.lastprivate.then:
// CHECK2-NEXT: [[TMP22:%.*]] = load double, double* [[G7]], align 8 // CHECK2-NEXT: [[TMP22:%.*]] = load double, double* [[G7]], align 8
// CHECK2-NEXT: store volatile double [[TMP22]], double* [[CONV3]], align 8 // CHECK2-NEXT: store volatile double [[TMP22]], double* [[CONV3]], align 8
// CHECK2-NEXT: [[TMP23:%.*]] = load double*, double** [[_TMP9]], align 8 // CHECK2-NEXT: [[TMP23:%.*]] = load double*, double** [[_TMP9]], align 8
// CHECK2-NEXT: [[TMP24:%.*]] = load double, double* [[TMP23]], align 8 // CHECK2-NEXT: [[TMP24:%.*]] = load double, double* [[TMP23]], align 8
// CHECK2-NEXT: store volatile double [[TMP24]], double* [[TMP2]], align 8 // CHECK2-NEXT: store volatile double [[TMP24]], double* [[TMP2]], align 8
// CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[SVAR10]], align 4 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[SVAR10]], align 4
// CHECK2-NEXT: store i32 [[TMP25]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[TMP25]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP26:%.*]] = load float, float* [[SFVAR11]], align 4 // CHECK2-NEXT: [[TMP26:%.*]] = load float, float* [[SFVAR11]], align 4
// CHECK2-NEXT: store float [[TMP26]], float* [[CONV2]], align 8 // CHECK2-NEXT: store float [[TMP26]], float* [[CONV2]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done: // CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK2-SAME: () #[[ATTR4:[0-9]+]] { // CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 // CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 // CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK5-NEXT: store i32 2, i32* [[I]], align 4 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK5: .omp.final.done: // CHECK5: .omp.final.done:
// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK5-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 // CHECK5-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
// CHECK5-NEXT: br i1 [[TMP27]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK5-NEXT: br i1 [[TMP27]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then: // CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[T_VAR3]], align 4
// CHECK5-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 8 // CHECK5-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP30:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* // CHECK5-NEXT: [[TMP30:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 8, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 8, i1 false)
// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP31:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* // CHECK5-NEXT: [[TMP31:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S*
// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2
// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP32]] // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP32]]
// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK5: omp.arraycpy.body: // CHECK5: omp.arraycpy.body:
// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
// CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP32]] // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP32]]
// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]]
// CHECK5: omp.arraycpy.done13: // CHECK5: omp.arraycpy.done13:
// CHECK5-NEXT: [[TMP35:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 // CHECK5-NEXT: [[TMP35:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8
// CHECK5-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP3]] to i8* // CHECK5-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP3]] to i8*
// CHECK5-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[TMP35]] to i8* // CHECK5-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[TMP35]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP36]], i8* align 4 [[TMP37]], i64 4, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP36]], i8* align 4 [[TMP37]], i64 4, i1 false)
// CHECK5-NEXT: [[TMP38:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK5-NEXT: [[TMP38:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK5-NEXT: store i32 [[TMP38]], i32* [[CONV1]], align 8 // CHECK5-NEXT: store i32 [[TMP38]], i32* [[CONV1]], align 4
// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK5: .omp.lastprivate.done: // CHECK5: .omp.lastprivate.done:
// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
// CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
// CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK5: arraydestroy.body: // CHECK5: arraydestroy.body:
// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
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// CHECK5-NEXT: store i32 2, i32* [[I]], align 4 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK5: .omp.final.done: // CHECK5: .omp.final.done:
// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 // CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
// CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then: // CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR5]], align 4 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR5]], align 4
// CHECK5-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 8 // CHECK5-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8* // CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false)
// CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR7]] to %struct.S* // CHECK5-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR7]] to %struct.S*
// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2
// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN15]], [[TMP31]] // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN15]], [[TMP31]]
// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE16:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE16:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK5: omp.arraycpy.body: // CHECK5: omp.arraycpy.body:
// CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN15]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN15]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
// CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false)
// CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]]
// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE16]], label [[OMP_ARRAYCPY_BODY]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE16]], label [[OMP_ARRAYCPY_BODY]]
// CHECK5: omp.arraycpy.done16: // CHECK5: omp.arraycpy.done16:
// CHECK5-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8 // CHECK5-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8
// CHECK5-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP5]] to i8* // CHECK5-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP5]] to i8*
// CHECK5-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* // CHECK5-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false)
// CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR10]], align 4 // CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR10]], align 4
// CHECK5-NEXT: store i32 [[TMP37]], i32* [[CONV1]], align 8 // CHECK5-NEXT: store i32 [[TMP37]], i32* [[CONV1]], align 4
// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK5: .omp.lastprivate.done: // CHECK5: .omp.lastprivate.done:
// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]] // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]]
// CHECK5-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0
// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2
// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK5: arraydestroy.body: // CHECK5: arraydestroy.body:
// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
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// CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
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// CHECK5-NEXT: store i32 2, i32* [[I]], align 4 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK5: .omp.final.done: // CHECK5: .omp.final.done:
// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 // CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
// CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then: // CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR2]], align 4
// CHECK5-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 8 // CHECK5-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* // CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false)
// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* // CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2
// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP30]] // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP30]]
// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
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// CHECK5-NEXT: store i32 2, i32* [[I]], align 4 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK5: .omp.final.done: // CHECK5: .omp.final.done:
// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 // CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
// CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then: // CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR4]], align 4 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR4]], align 4
// CHECK5-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 8 // CHECK5-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8* // CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false) // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false)
// CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
// CHECK5-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR6]] to %struct.S.0* // CHECK5-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR6]] to %struct.S.0*
// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2
// CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN13]], [[TMP31]] // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN13]], [[TMP31]]
// CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
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// CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 // CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 // CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4 // CHECK6-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK6-NEXT: store i32 2, i32* [[I]], align 4 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4
// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK6: .omp.final.done: // CHECK6: .omp.final.done:
// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 // CHECK6-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
// CHECK6-NEXT: br i1 [[TMP27]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK6-NEXT: br i1 [[TMP27]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then: // CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[T_VAR3]], align 4
// CHECK6-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 8 // CHECK6-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP30:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* // CHECK6-NEXT: [[TMP30:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 8, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 8, i1 false)
// CHECK6-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 // CHECK6-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
// CHECK6-NEXT: [[TMP31:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* // CHECK6-NEXT: [[TMP31:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S*
// CHECK6-NEXT: [[TMP32:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK6-NEXT: [[TMP32:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2
// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP32]] // CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP32]]
// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK6: omp.arraycpy.body: // CHECK6: omp.arraycpy.body:
// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
// CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP32]] // CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP32]]
// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]]
// CHECK6: omp.arraycpy.done13: // CHECK6: omp.arraycpy.done13:
// CHECK6-NEXT: [[TMP35:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 // CHECK6-NEXT: [[TMP35:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8
// CHECK6-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP3]] to i8* // CHECK6-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP3]] to i8*
// CHECK6-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[TMP35]] to i8* // CHECK6-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[TMP35]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP36]], i8* align 4 [[TMP37]], i64 4, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP36]], i8* align 4 [[TMP37]], i64 4, i1 false)
// CHECK6-NEXT: [[TMP38:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK6-NEXT: [[TMP38:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK6-NEXT: store i32 [[TMP38]], i32* [[CONV1]], align 8 // CHECK6-NEXT: store i32 [[TMP38]], i32* [[CONV1]], align 4
// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK6: .omp.lastprivate.done: // CHECK6: .omp.lastprivate.done:
// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
// CHECK6-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK6-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
// CHECK6-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK6-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK6: arraydestroy.body: // CHECK6: arraydestroy.body:
// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
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// CHECK6-NEXT: store i32 2, i32* [[I]], align 4 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4
// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK6: .omp.final.done: // CHECK6: .omp.final.done:
// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 // CHECK6-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
// CHECK6-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK6-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then: // CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR5]], align 4 // CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR5]], align 4
// CHECK6-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 8 // CHECK6-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8* // CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false)
// CHECK6-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 // CHECK6-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
// CHECK6-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR7]] to %struct.S* // CHECK6-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S]* [[S_ARR7]] to %struct.S*
// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK6-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2
// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN15]], [[TMP31]] // CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN15]], [[TMP31]]
// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE16:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE16:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK6: omp.arraycpy.body: // CHECK6: omp.arraycpy.body:
// CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP30]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN15]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN15]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
// CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false)
// CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]] // CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP31]]
// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE16]], label [[OMP_ARRAYCPY_BODY]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE16]], label [[OMP_ARRAYCPY_BODY]]
// CHECK6: omp.arraycpy.done16: // CHECK6: omp.arraycpy.done16:
// CHECK6-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8 // CHECK6-NEXT: [[TMP34:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8
// CHECK6-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP5]] to i8* // CHECK6-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP5]] to i8*
// CHECK6-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8* // CHECK6-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false)
// CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR10]], align 4 // CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR10]], align 4
// CHECK6-NEXT: store i32 [[TMP37]], i32* [[CONV1]], align 8 // CHECK6-NEXT: store i32 [[TMP37]], i32* [[CONV1]], align 4
// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK6: .omp.lastprivate.done: // CHECK6: .omp.lastprivate.done:
// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]] // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]]
// CHECK6-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0 // CHECK6-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0
// CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 // CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2
// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK6: arraydestroy.body: // CHECK6: arraydestroy.body:
// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
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// CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
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// CHECK6-NEXT: store i32 2, i32* [[I]], align 4 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4
// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK6: .omp.final.done: // CHECK6: .omp.final.done:
// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 // CHECK6-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
// CHECK6-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK6-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then: // CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR2]], align 4
// CHECK6-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 8 // CHECK6-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* // CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false)
// CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 // CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* // CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 // CHECK6-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2
// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP30]] // CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP30]]
// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
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// CHECK6-NEXT: store i32 2, i32* [[I]], align 4 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4
// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK6: .omp.final.done: // CHECK6: .omp.final.done:
// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 // CHECK6-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
// CHECK6-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK6-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then: // CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR4]], align 4 // CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR4]], align 4
// CHECK6-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 8 // CHECK6-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8* // CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false) // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false)
// CHECK6-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 // CHECK6-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
// CHECK6-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR6]] to %struct.S.0* // CHECK6-NEXT: [[TMP30:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR6]] to %struct.S.0*
// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK6-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2
// CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN13]], [[TMP31]] // CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN13]], [[TMP31]]
// CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp

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// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !13 // CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !13
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !13 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !13
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !13 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !13
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
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// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !22 // CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !22
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !22 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !22
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !22 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !22
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22
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// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK13: omp.precond.then: // CHECK13: omp.precond.then:
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK13-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK13-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
// CHECK13-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK13-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK13: cond.true: // CHECK13: cond.true:
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// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK13-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK13-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]
// CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK13-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !28 // CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !28 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !28
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !28 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !28 // CHECK13-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28 // CHECK13-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]), !llvm.access.group !28 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]), !llvm.access.group !28
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28 // CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28
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// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8
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// CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !34 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !34
// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !34 // CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !34
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !34 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !34
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !34 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !34
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34
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// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK13-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4, !llvm.access.group !40 // CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !40 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !40
// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !40 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4, !llvm.access.group !40 // CHECK13-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40 // CHECK13-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]), !llvm.access.group !40 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]), !llvm.access.group !40
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40
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// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK13: omp.precond.then: // CHECK13: omp.precond.then:
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 // CHECK13-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32
// CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK13-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK13-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) // CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]])
// CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK13: omp.dispatch.cond: // CHECK13: omp.dispatch.cond:
// CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..21 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..21
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// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58 // CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58
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// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK13: omp.dispatch.cond: // CHECK13: omp.dispatch.cond:
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK13-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..29 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..29
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// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70 // CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70
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// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK13: omp.dispatch.cond: // CHECK13: omp.dispatch.cond:
// CHECK13-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK13-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !13 // CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !13
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !13 // CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !13
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !13 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !13
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
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// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
// CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !22 // CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !22
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !22 // CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !22
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !22 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !22
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22
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// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK14: omp.precond.then: // CHECK14: omp.precond.then:
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK14-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK14-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
// CHECK14-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK14-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK14: cond.true: // CHECK14: cond.true:
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// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK14-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK14-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]
// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK14-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28 // CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !28 // CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !28 // CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !28
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !28 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !28 // CHECK14-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28 // CHECK14-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]), !llvm.access.group !28 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]), !llvm.access.group !28
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 // CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28 // CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28
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// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8
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// CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !34 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !34
// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !34 // CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !34
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !34 // CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !34
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !34 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !34
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34
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// CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK14-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK14-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4, !llvm.access.group !40 // CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !40 // CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !40
// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !40 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4, !llvm.access.group !40 // CHECK14-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40 // CHECK14-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]), !llvm.access.group !40 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]), !llvm.access.group !40
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 // CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40 // CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40
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// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK14-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK14: omp.precond.then: // CHECK14: omp.precond.then:
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 // CHECK14-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32
// CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK14-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK14-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) // CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 35, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]])
// CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK14: omp.dispatch.cond: // CHECK14: omp.dispatch.cond:
// CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK14-NEXT: entry: // CHECK14-NEXT: entry:
// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..21 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..21
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// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58 // CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58 // CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58
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// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK14: omp.dispatch.cond: // CHECK14: omp.dispatch.cond:
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK14-NEXT: entry: // CHECK14-NEXT: entry:
// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..29 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..29
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// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70 // CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70 // CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70
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// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK14: omp.dispatch.cond: // CHECK14: omp.dispatch.cond:
// CHECK14-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK14-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !13 // CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !13
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !13 // CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !13
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !13 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !13
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
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// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !22 // CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !22 // CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !22
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !22 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !22
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22
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// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK17: omp.precond.then: // CHECK17: omp.precond.then:
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
// CHECK17-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK17-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK17: cond.true: // CHECK17: cond.true:
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// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK17-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK17-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]
// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28
// CHECK17-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK17-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK17-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK17-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !28 // CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !28
// CHECK17-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !28 // CHECK17-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !28
// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !28 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !28
// CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !28 // CHECK17-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !28
// CHECK17-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28 // CHECK17-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]), !llvm.access.group !28 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]), !llvm.access.group !28
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
// CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28
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// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8
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// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !34 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !34
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !34 // CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !34
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !34 // CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !34
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !34 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !34
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34
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// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK17-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4, !llvm.access.group !40 // CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4, !llvm.access.group !40
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !40 // CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !40
// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !40 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !40
// CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4, !llvm.access.group !40 // CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4, !llvm.access.group !40
// CHECK17-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40 // CHECK17-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]), !llvm.access.group !40 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]), !llvm.access.group !40
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40
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// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK17-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK17-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK17-NEXT: store i32 0, i32* [[I]], align 4 // CHECK17-NEXT: store i32 0, i32* [[I]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK17: omp.precond.then: // CHECK17: omp.precond.then:
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 // CHECK17-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32
// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) // CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]])
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK17: omp.dispatch.cond: // CHECK17: omp.dispatch.cond:
// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..21 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..21
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// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58 // CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58 // CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58
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// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK17: omp.dispatch.cond: // CHECK17: omp.dispatch.cond:
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK17-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..29 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..29
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// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70
// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70 // CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70 // CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70
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// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK17: omp.dispatch.cond: // CHECK17: omp.dispatch.cond:
// CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !13 // CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !13
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !13 // CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !13
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !13 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !13
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 // CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
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// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !22 // CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !22 // CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !22
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !22 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !22
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 // CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22
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// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK18: omp.precond.then: // CHECK18: omp.precond.then:
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK18-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK18-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
// CHECK18-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK18-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK18: cond.true: // CHECK18: cond.true:
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// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
// CHECK18-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK18-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]]
// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28 // CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28
// CHECK18-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK18-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK18-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK18-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28 // CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !28 // CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !28
// CHECK18-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !28 // CHECK18-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !28
// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !28 // CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !28
// CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !28 // CHECK18-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !28
// CHECK18-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28 // CHECK18-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]), !llvm.access.group !28 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]), !llvm.access.group !28
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
// CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28 // CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28
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// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8
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// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !34 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !34
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !34 // CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !34
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !34 // CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !34
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !34 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !34
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34 // CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34
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// CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK18-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
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// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4, !llvm.access.group !40 // CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4, !llvm.access.group !40
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !40 // CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !40
// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !40 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !40
// CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4, !llvm.access.group !40 // CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4, !llvm.access.group !40
// CHECK18-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40 // CHECK18-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]), !llvm.access.group !40 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP22]]), !llvm.access.group !40
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40
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// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK18-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK18-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK18-NEXT: store i32 0, i32* [[I]], align 4 // CHECK18-NEXT: store i32 0, i32* [[I]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK18: omp.precond.then: // CHECK18: omp.precond.then:
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32 // CHECK18-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP6]] to i32
// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK18-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK18-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]]) // CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP12]], i32 1073741859, i32 [[TMP9]], i32 [[TMP10]], i32 1, i32 [[TMP8]])
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK18: omp.dispatch.cond: // CHECK18: omp.dispatch.cond:
// CHECK18-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..21 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..21
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// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58 // CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58 // CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58
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// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK18: omp.dispatch.cond: // CHECK18: omp.dispatch.cond:
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK18-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP2]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..29 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..29
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// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70
// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70 // CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70 // CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70
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// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK18: omp.dispatch.cond: // CHECK18: omp.dispatch.cond:
// CHECK18-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK18-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp

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// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK1: omp.inner.for.end: // CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit: // CHECK1: omp.loop.exit:
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 // CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
// CHECK1-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK1: .omp.final.then: // CHECK1: .omp.final.then:
// CHECK1-NEXT: store i32 10, i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 10, i32* [[CONV]], align 4
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK1: .omp.final.done: // CHECK1: .omp.final.done:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29
// CHECK1-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29 // CHECK1-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !29 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
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// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !32 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !32
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
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// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK1-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double // CHECK1-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
// CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 // CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
// CHECK1-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float // CHECK1-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
// CHECK1-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK1-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK1-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !35 // CHECK1-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !35
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// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !38 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !38
// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !38 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !38
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
// CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK1-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK1-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !38 // CHECK1-NEXT: store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !38
// CHECK1-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !38 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !38
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK1-NEXT: store double [[INC]], double* [[A6]], align 8, !llvm.access.group !38 // CHECK1-NEXT: store double [[INC]], double* [[A6]], align 8, !llvm.access.group !38
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// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK1-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK1-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK1-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK1-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK1-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK1-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK1-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK1-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !41 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !41
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41
// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK1-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !41 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !41
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !41 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !41
// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK1-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !41 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !41
// CHECK1-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !41 // CHECK1-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !41
// CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !41 // CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !41
// CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !41 // CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !41
// CHECK1-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK1-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK1-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK1-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK1-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK1-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !41 // CHECK1-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !41
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK1-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41 // CHECK1-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
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// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !44 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !44
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !44 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !44
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !44 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !44 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !44 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
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// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK2: omp.inner.for.end: // CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit: // CHECK2: omp.loop.exit:
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 // CHECK2-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
// CHECK2-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK2: .omp.final.then: // CHECK2: .omp.final.then:
// CHECK2-NEXT: store i32 10, i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 10, i32* [[CONV]], align 4
// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK2: .omp.final.done: // CHECK2: .omp.final.done:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29
// CHECK2-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29 // CHECK2-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !29 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
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// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32
// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !32 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !32
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !32 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !32 // CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
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// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK2-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double // CHECK2-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
// CHECK2-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 // CHECK2-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
// CHECK2-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float // CHECK2-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
// CHECK2-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK2-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK2-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !35 // CHECK2-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !35
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// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
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// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !38 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !38
// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !38 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !38
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
// CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK2-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK2-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !38 // CHECK2-NEXT: store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !38
// CHECK2-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !38 // CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !38
// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK2-NEXT: store double [[INC]], double* [[A6]], align 8, !llvm.access.group !38 // CHECK2-NEXT: store double [[INC]], double* [[A6]], align 8, !llvm.access.group !38
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// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK2-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK2-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK2-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK2-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK2-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK2-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK2-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK2-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !41 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !41
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41
// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK2-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !41 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !41
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !41 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !41
// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK2-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !41 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !41
// CHECK2-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !41 // CHECK2-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !41
// CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !41 // CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !41
// CHECK2-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !41 // CHECK2-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !41
// CHECK2-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK2-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK2-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK2-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK2-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK2-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK2-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !41 // CHECK2-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !41
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
// CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK2-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41 // CHECK2-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
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// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !44 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !44
// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !44 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !44
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !44 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !44 // CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !44 // CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK2-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
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// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
// CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
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// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
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// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK3-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK3-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !42 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !42
// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK3-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !42 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !42
// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
// CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK3-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !42 // CHECK3-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
// CHECK3-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !42 // CHECK3-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !42
// CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !42 // CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !42
// CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !42 // CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !42
// CHECK3-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK3-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK3-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK3-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK3-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !42 // CHECK3-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !42
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
// CHECK3-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK3-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK3-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42 // CHECK3-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
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// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !45 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue: // CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc: // CHECK3: omp.inner.for.inc:
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// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
// CHECK4-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK4-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !30 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
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// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !33 // CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK4-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
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// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK4-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK4-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !42 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !42
// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
// CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK4-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK4-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK4-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !42 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !42
// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
// CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK4-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !42 // CHECK4-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
// CHECK4-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !42 // CHECK4-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !42
// CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !42 // CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !42
// CHECK4-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !42 // CHECK4-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !42
// CHECK4-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK4-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK4-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK4-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK4-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !42 // CHECK4-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !42
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
// CHECK4-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK4-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK4-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42 // CHECK4-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
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// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45 // CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !45 // CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK4-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue: // CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK4: omp.inner.for.inc: // CHECK4: omp.inner.for.inc:
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// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102
// CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK5: omp.inner.for.end: // CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK5: omp.loop.exit: // CHECK5: omp.loop.exit:
// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK5-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 // CHECK5-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
// CHECK5-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK5-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK5: .omp.final.then: // CHECK5: .omp.final.then:
// CHECK5-NEXT: store i32 10, i32* [[CONV]], align 8 // CHECK5-NEXT: store i32 10, i32* [[CONV]], align 4
// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK5: .omp.final.done: // CHECK5: .omp.final.done:
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK5-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK5-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
// CHECK5-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !30 // CHECK5-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK5-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK5-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK5-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !30 // CHECK5-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue: // CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc: // CHECK5: omp.inner.for.inc:
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
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// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !33 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !33 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33
// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !33 // CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !33 // CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue: // CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc: // CHECK5: omp.inner.for.inc:
// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
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// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !36 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !36
// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK5-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !36 // CHECK5-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !36
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK5-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36 // CHECK5-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
// CHECK5-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double // CHECK5-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
// CHECK5-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 // CHECK5-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
// CHECK5-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float // CHECK5-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
// CHECK5-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36 // CHECK5-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK5-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36 // CHECK5-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
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// CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK5-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 // CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
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// CHECK5: cond.false: // CHECK5: cond.false:
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK5-NEXT: br label [[COND_END]] // CHECK5-NEXT: br label [[COND_END]]
// CHECK5: cond.end: // CHECK5: cond.end:
// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
// CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK5: omp_if.then: // CHECK5: omp_if.then:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond: // CHECK5: omp.inner.for.cond:
// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39
// CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !39 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !39
// CHECK5-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double // CHECK5-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK5-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00 // CHECK5-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK5-NEXT: store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !39 // CHECK5-NEXT: store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !39
// CHECK5-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK5-NEXT: [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !39 // CHECK5-NEXT: [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !39
// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 // CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
// CHECK5-NEXT: store double [[INC]], double* [[A7]], align 8, !llvm.access.group !39 // CHECK5-NEXT: store double [[INC]], double* [[A7]], align 8, !llvm.access.group !39
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// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK5-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] // CHECK5-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
// CHECK5-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]] // CHECK5-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]]
// CHECK5: omp.inner.for.body13: // CHECK5: omp.inner.for.body13:
// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK5-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1 // CHECK5-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1
// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]] // CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
// CHECK5-NEXT: store i32 [[ADD15]], i32* [[I]], align 4 // CHECK5-NEXT: store i32 [[ADD15]], i32* [[I]], align 4
// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double // CHECK5-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double
// CHECK5-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00 // CHECK5-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00
// CHECK5-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK5-NEXT: store double [[ADD17]], double* [[A18]], align 8 // CHECK5-NEXT: store double [[ADD17]], double* [[A18]], align 8
// CHECK5-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK5-NEXT: [[TMP21:%.*]] = load double, double* [[A19]], align 8 // CHECK5-NEXT: [[TMP21:%.*]] = load double, double* [[A19]], align 8
// CHECK5-NEXT: [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00 // CHECK5-NEXT: [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00
// CHECK5-NEXT: store double [[INC20]], double* [[A19]], align 8 // CHECK5-NEXT: store double [[INC20]], double* [[A19]], align 8
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// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK5-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK5-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK5-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK5-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK5-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK5-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK5-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK5-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK5-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK5-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK5-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK5-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !44 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !44
// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK5-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !44 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !44
// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK5-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !44 // CHECK5-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK5-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !44 // CHECK5-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !44
// CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK5-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK5-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK5-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !44 // CHECK5-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !44
// CHECK5-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !44 // CHECK5-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !44
// CHECK5-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK5-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK5-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK5-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK5-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !44 // CHECK5-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !44
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK5-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK5-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK5-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 // CHECK5-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue: // CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc: // CHECK5: omp.inner.for.inc:
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// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47
// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !47 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !47
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !47 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !47
// CHECK5-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !47 // CHECK5-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !47
// CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !47 // CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !47
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !47 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !47
// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK5-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !47 // CHECK5-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !47
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue: // CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc: // CHECK5: omp.inner.for.inc:
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// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102
// CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK6-NEXT: entry: // CHECK6-NEXT: entry:
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK6: omp.inner.for.end: // CHECK6: omp.inner.for.end:
// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK6: omp.loop.exit: // CHECK6: omp.loop.exit:
// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 // CHECK6-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
// CHECK6-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK6-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK6: .omp.final.then: // CHECK6: .omp.final.then:
// CHECK6-NEXT: store i32 10, i32* [[CONV]], align 8 // CHECK6-NEXT: store i32 10, i32* [[CONV]], align 4
// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK6: .omp.final.done: // CHECK6: .omp.final.done:
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK6-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK6-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
// CHECK6-NEXT: entry: // CHECK6-NEXT: entry:
// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK6-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
// CHECK6-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !30 // CHECK6-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK6-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK6-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK6-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK6-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK6-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !30 // CHECK6-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue: // CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK6: omp.inner.for.inc: // CHECK6: omp.inner.for.inc:
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
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// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !33 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33
// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !33 // CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33
// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !33 // CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK6-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK6-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK6-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK6-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !33 // CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue: // CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK6: omp.inner.for.inc: // CHECK6: omp.inner.for.inc:
// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
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// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9
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// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
// CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK6-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !36 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !36
// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK6-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !36 // CHECK6-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !36
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK6-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36 // CHECK6-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
// CHECK6-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double // CHECK6-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
// CHECK6-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 // CHECK6-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
// CHECK6-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float // CHECK6-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
// CHECK6-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36 // CHECK6-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
// CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK6-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36 // CHECK6-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
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// CHECK6-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK6-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4
// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK6-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 // CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 // CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
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// CHECK6: cond.false: // CHECK6: cond.false:
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK6-NEXT: br label [[COND_END]] // CHECK6-NEXT: br label [[COND_END]]
// CHECK6: cond.end: // CHECK6: cond.end:
// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
// CHECK6-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK6-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK6: omp_if.then: // CHECK6: omp_if.then:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK6: omp.inner.for.cond: // CHECK6: omp.inner.for.cond:
// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39
// CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
// CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !39 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !39
// CHECK6-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double // CHECK6-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK6-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00 // CHECK6-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK6-NEXT: store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !39 // CHECK6-NEXT: store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !39
// CHECK6-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK6-NEXT: [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !39 // CHECK6-NEXT: [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !39
// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 // CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
// CHECK6-NEXT: store double [[INC]], double* [[A7]], align 8, !llvm.access.group !39 // CHECK6-NEXT: store double [[INC]], double* [[A7]], align 8, !llvm.access.group !39
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// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK6-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] // CHECK6-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
// CHECK6-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]] // CHECK6-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]]
// CHECK6: omp.inner.for.body13: // CHECK6: omp.inner.for.body13:
// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK6-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1 // CHECK6-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1
// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]] // CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
// CHECK6-NEXT: store i32 [[ADD15]], i32* [[I]], align 4 // CHECK6-NEXT: store i32 [[ADD15]], i32* [[I]], align 4
// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double // CHECK6-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double
// CHECK6-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00 // CHECK6-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00
// CHECK6-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK6-NEXT: store double [[ADD17]], double* [[A18]], align 8 // CHECK6-NEXT: store double [[ADD17]], double* [[A18]], align 8
// CHECK6-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK6-NEXT: [[TMP21:%.*]] = load double, double* [[A19]], align 8 // CHECK6-NEXT: [[TMP21:%.*]] = load double, double* [[A19]], align 8
// CHECK6-NEXT: [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00 // CHECK6-NEXT: [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00
// CHECK6-NEXT: store double [[INC20]], double* [[A19]], align 8 // CHECK6-NEXT: store double [[INC20]], double* [[A19]], align 8
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// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK6-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK6-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK6-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK6-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK6-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK6-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK6-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK6-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK6-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK6-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK6-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK6-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK6-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK6-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK6-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !44 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !44
// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
// CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK6-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !44 // CHECK6-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !44
// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK6-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK6-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK6-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !44 // CHECK6-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK6-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !44 // CHECK6-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !44
// CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK6-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK6-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK6-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !44 // CHECK6-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !44
// CHECK6-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !44 // CHECK6-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !44
// CHECK6-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK6-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK6-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK6-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK6-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK6-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK6-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !44 // CHECK6-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !44
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK6-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK6-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK6-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 // CHECK6-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue: // CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK6: omp.inner.for.inc: // CHECK6: omp.inner.for.inc:
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// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47
// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !47 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !47
// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !47 // CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !47
// CHECK6-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !47 // CHECK6-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !47
// CHECK6-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK6-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK6-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK6-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !47 // CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !47
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !47 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !47
// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK6-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !47 // CHECK6-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !47
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue: // CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK6: omp.inner.for.inc: // CHECK6: omp.inner.for.inc:
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// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK7-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK7-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31
// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK7: omp.inner.for.body: // CHECK7: omp.inner.for.body:
// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
// CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !31 // CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !31
// CHECK7-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK7-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK7-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !31 // CHECK7-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !31
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue: // CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc: // CHECK7: omp.inner.for.inc:
// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK7-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 // CHECK7-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
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// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK7: omp.inner.for.body: // CHECK7: omp.inner.for.body:
// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34
// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !34 // CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !34 // CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue: // CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc: // CHECK7: omp.inner.for.inc:
// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
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// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
// CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK7-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK7-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 // CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]]) // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
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// CHECK7: cond.false: // CHECK7: cond.false:
// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK7-NEXT: br label [[COND_END]] // CHECK7-NEXT: br label [[COND_END]]
// CHECK7: cond.end: // CHECK7: cond.end:
// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
// CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK7: omp_if.then: // CHECK7: omp_if.then:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK7: omp.inner.for.cond: // CHECK7: omp.inner.for.cond:
// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !40 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !40
// CHECK7-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK7-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
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// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK7-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK7-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK7-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK7-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK7-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !45 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !45
// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
// CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK7-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK7-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK7-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !45 // CHECK7-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !45
// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK7-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !45 // CHECK7-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK7-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45 // CHECK7-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK7-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK7-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK7-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK7-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK7-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !45 // CHECK7-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK7-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !45 // CHECK7-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !45
// CHECK7-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK7-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK7-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK7-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK7-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK7-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK7-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !45 // CHECK7-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !45
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK7-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK7-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK7-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 // CHECK7-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue: // CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc: // CHECK7: omp.inner.for.inc:
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// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK7: omp.inner.for.body: // CHECK7: omp.inner.for.body:
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !48 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !48
// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !48 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !48
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !48 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !48
// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !48 // CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !48
// CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !48 // CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !48
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !48 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !48
// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !48 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !48
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue: // CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc: // CHECK7: omp.inner.for.inc:
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// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK8-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK8-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
// CHECK8-NEXT: entry: // CHECK8-NEXT: entry:
// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK8-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31
// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK8: omp.inner.for.body: // CHECK8: omp.inner.for.body:
// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
// CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !31 // CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !31
// CHECK8-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK8-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK8-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK8-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK8-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !31 // CHECK8-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !31
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK8: omp.body.continue: // CHECK8: omp.body.continue:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK8: omp.inner.for.inc: // CHECK8: omp.inner.for.inc:
// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK8-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 // CHECK8-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
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// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK8: omp.inner.for.body: // CHECK8: omp.inner.for.body:
// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34
// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34 // CHECK8-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34
// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !34 // CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK8-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK8-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !34 // CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK8: omp.body.continue: // CHECK8: omp.body.continue:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK8: omp.inner.for.inc: // CHECK8: omp.inner.for.inc:
// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 // CHECK8-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
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// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
// CHECK8-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 // CHECK8-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 // CHECK8-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK8-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK8-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 // CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 // CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]]) // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]])
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
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// CHECK8: cond.false: // CHECK8: cond.false:
// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK8-NEXT: br label [[COND_END]] // CHECK8-NEXT: br label [[COND_END]]
// CHECK8: cond.end: // CHECK8: cond.end:
// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
// CHECK8-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK8-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK8: omp_if.then: // CHECK8: omp_if.then:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK8: omp.inner.for.cond: // CHECK8: omp.inner.for.cond:
// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !40 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !40
// CHECK8-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK8-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
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// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 // CHECK8-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK8-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK8-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK8-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK8-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK8-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK8-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..13 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..13
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// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !45 // CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !45
// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 // CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
// CHECK8-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK8-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK8-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK8-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK8-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !45 // CHECK8-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !45
// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45 // CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK8-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !45 // CHECK8-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK8-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45 // CHECK8-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK8-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK8-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK8-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK8-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK8-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !45 // CHECK8-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK8-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !45 // CHECK8-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !45
// CHECK8-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK8-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK8-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK8-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK8-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK8-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK8-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !45 // CHECK8-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !45
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK8-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK8-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK8-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 // CHECK8-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK8: omp.body.continue: // CHECK8: omp.body.continue:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK8: omp.inner.for.inc: // CHECK8: omp.inner.for.inc:
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// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK8-NEXT: ret void // CHECK8-NEXT: ret void
// //
// //
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..16 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..16
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// CHECK8: omp.inner.for.body: // CHECK8: omp.inner.for.body:
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !48 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !48
// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !48 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !48
// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !48 // CHECK8-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !48
// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !48 // CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !48
// CHECK8-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK8-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !48 // CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !48
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !48 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !48
// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !48 // CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !48
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK8: omp.body.continue: // CHECK8: omp.body.continue:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK8: omp.inner.for.inc: // CHECK8: omp.inner.for.inc:
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// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
// CHECK17-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !18 // CHECK17-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !18 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
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// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !21 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21
// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !21 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !21 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
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// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK17-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !24 // CHECK17-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24 // CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
// CHECK17-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double // CHECK17-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
// CHECK17-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 // CHECK17-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
// CHECK17-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float // CHECK17-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
// CHECK17-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24 // CHECK17-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
// CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK17-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 // CHECK17-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
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// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK17-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK17-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK17-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK17-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK17-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK17-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK17-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK17-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK17-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK17-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
// CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK17-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27 // CHECK17-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27
// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !27 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27
// CHECK17-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK17-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK17-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !27 // CHECK17-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27
// CHECK17-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !27 // CHECK17-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27
// CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !27 // CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27
// CHECK17-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !27 // CHECK17-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK17-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK17-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK17-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK17-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK17-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK17-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK17-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !27 // CHECK17-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
// CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK17-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 // CHECK17-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
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// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
// CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !30 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30
// CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK17-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK17-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !30 // CHECK17-NEXT: store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !30
// CHECK17-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !30 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !30
// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK17-NEXT: store double [[INC]], double* [[A6]], align 8, !llvm.access.group !30 // CHECK17-NEXT: store double [[INC]], double* [[A6]], align 8, !llvm.access.group !30
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// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !33 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !33 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33
// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !33 // CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !33 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue: // CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
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// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
// CHECK18-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !18 // CHECK18-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !18 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
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// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !21 // CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21
// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !21 // CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !21 // CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK18-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK18-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
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// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24 // CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK18-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !24 // CHECK18-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24 // CHECK18-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
// CHECK18-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double // CHECK18-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
// CHECK18-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 // CHECK18-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
// CHECK18-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float // CHECK18-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
// CHECK18-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24 // CHECK18-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
// CHECK18-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK18-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK18-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 // CHECK18-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
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// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK18-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK18-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK18-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK18-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK18-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK18-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK18-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK18-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK18-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK18-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK18-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK18-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
// CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK18-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27 // CHECK18-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27
// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !27 // CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27
// CHECK18-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK18-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK18-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !27 // CHECK18-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27
// CHECK18-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !27 // CHECK18-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27
// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !27 // CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27
// CHECK18-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !27 // CHECK18-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK18-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK18-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK18-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK18-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK18-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK18-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK18-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !27 // CHECK18-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
// CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK18-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 // CHECK18-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
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// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
// CHECK18-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK18-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
// CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !30 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30
// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double // CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK18-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 // CHECK18-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !30 // CHECK18-NEXT: store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !30
// CHECK18-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !30 // CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !30
// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// CHECK18-NEXT: store double [[INC]], double* [[A6]], align 8, !llvm.access.group !30 // CHECK18-NEXT: store double [[INC]], double* [[A6]], align 8, !llvm.access.group !30
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// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !33 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !33 // CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33
// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !33 // CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !33 // CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 // CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue: // CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
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// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK19: omp.inner.for.body: // CHECK19: omp.inner.for.body:
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
// CHECK19-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !19 // CHECK19-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !19 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue: // CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK19: omp.inner.for.inc: // CHECK19: omp.inner.for.inc:
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 // CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
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// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK19: omp.inner.for.body: // CHECK19: omp.inner.for.body:
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !22 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !22 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue: // CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK19: omp.inner.for.inc: // CHECK19: omp.inner.for.inc:
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
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// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK19-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK19-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK19-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28
// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
// CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK19-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28 // CHECK19-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28
// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28
// CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK19-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28 // CHECK19-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28
// CHECK19-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !28 // CHECK19-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28
// CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !28 // CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28
// CHECK19-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !28 // CHECK19-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK19-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK19-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK19-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK19-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK19-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK19-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK19-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !28 // CHECK19-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
// CHECK19-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK19-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK19-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 // CHECK19-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue: // CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK19: omp.inner.for.inc: // CHECK19: omp.inner.for.inc:
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// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK19: omp.inner.for.body: // CHECK19: omp.inner.for.body:
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34
// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !34 // CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !34 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !34 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !34
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue: // CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK19: omp.inner.for.inc: // CHECK19: omp.inner.for.inc:
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// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK20: omp.inner.for.body: // CHECK20: omp.inner.for.body:
// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 // CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
// CHECK20-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !19 // CHECK20-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !19 // CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue: // CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK20: omp.inner.for.inc: // CHECK20: omp.inner.for.inc:
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 // CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
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// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK20: omp.inner.for.body: // CHECK20: omp.inner.for.body:
// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 // CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !22 // CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !22 // CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue: // CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK20: omp.inner.for.inc: // CHECK20: omp.inner.for.inc:
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
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// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK20-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK20-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK20-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28 // CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28
// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 // CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
// CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK20-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK20-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK20-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28 // CHECK20-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28
// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28 // CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28
// CHECK20-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK20-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK20-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28 // CHECK20-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28
// CHECK20-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !28 // CHECK20-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28
// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !28 // CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28
// CHECK20-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !28 // CHECK20-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK20-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK20-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK20-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK20-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK20-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK20-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK20-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !28 // CHECK20-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 // CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
// CHECK20-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK20-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK20-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 // CHECK20-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue: // CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK20: omp.inner.for.inc: // CHECK20: omp.inner.for.inc:
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// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK20: omp.inner.for.body: // CHECK20: omp.inner.for.body:
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34 // CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34
// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !34 // CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !34 // CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !34 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !34
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue: // CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK20: omp.inner.for.inc: // CHECK20: omp.inner.for.inc:
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// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK21-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK21-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK21-NEXT: ret void // CHECK21-NEXT: ret void
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK21-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK21-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK21-NEXT: entry: // CHECK21-NEXT: entry:
// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK21-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK21-NEXT: ret void // CHECK21-NEXT: ret void
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK21: omp.inner.for.body: // CHECK21: omp.inner.for.body:
// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
// CHECK21-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !18 // CHECK21-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK21-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK21-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK21-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !18 // CHECK21-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK21: omp.body.continue: // CHECK21: omp.body.continue:
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK21: omp.inner.for.inc: // CHECK21: omp.inner.for.inc:
// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK21-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK21-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
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// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK21-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK21-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK21-NEXT: ret void // CHECK21-NEXT: ret void
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
// CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK21: omp.inner.for.body: // CHECK21: omp.inner.for.body:
// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21
// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !21 // CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21
// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !21 // CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK21-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK21-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK21-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK21-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !21 // CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK21: omp.body.continue: // CHECK21: omp.body.continue:
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK21: omp.inner.for.inc: // CHECK21: omp.inner.for.inc:
// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK21-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK21-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
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// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK21-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK21-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK21-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK21-NEXT: ret void // CHECK21-NEXT: ret void
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
// CHECK21-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK21-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK21-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK21: omp.inner.for.body: // CHECK21: omp.inner.for.body:
// CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
// CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK21-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !24 // CHECK21-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK21-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24 // CHECK21-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
// CHECK21-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double // CHECK21-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
// CHECK21-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 // CHECK21-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
// CHECK21-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float // CHECK21-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
// CHECK21-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24 // CHECK21-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
// CHECK21-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK21-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK21-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 // CHECK21-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
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// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK21-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK21-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK21-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK21-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK21-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK21-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK21-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK21-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK21-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK21-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK21-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK21-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK21-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK21-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK21-NEXT: ret void // CHECK21-NEXT: ret void
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK21-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK21-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK21-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK21-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK21-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK21-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK21-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK21-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK21-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK21-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK21-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK21-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK21-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK21-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK21-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK21-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK21-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK21: omp.inner.for.body: // CHECK21: omp.inner.for.body:
// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27
// CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
// CHECK21-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK21-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK21-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK21-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK21-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27 // CHECK21-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27
// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !27 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27
// CHECK21-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK21-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK21-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !27 // CHECK21-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27
// CHECK21-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !27 // CHECK21-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27
// CHECK21-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK21-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK21-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK21-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK21-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !27 // CHECK21-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27
// CHECK21-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !27 // CHECK21-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK21-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK21-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK21-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK21-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK21-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK21-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK21-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !27 // CHECK21-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
// CHECK21-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK21-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK21-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 // CHECK21-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK21: omp.body.continue: // CHECK21: omp.body.continue:
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK21: omp.inner.for.inc: // CHECK21: omp.inner.for.inc:
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// CHECK21-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK21-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK21-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK21-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK21-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4 // CHECK21-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4
// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK21-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK21-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK21-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 // CHECK21-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
// CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]]) // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]])
// CHECK21-NEXT: ret void // CHECK21-NEXT: ret void
// //
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// CHECK21: cond.false: // CHECK21: cond.false:
// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK21-NEXT: br label [[COND_END]] // CHECK21-NEXT: br label [[COND_END]]
// CHECK21: cond.end: // CHECK21: cond.end:
// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
// CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK21-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
// CHECK21-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK21-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK21: omp_if.then: // CHECK21: omp_if.then:
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK21: omp.inner.for.cond: // CHECK21: omp.inner.for.cond:
// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
// CHECK21-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK21-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
// CHECK21-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK21: omp.inner.for.body: // CHECK21: omp.inner.for.body:
// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !30 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30
// CHECK21-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double // CHECK21-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK21-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00 // CHECK21-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK21-NEXT: store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !30 // CHECK21-NEXT: store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !30
// CHECK21-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK21-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK21-NEXT: [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !30 // CHECK21-NEXT: [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !30
// CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 // CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
// CHECK21-NEXT: store double [[INC]], double* [[A7]], align 8, !llvm.access.group !30 // CHECK21-NEXT: store double [[INC]], double* [[A7]], align 8, !llvm.access.group !30
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// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK21-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] // CHECK21-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
// CHECK21-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]] // CHECK21-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]]
// CHECK21: omp.inner.for.body13: // CHECK21: omp.inner.for.body13:
// CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK21-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1 // CHECK21-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1
// CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]] // CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
// CHECK21-NEXT: store i32 [[ADD15]], i32* [[I]], align 4 // CHECK21-NEXT: store i32 [[ADD15]], i32* [[I]], align 4
// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double // CHECK21-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double
// CHECK21-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00 // CHECK21-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00
// CHECK21-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK21-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK21-NEXT: store double [[ADD17]], double* [[A18]], align 8 // CHECK21-NEXT: store double [[ADD17]], double* [[A18]], align 8
// CHECK21-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK21-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK21-NEXT: [[TMP21:%.*]] = load double, double* [[A19]], align 8 // CHECK21-NEXT: [[TMP21:%.*]] = load double, double* [[A19]], align 8
// CHECK21-NEXT: [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00 // CHECK21-NEXT: [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00
// CHECK21-NEXT: store double [[INC20]], double* [[A19]], align 8 // CHECK21-NEXT: store double [[INC20]], double* [[A19]], align 8
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// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK21-NEXT: ret void // CHECK21-NEXT: ret void
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
// CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK21: omp.inner.for.body: // CHECK21: omp.inner.for.body:
// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35
// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK21-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !35 // CHECK21-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !35
// CHECK21-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK21-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK21-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK21-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !35 // CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !35
// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK21-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK21-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK21: omp.body.continue: // CHECK21: omp.body.continue:
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK21: omp.inner.for.inc: // CHECK21: omp.inner.for.inc:
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// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK22-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK22-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 // CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
// CHECK22-NEXT: ret void // CHECK22-NEXT: ret void
// //
// //
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK22-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK22-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
// CHECK22-NEXT: entry: // CHECK22-NEXT: entry:
// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK22-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK22-NEXT: ret void // CHECK22-NEXT: ret void
// //
// //
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 // CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK22: omp.inner.for.body: // CHECK22: omp.inner.for.body:
// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 // CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
// CHECK22-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !18 // CHECK22-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK22-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK22-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK22-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK22-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK22-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !18 // CHECK22-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK22: omp.body.continue: // CHECK22: omp.body.continue:
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK22: omp.inner.for.inc: // CHECK22: omp.inner.for.inc:
// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK22-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK22-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
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// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 // CHECK22-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 // CHECK22-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
// CHECK22-NEXT: ret void // CHECK22-NEXT: ret void
// //
// //
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 // CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
// CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK22: omp.inner.for.body: // CHECK22: omp.inner.for.body:
// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 // CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21
// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !21 // CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21
// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !21 // CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK22-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 // CHECK22-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK22-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK22-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !21 // CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK22: omp.body.continue: // CHECK22: omp.body.continue:
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK22: omp.inner.for.inc: // CHECK22: omp.inner.for.inc:
// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK22-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 // CHECK22-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
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// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK22-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
// CHECK22-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 // CHECK22-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 // CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK22-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 // CHECK22-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK22-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 // CHECK22-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 // CHECK22-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
// CHECK22-NEXT: ret void // CHECK22-NEXT: ret void
// //
// //
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 // CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
// CHECK22-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK22-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK22-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK22-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK22: omp.inner.for.body: // CHECK22: omp.inner.for.body:
// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 // CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 // CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24 // CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK22-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !24 // CHECK22-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK22-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24 // CHECK22-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
// CHECK22-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double // CHECK22-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
// CHECK22-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 // CHECK22-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
// CHECK22-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float // CHECK22-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
// CHECK22-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24 // CHECK22-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
// CHECK22-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 // CHECK22-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
// CHECK22-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 // CHECK22-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
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// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK22-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK22-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 // CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 // CHECK22-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK22-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK22-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK22-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK22-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 // CHECK22-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK22-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK22-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK22-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* // CHECK22-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK22-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 // CHECK22-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 // CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK22-NEXT: ret void // CHECK22-NEXT: ret void
// //
// //
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK22-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 // CHECK22-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK22-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK22-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK22-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK22-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] // CHECK22-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
// CHECK22-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 // CHECK22-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
// CHECK22-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 // CHECK22-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1
// CHECK22-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 // CHECK22-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK22-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 // CHECK22-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1
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// CHECK22-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] // CHECK22-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
// CHECK22-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK22-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK22: omp.inner.for.body: // CHECK22: omp.inner.for.body:
// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27 // CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27
// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 // CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
// CHECK22-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK22-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK22-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK22-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK22-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27 // CHECK22-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27
// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !27 // CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27
// CHECK22-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK22-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK22-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !27 // CHECK22-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27
// CHECK22-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !27 // CHECK22-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27
// CHECK22-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 // CHECK22-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK22-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 // CHECK22-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK22-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 // CHECK22-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
// CHECK22-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !27 // CHECK22-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27
// CHECK22-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !27 // CHECK22-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK22-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 // CHECK22-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK22-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 // CHECK22-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK22-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 // CHECK22-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
// CHECK22-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !27 // CHECK22-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 // CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
// CHECK22-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK22-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK22-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 // CHECK22-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK22: omp.body.continue: // CHECK22: omp.body.continue:
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK22: omp.inner.for.inc: // CHECK22: omp.inner.for.inc:
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// CHECK22-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 // CHECK22-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK22-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK22-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 // CHECK22-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4 // CHECK22-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4
// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK22-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK22-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 // CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK22-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK22-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK22-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 // CHECK22-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
// CHECK22-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK22-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]]) // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]])
// CHECK22-NEXT: ret void // CHECK22-NEXT: ret void
// //
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// CHECK22: cond.false: // CHECK22: cond.false:
// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK22-NEXT: br label [[COND_END]] // CHECK22-NEXT: br label [[COND_END]]
// CHECK22: cond.end: // CHECK22: cond.end:
// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] // CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK22-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK22-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
// CHECK22-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8 // CHECK22-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK22: omp_if.then: // CHECK22: omp_if.then:
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK22: omp.inner.for.cond: // CHECK22: omp.inner.for.cond:
// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30 // CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
// CHECK22-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK22-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
// CHECK22-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK22-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK22: omp.inner.for.body: // CHECK22: omp.inner.for.body:
// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 // CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30 // CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !30 // CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30
// CHECK22-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double // CHECK22-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK22-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00 // CHECK22-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK22-NEXT: store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !30 // CHECK22-NEXT: store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !30
// CHECK22-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK22-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK22-NEXT: [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !30 // CHECK22-NEXT: [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !30
// CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 // CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
// CHECK22-NEXT: store double [[INC]], double* [[A7]], align 8, !llvm.access.group !30 // CHECK22-NEXT: store double [[INC]], double* [[A7]], align 8, !llvm.access.group !30
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// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK22-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] // CHECK22-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
// CHECK22-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]] // CHECK22-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]]
// CHECK22: omp.inner.for.body13: // CHECK22: omp.inner.for.body13:
// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK22-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1 // CHECK22-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1
// CHECK22-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]] // CHECK22-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
// CHECK22-NEXT: store i32 [[ADD15]], i32* [[I]], align 4 // CHECK22-NEXT: store i32 [[ADD15]], i32* [[I]], align 4
// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double // CHECK22-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double
// CHECK22-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00 // CHECK22-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00
// CHECK22-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK22-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK22-NEXT: store double [[ADD17]], double* [[A18]], align 8 // CHECK22-NEXT: store double [[ADD17]], double* [[A18]], align 8
// CHECK22-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK22-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK22-NEXT: [[TMP21:%.*]] = load double, double* [[A19]], align 8 // CHECK22-NEXT: [[TMP21:%.*]] = load double, double* [[A19]], align 8
// CHECK22-NEXT: [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00 // CHECK22-NEXT: [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00
// CHECK22-NEXT: store double [[INC20]], double* [[A19]], align 8 // CHECK22-NEXT: store double [[INC20]], double* [[A19]], align 8
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// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 // CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 // CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* // CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 // CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 // CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK22-NEXT: ret void // CHECK22-NEXT: ret void
// //
// //
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35 // CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
// CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK22: omp.inner.for.body: // CHECK22: omp.inner.for.body:
// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35 // CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35
// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !35 // CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK22-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !35 // CHECK22-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !35
// CHECK22-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 // CHECK22-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 // CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK22-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 // CHECK22-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
// CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !35 // CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !35
// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK22-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !35 // CHECK22-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK22: omp.body.continue: // CHECK22: omp.body.continue:
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK22: omp.inner.for.inc: // CHECK22: omp.inner.for.inc:
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// CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK23-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK23-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK23-NEXT: ret void // CHECK23-NEXT: ret void
// //
// //
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK23-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK23-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK23-NEXT: entry: // CHECK23-NEXT: entry:
// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK23-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK23-NEXT: ret void // CHECK23-NEXT: ret void
// //
// //
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK23: omp.inner.for.body: // CHECK23: omp.inner.for.body:
// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
// CHECK23-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !19 // CHECK23-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK23-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK23-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK23-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !19 // CHECK23-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK23: omp.body.continue: // CHECK23: omp.body.continue:
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK23: omp.inner.for.inc: // CHECK23: omp.inner.for.inc:
// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
// CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK23-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 // CHECK23-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
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// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK23-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK23-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK23-NEXT: ret void // CHECK23-NEXT: ret void
// //
// //
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK23: omp.inner.for.body: // CHECK23: omp.inner.for.body:
// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22 // CHECK23-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
// CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !22 // CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !22 // CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK23: omp.body.continue: // CHECK23: omp.body.continue:
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK23: omp.inner.for.inc: // CHECK23: omp.inner.for.inc:
// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK23-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK23-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
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// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 // CHECK23-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK23-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK23-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK23-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK23-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK23-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK23-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK23-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK23-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK23-NEXT: ret void // CHECK23-NEXT: ret void
// //
// //
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28
// CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
// CHECK23-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK23-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK23-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK23-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK23-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28 // CHECK23-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28
// CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28
// CHECK23-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK23-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK23-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28 // CHECK23-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28
// CHECK23-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !28 // CHECK23-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28
// CHECK23-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK23-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK23-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK23-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK23-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK23-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK23-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !28 // CHECK23-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28
// CHECK23-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !28 // CHECK23-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK23-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK23-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK23-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK23-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK23-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK23-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK23-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !28 // CHECK23-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
// CHECK23-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK23-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK23-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 // CHECK23-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK23: omp.body.continue: // CHECK23: omp.body.continue:
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK23: omp.inner.for.inc: // CHECK23: omp.inner.for.inc:
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// CHECK23-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK23-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
// CHECK23-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 // CHECK23-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 // CHECK23-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK23-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK23-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK23-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 // CHECK23-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]]) // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]])
// CHECK23-NEXT: ret void // CHECK23-NEXT: ret void
// //
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// CHECK23: cond.false: // CHECK23: cond.false:
// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK23-NEXT: br label [[COND_END]] // CHECK23-NEXT: br label [[COND_END]]
// CHECK23: cond.end: // CHECK23: cond.end:
// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
// CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK23-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK23-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
// CHECK23-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK23-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK23: omp_if.then: // CHECK23: omp_if.then:
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK23: omp.inner.for.cond: // CHECK23: omp.inner.for.cond:
// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31
// CHECK23-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK23-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
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// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK23-NEXT: ret void // CHECK23-NEXT: ret void
// //
// //
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK23: omp.inner.for.body: // CHECK23: omp.inner.for.body:
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !36 // CHECK23-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
// CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !36 // CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !36
// CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !36 // CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !36
// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !36 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !36
// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !36 // CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !36
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK23: omp.body.continue: // CHECK23: omp.body.continue:
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK23: omp.inner.for.inc: // CHECK23: omp.inner.for.inc:
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// CHECK24-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) // CHECK24-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK24-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK24-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 // CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
// CHECK24-NEXT: ret void // CHECK24-NEXT: ret void
// //
// //
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined.
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// //
// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
// CHECK24-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK24-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
// CHECK24-NEXT: entry: // CHECK24-NEXT: entry:
// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 // CHECK24-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
// CHECK24-NEXT: ret void // CHECK24-NEXT: ret void
// //
// //
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK24: omp.inner.for.body: // CHECK24: omp.inner.for.body:
// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 // CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 // CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
// CHECK24-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !19 // CHECK24-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK24-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 // CHECK24-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK24-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK24-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
// CHECK24-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !19 // CHECK24-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK24: omp.body.continue: // CHECK24: omp.body.continue:
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK24: omp.inner.for.inc: // CHECK24: omp.inner.for.inc:
// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 // CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
// CHECK24-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK24-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK24-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 // CHECK24-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
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// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 // CHECK24-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 // CHECK24-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
// CHECK24-NEXT: ret void // CHECK24-NEXT: ret void
// //
// //
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK24: omp.inner.for.body: // CHECK24: omp.inner.for.body:
// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 // CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22 // CHECK24-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
// CHECK24-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !22 // CHECK24-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK24-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 // CHECK24-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !22 // CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK24: omp.body.continue: // CHECK24: omp.body.continue:
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK24: omp.inner.for.inc: // CHECK24: omp.inner.for.inc:
// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK24-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 // CHECK24-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
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// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* // CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 // CHECK24-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
// CHECK24-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK24-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK24-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK24-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK24-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4 // CHECK24-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* // CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK24-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 // CHECK24-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
// CHECK24-NEXT: ret void // CHECK24-NEXT: ret void
// //
// //
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28 // CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28
// CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 // CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
// CHECK24-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 // CHECK24-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK24-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] // CHECK24-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK24-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28 // CHECK24-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28
// CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28 // CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28
// CHECK24-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK24-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK24-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28 // CHECK24-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28
// CHECK24-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !28 // CHECK24-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28
// CHECK24-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 // CHECK24-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK24-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK24-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK24-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 // CHECK24-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
// CHECK24-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !28 // CHECK24-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28
// CHECK24-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !28 // CHECK24-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK24-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 // CHECK24-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK24-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 // CHECK24-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK24-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 // CHECK24-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
// CHECK24-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !28 // CHECK24-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 // CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
// CHECK24-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK24-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK24-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 // CHECK24-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK24: omp.body.continue: // CHECK24: omp.body.continue:
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK24: omp.inner.for.inc: // CHECK24: omp.inner.for.inc:
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// CHECK24-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 // CHECK24-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
// CHECK24-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 // CHECK24-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* // CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 // CHECK24-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK24-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK24-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 // CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK24-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK24-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK24-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 // CHECK24-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 // CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]]) // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]])
// CHECK24-NEXT: ret void // CHECK24-NEXT: ret void
// //
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// CHECK24: cond.false: // CHECK24: cond.false:
// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK24-NEXT: br label [[COND_END]] // CHECK24-NEXT: br label [[COND_END]]
// CHECK24: cond.end: // CHECK24: cond.end:
// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] // CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK24-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK24-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
// CHECK24-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK24-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1 // CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK24: omp_if.then: // CHECK24: omp_if.then:
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK24: omp.inner.for.cond: // CHECK24: omp.inner.for.cond:
// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 // CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31 // CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31
// CHECK24-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK24-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
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// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 // CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 // CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* // CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 // CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 // CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* // CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 // CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
// CHECK24-NEXT: ret void // CHECK24-NEXT: ret void
// //
// //
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..6 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK24: omp.inner.for.body: // CHECK24: omp.inner.for.body:
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36 // CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36 // CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !36 // CHECK24-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !36 // CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !36
// CHECK24-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 // CHECK24-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 // CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
// CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !36 // CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !36
// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !36 // CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !36
// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !36 // CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !36
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK24: omp.body.continue: // CHECK24: omp.body.continue:
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK24: omp.inner.for.inc: // CHECK24: omp.inner.for.inc:
▲ Show 20 Lines • Show All 4,281 Lines • Show Last 20 Lines

clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp

Show First 20 Lines • Show All 1,126 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 // CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
// CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 // CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 // CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 // CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
// CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 // CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
▲ Show 20 Lines • Show All 1,970 Lines • Show Last 20 Lines

clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,327 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK9: omp.precond.then: // CHECK9: omp.precond.then:
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK9: omp.dispatch.cond: // CHECK9: omp.dispatch.cond:
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK9-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
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// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
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// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP3]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP5]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK10: omp.precond.then: // CHECK10: omp.precond.then:
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK10: omp.dispatch.cond: // CHECK10: omp.dispatch.cond:
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
// CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
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clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp

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// CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]]
// CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8*
// CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* // CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8, !llvm.access.group !5 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1
// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
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// CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 // CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11 // CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]]
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// CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 // CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]]
// CHECK2-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK2-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8*
// CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* // CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8, !llvm.access.group !5 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1
// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
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// CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
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// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 // CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11 // CHECK2-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]]
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// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !4 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4
// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !4 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4
// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4
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// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 // CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !4 // CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4
// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !4 // CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4
// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4
// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4
// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4
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clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp

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// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[G_CASTED]] to double* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[G_CASTED]] to double*
// CHECK1-NEXT: store double [[TMP0]], double* [[CONV4]], align 8 // CHECK1-NEXT: store double [[TMP0]], double* [[CONV4]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load volatile double, double* [[TMP2]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load volatile double, double* [[TMP2]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[G1_CASTED]] to double* // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK1-NEXT: store double [[TMP3]], double* [[CONV5]], align 8 // CHECK1-NEXT: store double [[TMP3]], double* [[CONV5]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV6]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 4
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float* // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK1-NEXT: store float [[TMP7]], float* [[CONV7]], align 4 // CHECK1-NEXT: store float [[TMP7]], float* [[CONV7]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK1: .omp.lastprivate.then: // CHECK1: .omp.lastprivate.then:
// CHECK1-NEXT: [[TMP20:%.*]] = load double, double* [[G5]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load double, double* [[G5]], align 8
// CHECK1-NEXT: store volatile double [[TMP20]], double* [[CONV]], align 8 // CHECK1-NEXT: store volatile double [[TMP20]], double* [[CONV]], align 8
// CHECK1-NEXT: [[TMP21:%.*]] = load double*, double** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load double*, double** [[_TMP7]], align 8
// CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8
// CHECK1-NEXT: store volatile double [[TMP22]], double* [[TMP0]], align 8 // CHECK1-NEXT: store volatile double [[TMP22]], double* [[TMP0]], align 8
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8 // CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR9]], align 4 // CHECK1-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR9]], align 4
// CHECK1-NEXT: store float [[TMP24]], float* [[CONV3]], align 8 // CHECK1-NEXT: store float [[TMP24]], float* [[CONV3]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done: // CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK1-SAME: () #[[ATTR5:[0-9]+]] { // CHECK1-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[G_CASTED]] to double* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[G_CASTED]] to double*
// CHECK2-NEXT: store double [[TMP0]], double* [[CONV4]], align 8 // CHECK2-NEXT: store double [[TMP0]], double* [[CONV4]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load volatile double, double* [[TMP2]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load volatile double, double* [[TMP2]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[G1_CASTED]] to double* // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK2-NEXT: store double [[TMP3]], double* [[CONV5]], align 8 // CHECK2-NEXT: store double [[TMP3]], double* [[CONV5]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV6]], align 4 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 4
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float* // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK2-NEXT: store float [[TMP7]], float* [[CONV7]], align 4 // CHECK2-NEXT: store float [[TMP7]], float* [[CONV7]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK2: .omp.lastprivate.then: // CHECK2: .omp.lastprivate.then:
// CHECK2-NEXT: [[TMP20:%.*]] = load double, double* [[G5]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load double, double* [[G5]], align 8
// CHECK2-NEXT: store volatile double [[TMP20]], double* [[CONV]], align 8 // CHECK2-NEXT: store volatile double [[TMP20]], double* [[CONV]], align 8
// CHECK2-NEXT: [[TMP21:%.*]] = load double*, double** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP21:%.*]] = load double*, double** [[_TMP7]], align 8
// CHECK2-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8 // CHECK2-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8
// CHECK2-NEXT: store volatile double [[TMP22]], double* [[TMP0]], align 8 // CHECK2-NEXT: store volatile double [[TMP22]], double* [[TMP0]], align 8
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK2-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8 // CHECK2-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR9]], align 4 // CHECK2-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR9]], align 4
// CHECK2-NEXT: store float [[TMP24]], float* [[CONV3]], align 8 // CHECK2-NEXT: store float [[TMP24]], float* [[CONV3]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done: // CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK2-SAME: () #[[ATTR5:[0-9]+]] { // CHECK2-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK9-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: store i32 2, i32* [[I]], align 4 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK9: .omp.final.done: // CHECK9: .omp.final.done:
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 // CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
// CHECK9-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK9-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK9: .omp.lastprivate.then: // CHECK9: .omp.lastprivate.then:
// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4
// CHECK9-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* // CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* // CHECK9-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S*
// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2
// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP29]] // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP29]]
// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK9: omp.arraycpy.body: // CHECK9: omp.arraycpy.body:
// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK9-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK9-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
// CHECK9-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK9-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false)
// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]]
// CHECK9: omp.arraycpy.done14: // CHECK9: omp.arraycpy.done14:
// CHECK9-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8
// CHECK9-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP3]] to i8* // CHECK9-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP3]] to i8*
// CHECK9-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* // CHECK9-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK9-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 8 // CHECK9-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 4
// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK9: .omp.lastprivate.done: // CHECK9: .omp.lastprivate.done:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR5]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR5]]
// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2
// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK9: arraydestroy.body: // CHECK9: arraydestroy.body:
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
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// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
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// CHECK9-NEXT: store i32 2, i32* [[I]], align 4 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK9: .omp.final.done: // CHECK9: .omp.final.done:
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 // CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
// CHECK9-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK9-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK9: .omp.lastprivate.then: // CHECK9: .omp.lastprivate.then:
// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4
// CHECK9-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* // CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
// CHECK9-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* // CHECK9-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2
// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP29]] // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP29]]
// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
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// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK10-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 // CHECK10-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 // CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: store i32 2, i32* [[I]], align 4 // CHECK10-NEXT: store i32 2, i32* [[I]], align 4
// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK10: .omp.final.done: // CHECK10: .omp.final.done:
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 // CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
// CHECK10-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK10-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK10: .omp.lastprivate.then: // CHECK10: .omp.lastprivate.then:
// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4
// CHECK10-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* // CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
// CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0 // CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
// CHECK10-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S* // CHECK10-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S*
// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 // CHECK10-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2
// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP29]] // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN13]], [[TMP29]]
// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK10: omp.arraycpy.body: // CHECK10: omp.arraycpy.body:
// CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK10-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK10-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
// CHECK10-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK10-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false) // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false)
// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]] // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]]
// CHECK10: omp.arraycpy.done14: // CHECK10: omp.arraycpy.done14:
// CHECK10-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8
// CHECK10-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP3]] to i8* // CHECK10-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP3]] to i8*
// CHECK10-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8* // CHECK10-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR8]], align 4
// CHECK10-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 8 // CHECK10-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 4
// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK10: .omp.lastprivate.done: // CHECK10: .omp.lastprivate.done:
// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR5]] // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR5]]
// CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2
// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK10: arraydestroy.body: // CHECK10: arraydestroy.body:
// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
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// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
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// CHECK10-NEXT: store i32 2, i32* [[I]], align 4 // CHECK10-NEXT: store i32 2, i32* [[I]], align 4
// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK10: .omp.final.done: // CHECK10: .omp.final.done:
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 // CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
// CHECK10-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // CHECK10-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK10: .omp.lastprivate.then: // CHECK10: .omp.lastprivate.then:
// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4
// CHECK10-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* // CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8* // CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false) // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
// CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0 // CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
// CHECK10-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0* // CHECK10-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
// CHECK10-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK10-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2
// CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP29]] // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN11]], [[TMP29]]
// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
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clang/test/OpenMP/target_teams_num_teams_codegen.cpp

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// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK1-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK1-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK1-SAME: () #[[ATTR5:[0-9]+]] { // CHECK1-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @__tgt_register_requires(i64 1) // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK2-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK2-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK2-SAME: () #[[ATTR5:[0-9]+]] { // CHECK2-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
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// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK3-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK4-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK4-SAME: () #[[ATTR5:[0-9]+]] { // CHECK4-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: call void @__tgt_register_requires(i64 1) // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
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// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
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// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
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// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
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// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_Z3bari // CHECK17-LABEL: define {{[^@]+}}@_Z3bari
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// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
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// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK17-SAME: () #[[ATTR5:[0-9]+]] { // CHECK17-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) // CHECK17-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
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// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
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// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK18-SAME: () #[[ATTR5:[0-9]+]] { // CHECK18-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) // CHECK18-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
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// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK20-SAME: () #[[ATTR5:[0-9]+]] { // CHECK20-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) // CHECK20-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
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// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
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// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
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// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
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// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) // CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //

clang/test/OpenMP/target_teams_thread_limit_codegen.cpp

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// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK1-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK1-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK1-SAME: () #[[ATTR5:[0-9]+]] { // CHECK1-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void @__tgt_register_requires(i64 1) // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK2-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK2-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK2-SAME: () #[[ATTR5:[0-9]+]] { // CHECK2-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
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// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK3-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK4-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK4-SAME: () #[[ATTR5:[0-9]+]] { // CHECK4-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: call void @__tgt_register_requires(i64 1) // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
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// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
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// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
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// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: ret void // CHECK11-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
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// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: ret void // CHECK12-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_Z3bari // CHECK17-LABEL: define {{[^@]+}}@_Z3bari
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// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
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// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK17-SAME: () #[[ATTR5:[0-9]+]] { // CHECK17-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) // CHECK17-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
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// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
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// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
// //
// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK18-SAME: () #[[ATTR5:[0-9]+]] { // CHECK18-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK18-NEXT: entry: // CHECK18-NEXT: entry:
// CHECK18-NEXT: call void @__tgt_register_requires(i64 1) // CHECK18-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
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// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
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// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK20-SAME: () #[[ATTR5:[0-9]+]] { // CHECK20-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK20-NEXT: entry: // CHECK20-NEXT: entry:
// CHECK20-NEXT: call void @__tgt_register_requires(i64 1) // CHECK20-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK20-NEXT: ret void // CHECK20-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
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// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
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// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]]) // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double // CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
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// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 // CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 // CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
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// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: ret void // CHECK27-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
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// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 // CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024) // CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 // CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 // CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //
// //
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
// CHECK28-NEXT: entry: // CHECK28-NEXT: entry:
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: ret void // CHECK28-NEXT: ret void
// //

clang/test/OpenMP/teams_codegen.cpp

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// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 // CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[CONV1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[CONV1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 // CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[GBLB]], i64* [[GBLB_ADDR]], align 8 // CHECK1-NEXT: store i64 [[GBLB]], i64* [[GBLB_ADDR]], align 8
// CHECK1-NEXT: store i64 [[LC]], i64* [[LC_ADDR]], align 8 // CHECK1-NEXT: store i64 [[LC]], i64* [[LC_ADDR]], align 8
// CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 // CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[GBLA_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[GBLA_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[LC_ADDR]] to float* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[LC_ADDR]] to float*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[GBLB_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[GBLB_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load float, float* [[CONV2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load float, float* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV4:%.*]] = fptosi float [[TMP4]] to i64 // CHECK1-NEXT: [[CONV4:%.*]] = fptosi float [[TMP4]] to i64
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP3]], [[CONV4]] // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP3]], [[CONV4]]
// CHECK1-NEXT: [[TMP5:%.*]] = trunc i64 [[ADD5]] to i32 // CHECK1-NEXT: [[TMP5:%.*]] = trunc i64 [[ADD5]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[TMP5]]) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[TMP5]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[CONV3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[CONV3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 // CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[CONV1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[CONV1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 // CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[GBLB]], i64* [[GBLB_ADDR]], align 8 // CHECK2-NEXT: store i64 [[GBLB]], i64* [[GBLB_ADDR]], align 8
// CHECK2-NEXT: store i64 [[LC]], i64* [[LC_ADDR]], align 8 // CHECK2-NEXT: store i64 [[LC]], i64* [[LC_ADDR]], align 8
// CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 // CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[GBLA_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[GBLA_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[LC_ADDR]] to float* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[LC_ADDR]] to float*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[GBLB_ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[GBLB_ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load float, float* [[CONV2]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load float, float* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV4:%.*]] = fptosi float [[TMP4]] to i64 // CHECK2-NEXT: [[CONV4:%.*]] = fptosi float [[TMP4]] to i64
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP3]], [[CONV4]] // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP3]], [[CONV4]]
// CHECK2-NEXT: [[TMP5:%.*]] = trunc i64 [[ADD5]] to i32 // CHECK2-NEXT: [[TMP5:%.*]] = trunc i64 [[ADD5]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[TMP5]]) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[TMP5]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[CONV3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[CONV3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
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// CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
// CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK33-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK33-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK33-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK33-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK33-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 // CHECK33-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
// CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK33-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK33-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK33-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK33-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]]) // CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]])
// CHECK33-NEXT: ret void // CHECK33-NEXT: ret void
// //
// //
// CHECK33-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK33-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
// CHECK33-NEXT: entry: // CHECK33-NEXT: entry:
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// CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8
// CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK33-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK33-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK33-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK33-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK33-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 // CHECK33-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8
// CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK33-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK33-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) // CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]])
// CHECK33-NEXT: ret void // CHECK33-NEXT: ret void
// //
// //
// CHECK33-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK33-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] {
// CHECK33-NEXT: entry: // CHECK33-NEXT: entry:
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// CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
// CHECK34-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK34-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK34-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK34-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK34-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK34-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK34-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 // CHECK34-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
// CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK34-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK34-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]]) // CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]])
// CHECK34-NEXT: ret void // CHECK34-NEXT: ret void
// //
// //
// CHECK34-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK34-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
// CHECK34-NEXT: entry: // CHECK34-NEXT: entry:
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// CHECK34-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK34-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8
// CHECK34-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK34-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK34-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK34-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK34-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 // CHECK34-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK34-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 // CHECK34-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8
// CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* // CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) // CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) // CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]])
// CHECK34-NEXT: ret void // CHECK34-NEXT: ret void
// //
// //
// CHECK34-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK34-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] {
// CHECK34-NEXT: entry: // CHECK34-NEXT: entry:
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clang/test/OpenMP/teams_distribute_codegen.cpp

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// CHECK1-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK1-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK1-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK1-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK2-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK2-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK2-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK2-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK25-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK25-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK25-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK25-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
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// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK26-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK26-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK26-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK26-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
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clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp

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// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
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// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK9: omp.precond.then: // CHECK9: omp.precond.then:
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK9: omp.dispatch.cond: // CHECK9: omp.dispatch.cond:
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
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// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
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// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK10: omp.precond.then: // CHECK10: omp.precond.then:
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK10: omp.dispatch.cond: // CHECK10: omp.dispatch.cond:
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
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clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp

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// CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]]
// CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8*
// CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* // CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1
// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]]
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// CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]]
// CHECK2-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK2-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8*
// CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* // CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1
// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
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// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]]
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// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4
// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8
// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
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// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4
// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8
// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8
// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8
// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
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clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// CHECK1-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK1-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK1-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK1-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK2-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK2-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK2-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK2-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]])
// CHECK25-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK25-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK25-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK25-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
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// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]])
// CHECK26-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK26-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK26-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK26-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
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clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp

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Show First 20 Lines • Show All 3,061 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
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// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK9: omp.precond.then: // CHECK9: omp.precond.then:
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK9: cond.true: // CHECK9: cond.true:
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// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK9-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK9-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 // CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 // CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4
// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]])
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
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// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK9: cond.true: // CHECK9: cond.true:
// CHECK9-NEXT: br label [[COND_END:%.*]] // CHECK9-NEXT: br label [[COND_END:%.*]]
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// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
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// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK10: omp.precond.then: // CHECK10: omp.precond.then:
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK10: cond.true: // CHECK10: cond.true:
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// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK10-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK10-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 // CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 // CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4
// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]])
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
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// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK10: cond.true: // CHECK10: cond.true:
// CHECK10-NEXT: br label [[COND_END:%.*]] // CHECK10-NEXT: br label [[COND_END:%.*]]
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// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp

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// CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]])
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
// CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
// CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 // CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]])
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
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// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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// CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 // CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]])
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
// CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
// CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* // CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
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// CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
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// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 // CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]])
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
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// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 // CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 // CHECK9-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8
// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
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// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 // CHECK10-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 // CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 // CHECK10-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8 // CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8
// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
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clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp

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// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97
// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK1-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK1-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK1-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK1-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.else: // CHECK1: omp_if.else:
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 432 Lines • ▼ Show 20 Lines
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72
// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK1-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK1-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK1-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK1-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.else: // CHECK1: omp_if.else:
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 745 Lines • ▼ Show 20 Lines
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97
// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK2-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK2-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK2-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK2-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.else: // CHECK2: omp_if.else:
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 432 Lines • ▼ Show 20 Lines
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72
// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK2-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK2-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK2-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK2-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.else: // CHECK2: omp_if.else:
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 745 Lines • ▼ Show 20 Lines
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97
// CHECK5-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK5-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK5-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK5-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK5-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK5-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK5-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK5-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK5-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK5: omp_if.then: // CHECK5: omp_if.then:
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK5: omp_if.else: // CHECK5: omp_if.else:
// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK5-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 432 Lines • ▼ Show 20 Lines
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72
// CHECK5-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK5-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK5-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK5-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK5-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK5-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK5-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK5-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK5-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK5: omp_if.then: // CHECK5: omp_if.then:
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]] // CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK5: omp_if.else: // CHECK5: omp_if.else:
// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK5-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 745 Lines • ▼ Show 20 Lines
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97
// CHECK6-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK6-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK6-NEXT: entry: // CHECK6-NEXT: entry:
// CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK6-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK6-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK6-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK6-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK6-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK6-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK6-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK6: omp_if.then: // CHECK6: omp_if.then:
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK6-NEXT: br label [[OMP_IF_END:%.*]] // CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK6: omp_if.else: // CHECK6: omp_if.else:
// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK6-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 432 Lines • ▼ Show 20 Lines
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72
// CHECK6-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK6-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK6-NEXT: entry: // CHECK6-NEXT: entry:
// CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK6-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK6-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK6-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK6-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK6-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK6-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK6-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK6: omp_if.then: // CHECK6: omp_if.then:
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK6-NEXT: br label [[OMP_IF_END:%.*]] // CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK6: omp_if.else: // CHECK6: omp_if.else:
// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK6-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 745 Lines • ▼ Show 20 Lines
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97
// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then: // CHECK9: omp_if.then:
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK9: omp_if.else: // CHECK9: omp_if.else:
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 432 Lines • ▼ Show 20 Lines
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72
// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then: // CHECK9: omp_if.then:
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK9: omp_if.else: // CHECK9: omp_if.else:
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 745 Lines • ▼ Show 20 Lines
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97
// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then: // CHECK10: omp_if.then:
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK10: omp_if.else: // CHECK10: omp_if.else:
// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 432 Lines • ▼ Show 20 Lines
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72
// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then: // CHECK10: omp_if.then:
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK10: omp_if.else: // CHECK10: omp_if.else:
// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 745 Lines • ▼ Show 20 Lines
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97
// CHECK13-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK13-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK13-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK13-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK13-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK13-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK13-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK13-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK13-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK13-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK13-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK13: omp_if.then: // CHECK13: omp_if.then:
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK13-NEXT: br label [[OMP_IF_END:%.*]] // CHECK13-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK13: omp_if.else: // CHECK13: omp_if.else:
// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72
// CHECK13-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK13-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK13-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK13-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK13-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK13-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK13-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK13-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK13-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK13-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK13-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK13: omp_if.then: // CHECK13: omp_if.then:
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK13-NEXT: br label [[OMP_IF_END:%.*]] // CHECK13-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK13: omp_if.else: // CHECK13: omp_if.else:
// CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK13-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97
// CHECK14-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK14-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK14-NEXT: entry: // CHECK14-NEXT: entry:
// CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK14-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK14-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK14-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK14-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK14-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK14-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK14-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK14-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK14-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK14: omp_if.then: // CHECK14: omp_if.then:
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK14-NEXT: br label [[OMP_IF_END:%.*]] // CHECK14-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK14: omp_if.else: // CHECK14: omp_if.else:
// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
▲ Show 20 Lines • Show All 432 Lines • ▼ Show 20 Lines
// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72
// CHECK14-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK14-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK14-NEXT: entry: // CHECK14-NEXT: entry:
// CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK14-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK14-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK14-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK14-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK14-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK14-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK14-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK14-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK14-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK14: omp_if.then: // CHECK14: omp_if.then:
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
// CHECK14-NEXT: br label [[OMP_IF_END:%.*]] // CHECK14-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK14: omp_if.else: // CHECK14: omp_if.else:
// CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK14-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp

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// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
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// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond: // CHECK1: omp.inner.for.cond:
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]])
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond: // CHECK1: omp.inner.for.cond:
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]])
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
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// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK2: omp.inner.for.cond: // CHECK2: omp.inner.for.cond:
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]])
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK2: omp.inner.for.cond: // CHECK2: omp.inner.for.cond:
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]])
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
// CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
// CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK5-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 // CHECK5-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
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// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond: // CHECK5: omp.inner.for.cond:
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]])
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond: // CHECK5: omp.inner.for.cond:
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]])
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
// CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK6-NEXT: entry: // CHECK6-NEXT: entry:
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK6-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 // CHECK6-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
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// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK6: omp.inner.for.cond: // CHECK6: omp.inner.for.cond:
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) // CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]])
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK6: omp.inner.for.cond: // CHECK6: omp.inner.for.cond:
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) // CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]])
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp

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// CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
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// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK13: omp.precond.then: // CHECK13: omp.precond.then:
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK13-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
// CHECK13-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK13-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK13: cond.true: // CHECK13: cond.true:
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// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK13-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK13-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
// CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 // CHECK13-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 // CHECK13-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4
// CHECK13-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]])
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
▲ Show 20 Lines • Show All 362 Lines • ▼ Show 20 Lines
// CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
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// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK13-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
// CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK13-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4 // CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4
// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]])
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK13-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK13-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK13-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK13-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) // CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]])
// CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK13: omp.dispatch.cond: // CHECK13: omp.dispatch.cond:
// CHECK13-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
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// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK13: omp.dispatch.cond: // CHECK13: omp.dispatch.cond:
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK13-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
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// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK13: omp.dispatch.cond: // CHECK13: omp.dispatch.cond:
// CHECK13-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK13-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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// CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
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// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK14: omp.precond.then: // CHECK14: omp.precond.then:
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK14-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
// CHECK14-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK14-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK14: cond.true: // CHECK14: cond.true:
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// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK14-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK14-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
// CHECK14-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 // CHECK14-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 // CHECK14-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4
// CHECK14-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]])
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
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// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK14-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
// CHECK14-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK14-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4 // CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4
// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]])
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK14-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK14-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK14-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK14-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 // CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) // CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]])
// CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK14: omp.dispatch.cond: // CHECK14: omp.dispatch.cond:
// CHECK14-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
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// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK14: omp.dispatch.cond: // CHECK14: omp.dispatch.cond:
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
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// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK14: omp.dispatch.cond: // CHECK14: omp.dispatch.cond:
// CHECK14-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK14-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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// CHECK17-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK17-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
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// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK17: omp.precond.then: // CHECK17: omp.precond.then:
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK17-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
// CHECK17-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK17-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK17: cond.true: // CHECK17: cond.true:
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// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK17-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK17-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 // CHECK17-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 // CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4
// CHECK17-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]])
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK17-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK17-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK17-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
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// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK17-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK17-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4 // CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4
// CHECK17-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]])
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK17-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK17-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) // CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]])
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK17: omp.dispatch.cond: // CHECK17: omp.dispatch.cond:
// CHECK17-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK17-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
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// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK17: omp.dispatch.cond: // CHECK17: omp.dispatch.cond:
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK17-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK17-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
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// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK17: omp.inner.for.body: // CHECK17: omp.inner.for.body:
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK17: omp.inner.for.inc: // CHECK17: omp.inner.for.inc:
// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK17: omp.dispatch.cond: // CHECK17: omp.dispatch.cond:
// CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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// CHECK18-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK18-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
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// CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK18: omp.precond.then: // CHECK18: omp.precond.then:
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK18-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
// CHECK18-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK18-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK18: cond.true: // CHECK18: cond.true:
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// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK18-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK18-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 // CHECK18-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 // CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4
// CHECK18-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]])
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK18-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK18-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK18-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
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// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK18-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK18-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK18-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4 // CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4
// CHECK18-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]])
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK18-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK18-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) // CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]])
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK18: omp.dispatch.cond: // CHECK18: omp.dispatch.cond:
// CHECK18-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK18-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
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// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK18: omp.dispatch.cond: // CHECK18: omp.dispatch.cond:
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK18-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK18-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK18-NEXT: ret void // CHECK18-NEXT: ret void
// //
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// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK18: omp.inner.for.body: // CHECK18: omp.inner.for.body:
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 // CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]])
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK18: omp.inner.for.inc: // CHECK18: omp.inner.for.inc:
// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
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// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK18-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK18-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK18: omp.dispatch.cond: // CHECK18: omp.dispatch.cond:
// CHECK18-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK18-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp

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// CHECK1-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK1-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK1-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK1-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK2-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK2-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK2-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK2-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
// CHECK25-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK25-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK25-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK25-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK25-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK25-NEXT: ret void // CHECK25-NEXT: ret void
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
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// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]]) // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
// CHECK26-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK26-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK26-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK26-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK26-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK26-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK26-NEXT: ret void // CHECK26-NEXT: ret void
// //
// //
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
// CHECK26-NEXT: entry: // CHECK26-NEXT: entry:
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clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
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// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK9: omp.precond.then: // CHECK9: omp.precond.then:
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK9: cond.true: // CHECK9: cond.true:
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// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK9-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK9-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 // CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !24 // CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24 // CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !24 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !24
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
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// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
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// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK9: cond.true: // CHECK9: cond.true:
// CHECK9-NEXT: br label [[COND_END:%.*]] // CHECK9-NEXT: br label [[COND_END:%.*]]
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// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !42 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42 // CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42 // CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
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// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
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// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK10: omp.precond.then: // CHECK10: omp.precond.then:
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK10: cond.true: // CHECK10: cond.true:
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// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK10-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK10-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 // CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !24 // CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24 // CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !24 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !24
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 // CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
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// CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
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// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK10: cond.true: // CHECK10: cond.true:
// CHECK10-NEXT: br label [[COND_END:%.*]] // CHECK10-NEXT: br label [[COND_END:%.*]]
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// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !42 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42 // CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42 // CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
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clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp

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// CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
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// CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
// CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
// CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !9 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
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// CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !14 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !14
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14 // CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14
// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14
// CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14 // CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
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// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17 // CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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// CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5 // CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5
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// CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 // CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
// CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
// CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* // CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !9 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
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// CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
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// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14
// CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 // CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
// CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !14 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !14
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14 // CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14
// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14
// CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14 // CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
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// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17 // CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
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// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4 // CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4
// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK9-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !4 // CHECK9-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4 // CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !4 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4 // CHECK9-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK9: omp.inner.for.inc: // CHECK9: omp.inner.for.inc:
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
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// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !8
// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8
// CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8
// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !8
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8
// CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8 // CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8
// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8
// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8
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// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4 // CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4 // CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4
// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK10-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !4 // CHECK10-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4 // CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !4 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4 // CHECK10-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK10: omp.inner.for.inc: // CHECK10: omp.inner.for.inc:
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4
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// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8 // CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !8
// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 // CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8
// CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8
// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8 // CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !8
// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8
// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8
// CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8 // CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8
// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8
// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !8
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clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp

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// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK1-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK1-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK1-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK1-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !38 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !38
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !38 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !38
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.else: // CHECK1: omp_if.else:
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38
// CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38 // CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38
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// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK1-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK1-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK1-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK1-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !56 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !56
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !56 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !56
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then: // CHECK1: omp_if.then:
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !56 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !56
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.else: // CHECK1: omp_if.else:
// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !56 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !56
// CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !56 // CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !56
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// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK2-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK2-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK2-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK2-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !38 // CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !38
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !38 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !38
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.else: // CHECK2: omp_if.else:
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38 // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38
// CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38 // CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38
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// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK2-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK2-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK2-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK2-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !56 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !56
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !56 // CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !56
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then: // CHECK2: omp_if.then:
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !56 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !56
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.else: // CHECK2: omp_if.else:
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !56 // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !56
// CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !56 // CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !56
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// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK3-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK3-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK3-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK3-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK3-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK3: cond.false: // CHECK3: cond.false:
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: br label [[COND_END]] // CHECK3-NEXT: br label [[COND_END]]
// CHECK3: cond.end: // CHECK3: cond.end:
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond: // CHECK3: omp.inner.for.cond:
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !35 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !35
// CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35
// CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !35 // CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !35
// CHECK3-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1 // CHECK3-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8 // CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !35 // CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !35
// CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !35 // CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !35
// CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !35 // CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !35
// CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then5: // CHECK3: omp_if.then5:
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !35 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !35
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK3: omp_if.else: // CHECK3: omp_if.else:
// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !35 // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !35
// CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !35 // CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !35
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// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]] // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]]
// CHECK3: omp.inner.for.body9: // CHECK3: omp.inner.for.body9:
// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK3-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64 // CHECK3-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 // CHECK3-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
// CHECK3-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1 // CHECK3-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK3-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8* // CHECK3-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK3-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8 // CHECK3-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1 // CHECK3-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8 // CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
// CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1 // CHECK3-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK3: omp_if.then15: // CHECK3: omp_if.then15:
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]]) // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
// CHECK3-NEXT: br label [[OMP_IF_END18:%.*]] // CHECK3-NEXT: br label [[OMP_IF_END18:%.*]]
// CHECK3: omp_if.else16: // CHECK3: omp_if.else16:
// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK3-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK3-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK3-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK3-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK3-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK3-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body: // CHECK3: omp.inner.for.body:
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !55 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !55
// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55
// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !55 // CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !55
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then: // CHECK3: omp_if.then:
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !55 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !55
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK3: omp_if.else: // CHECK3: omp_if.else:
// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !55 // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !55
// CHECK3-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !55 // CHECK3-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !55
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// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK4-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK4-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK4-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK4-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK4-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK4: cond.false: // CHECK4: cond.false:
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK4-NEXT: br label [[COND_END]] // CHECK4-NEXT: br label [[COND_END]]
// CHECK4: cond.end: // CHECK4: cond.end:
// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK4: omp.inner.for.cond: // CHECK4: omp.inner.for.cond:
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !35 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !35
// CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35
// CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !35 // CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !35
// CHECK4-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1 // CHECK4-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8 // CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !35 // CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !35
// CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !35 // CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !35
// CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !35 // CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !35
// CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then5: // CHECK4: omp_if.then5:
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !35 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !35
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.else: // CHECK4: omp_if.else:
// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !35 // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !35
// CHECK4-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !35 // CHECK4-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !35
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// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]] // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]]
// CHECK4: omp.inner.for.body9: // CHECK4: omp.inner.for.body9:
// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK4-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64 // CHECK4-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK4-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 // CHECK4-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
// CHECK4-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1 // CHECK4-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK4-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8* // CHECK4-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK4-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8 // CHECK4-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1 // CHECK4-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK4-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8 // CHECK4-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
// CHECK4-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1 // CHECK4-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK4: omp_if.then15: // CHECK4: omp_if.then15:
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]]) // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
// CHECK4-NEXT: br label [[OMP_IF_END18:%.*]] // CHECK4-NEXT: br label [[OMP_IF_END18:%.*]]
// CHECK4: omp_if.else16: // CHECK4: omp_if.else16:
// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK4-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK4-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK4-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK4-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK4-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK4-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK4-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK4-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK4: omp.inner.for.body: // CHECK4: omp.inner.for.body:
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !55 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !55
// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55
// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !55 // CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !55
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then: // CHECK4: omp_if.then:
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !55 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !55
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]] // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.else: // CHECK4: omp_if.else:
// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !55 // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !55
// CHECK4-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !55 // CHECK4-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !55
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// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42 // CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !42
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then: // CHECK9: omp_if.then:
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !42 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !42
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK9: omp_if.else: // CHECK9: omp_if.else:
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !42 // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !42
// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !42 // CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !42
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// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK9-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK9-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK9-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !60 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !60
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !60 // CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !60
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then: // CHECK9: omp_if.then:
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !60 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !60
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK9: omp_if.else: // CHECK9: omp_if.else:
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !60 // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !60
// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !60 // CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !60
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// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42 // CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !42
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then: // CHECK10: omp_if.then:
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !42 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !42
// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK10: omp_if.else: // CHECK10: omp_if.else:
// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !42 // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !42
// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !42 // CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !42
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// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK10-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK10-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK10-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60
// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !60 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !60
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !60 // CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !60
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then: // CHECK10: omp_if.then:
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !60 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !60
// CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK10: omp_if.else: // CHECK10: omp_if.else:
// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !60 // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !60
// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !60 // CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !60
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// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK11-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK11-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK11-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK11-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK11-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK11: cond.false: // CHECK11: cond.false:
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: br label [[COND_END]] // CHECK11-NEXT: br label [[COND_END]]
// CHECK11: cond.end: // CHECK11: cond.end:
// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK11: omp_if.then: // CHECK11: omp_if.then:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK11: omp.inner.for.cond: // CHECK11: omp.inner.for.cond:
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK11: omp.inner.for.body: // CHECK11: omp.inner.for.body:
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !39 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !39
// CHECK11-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK11-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39
// CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK11-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !39 // CHECK11-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !39
// CHECK11-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1 // CHECK11-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8 // CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !39 // CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !39
// CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !39 // CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !39
// CHECK11-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !39 // CHECK11-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !39
// CHECK11-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK11-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then5: // CHECK11: omp_if.then5:
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !39 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !39
// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK11: omp_if.else: // CHECK11: omp_if.else:
// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !39 // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !39
// CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !39 // CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !39
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// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] // CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
// CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]] // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]]
// CHECK11: omp.inner.for.body9: // CHECK11: omp.inner.for.body9:
// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK11-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64 // CHECK11-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 // CHECK11-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
// CHECK11-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1 // CHECK11-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK11-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8* // CHECK11-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK11-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8 // CHECK11-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1 // CHECK11-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
// CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1 // CHECK11-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK11: omp_if.then15: // CHECK11: omp_if.then15:
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]]) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
// CHECK11-NEXT: br label [[OMP_IF_END18:%.*]] // CHECK11-NEXT: br label [[OMP_IF_END18:%.*]]
// CHECK11: omp_if.else16: // CHECK11: omp_if.else16:
// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK11-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then: // CHECK11: omp_if.then:
// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK11-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then: // CHECK11: omp_if.then:
// CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
// CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK11-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK11-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK11-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK11-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK11-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK11: omp.inner.for.body: // CHECK11: omp.inner.for.body:
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !59 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !59
// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59
// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK11-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !59 // CHECK11-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !59
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then: // CHECK11: omp_if.then:
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !59 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !59
// CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK11: omp_if.else: // CHECK11: omp_if.else:
// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !59 // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !59
// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !59 // CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !59
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// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92
// CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK12-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK12-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK12-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK12-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK12-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK12: cond.false: // CHECK12: cond.false:
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK12-NEXT: br label [[COND_END]] // CHECK12-NEXT: br label [[COND_END]]
// CHECK12: cond.end: // CHECK12: cond.end:
// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK12: omp_if.then: // CHECK12: omp_if.then:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK12: omp.inner.for.cond: // CHECK12: omp.inner.for.cond:
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39
// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK12: omp.inner.for.body: // CHECK12: omp.inner.for.body:
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !39 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !39
// CHECK12-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK12-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39
// CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK12-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !39 // CHECK12-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !39
// CHECK12-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1 // CHECK12-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8 // CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !39 // CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !39
// CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !39 // CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !39
// CHECK12-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !39 // CHECK12-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !39
// CHECK12-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK12-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then5: // CHECK12: omp_if.then5:
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !39 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !39
// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] // CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK12: omp_if.else: // CHECK12: omp_if.else:
// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !39 // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !39
// CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !39 // CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !39
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// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]] // CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
// CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]] // CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END21:%.*]]
// CHECK12: omp.inner.for.body9: // CHECK12: omp.inner.for.body9:
// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK12-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64 // CHECK12-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK12-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 // CHECK12-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
// CHECK12-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1 // CHECK12-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK12-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8* // CHECK12-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK12-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8 // CHECK12-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1 // CHECK12-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8 // CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
// CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1 // CHECK12-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK12: omp_if.then15: // CHECK12: omp_if.then15:
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]]) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP25]])
// CHECK12-NEXT: br label [[OMP_IF_END18:%.*]] // CHECK12-NEXT: br label [[OMP_IF_END18:%.*]]
// CHECK12: omp_if.else16: // CHECK12: omp_if.else16:
// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
// CHECK12-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK12-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then: // CHECK12: omp_if.then:
// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK12-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK12-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then: // CHECK12: omp_if.then:
// CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99
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// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67
// CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] {
// CHECK12-NEXT: entry: // CHECK12-NEXT: entry:
// CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 // CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32* // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 // CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK12-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1 // CHECK12-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK12-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8 // CHECK12-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL1]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 // CHECK12-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
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// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59
// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK12: omp.inner.for.body: // CHECK12: omp.inner.for.body:
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !59 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !59
// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 // CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59
// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK12-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !59 // CHECK12-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !59
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then: // CHECK12: omp_if.then:
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !59 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !59
// CHECK12-NEXT: br label [[OMP_IF_END:%.*]] // CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK12: omp_if.else: // CHECK12: omp_if.else:
// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !59 // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !59
// CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !59 // CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !59
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clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp

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// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
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// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond: // CHECK1: omp.inner.for.cond:
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !18 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !18
// CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
// CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond: // CHECK1: omp.inner.for.cond:
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !42
// CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
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// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK2: omp.inner.for.cond: // CHECK2: omp.inner.for.cond:
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !18 // CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !18
// CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18 // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
// CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK2: omp.inner.for.cond: // CHECK2: omp.inner.for.cond:
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42 // CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !42
// CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42 // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
// CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
// CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK5-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 // CHECK5-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]]) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]])
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
// //
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// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond: // CHECK5: omp.inner.for.cond:
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !18 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !18
// CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
// CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond: // CHECK5: omp.inner.for.cond:
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body: // CHECK5: omp.inner.for.body:
// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !42
// CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
// CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR3]] {
// CHECK6-NEXT: entry: // CHECK6-NEXT: entry:
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8* // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK6-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 // CHECK6-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]]) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
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// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK6: omp.inner.for.cond: // CHECK6: omp.inner.for.cond:
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !18 // CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !18
// CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18 // CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
// CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK6: omp.inner.for.cond: // CHECK6: omp.inner.for.cond:
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body: // CHECK6: omp.inner.for.body:
// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42 // CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !42
// CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 // CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42 // CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 // CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
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// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK13: omp.precond.then: // CHECK13: omp.precond.then:
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK13-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
// CHECK13-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK13-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK13: cond.true: // CHECK13: cond.true:
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// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK13-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK13-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
// CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 // CHECK13-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !28 // CHECK13-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28 // CHECK13-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !28 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !28
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28
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// CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK13-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK13-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
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// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK13-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
// CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK13-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4, !llvm.access.group !40 // CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]), !llvm.access.group !40 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]), !llvm.access.group !40
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40
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// CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK13-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK13-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK13-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK13-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) // CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]])
// CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK13: omp.dispatch.cond: // CHECK13: omp.dispatch.cond:
// CHECK13-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
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// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58 // CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58
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// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK13: omp.dispatch.cond: // CHECK13: omp.dispatch.cond:
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK13-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK13-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK13-NEXT: ret void // CHECK13-NEXT: ret void
// //
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// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK13: omp.inner.for.body: // CHECK13: omp.inner.for.body:
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70 // CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK13: omp.inner.for.inc: // CHECK13: omp.inner.for.inc:
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70
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// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK13-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK13-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK13: omp.dispatch.cond: // CHECK13: omp.dispatch.cond:
// CHECK13-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK13-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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// CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
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// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK14: omp.precond.then: // CHECK14: omp.precond.then:
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK14-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
// CHECK14-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK14-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK14: cond.true: // CHECK14: cond.true:
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// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK14-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK14-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
// CHECK14-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 // CHECK14-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !28 // CHECK14-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28 // CHECK14-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !28 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !28
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 // CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28 // CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28
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// CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK14-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK14-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
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// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK14-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
// CHECK14-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK14-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40 // CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4, !llvm.access.group !40 // CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40 // CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]), !llvm.access.group !40 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]), !llvm.access.group !40
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40 // CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40
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// CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK14-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK14-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK14-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK14-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 // CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) // CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]])
// CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK14: omp.dispatch.cond: // CHECK14: omp.dispatch.cond:
// CHECK14-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
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// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58 // CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58 // CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58
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// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK14: omp.dispatch.cond: // CHECK14: omp.dispatch.cond:
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK14-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK14-NEXT: ret void // CHECK14-NEXT: ret void
// //
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// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK14: omp.inner.for.body: // CHECK14: omp.inner.for.body:
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70 // CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70 // CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK14: omp.inner.for.inc: // CHECK14: omp.inner.for.inc:
// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70
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// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK14-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK14-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK14-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK14: omp.dispatch.cond: // CHECK14: omp.dispatch.cond:
// CHECK14-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK14-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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// CHECK15-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK15-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK15-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK15-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK15-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK15-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK15-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK15-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK15-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK15-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK15-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK15-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK15-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK15-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK15-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK15-NEXT: ret void // CHECK15-NEXT: ret void
// //
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// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK15: omp.precond.then: // CHECK15: omp.precond.then:
// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK15-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK15-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK15-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
// CHECK15-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK15-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK15: cond.true: // CHECK15: cond.true:
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// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK15-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK15-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
// CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK15: omp.inner.for.body: // CHECK15: omp.inner.for.body:
// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28
// CHECK15-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK15-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK15-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 // CHECK15-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK15-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK15-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK15-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !28 // CHECK15-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !28
// CHECK15-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28 // CHECK15-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !28 // CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !28
// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK15: omp.inner.for.inc: // CHECK15: omp.inner.for.inc:
// CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
// CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28 // CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28
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// CHECK15-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK15-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK15-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK15-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK15-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK15-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK15-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK15-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK15-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK15-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK15-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK15-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK15-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK15-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK15-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK15-NEXT: ret void // CHECK15-NEXT: ret void
// //
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// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK15-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK15-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
// CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK15: omp.inner.for.body: // CHECK15: omp.inner.for.body:
// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
// CHECK15-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK15-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK15-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK15-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK15-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK15-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK15-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4, !llvm.access.group !40 // CHECK15-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4, !llvm.access.group !40
// CHECK15-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40 // CHECK15-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]), !llvm.access.group !40 // CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]), !llvm.access.group !40
// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK15: omp.inner.for.inc: // CHECK15: omp.inner.for.inc:
// CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 // CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
// CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40
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// CHECK15-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK15-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK15-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK15-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK15-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK15-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK15-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK15-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK15-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK15-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) // CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 35, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]])
// CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK15: omp.dispatch.cond: // CHECK15: omp.dispatch.cond:
// CHECK15-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK15-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK15-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK15-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK15-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK15-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK15-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK15-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK15-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK15-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK15-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK15-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK15-NEXT: ret void // CHECK15-NEXT: ret void
// //
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// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK15: omp.inner.for.body: // CHECK15: omp.inner.for.body:
// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
// CHECK15-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK15-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK15-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK15-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK15-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK15-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58 // CHECK15-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK15-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58 // CHECK15-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58 // CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58
// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK15: omp.inner.for.inc: // CHECK15: omp.inner.for.inc:
// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58
// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58
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// CHECK15-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK15-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK15-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK15-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK15-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK15-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK15-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK15-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK15-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK15-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK15-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK15: omp.dispatch.cond: // CHECK15: omp.dispatch.cond:
// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK15-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK15-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK15-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK15-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK15-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK15-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK15-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK15-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK15-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK15-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK15-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK15-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK15-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK15-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK15-NEXT: ret void // CHECK15-NEXT: ret void
// //
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// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK15: omp.inner.for.body: // CHECK15: omp.inner.for.body:
// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70
// CHECK15-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK15-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK15-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK15-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK15-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK15-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70 // CHECK15-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK15-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70 // CHECK15-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70 // CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70
// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK15: omp.inner.for.inc: // CHECK15: omp.inner.for.inc:
// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70
// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70
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// CHECK15-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK15-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK15-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK15-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK15-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK15-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK15-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK15-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK15-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK15-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK15-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK15-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK15-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 35, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK15-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK15: omp.dispatch.cond: // CHECK15: omp.dispatch.cond:
// CHECK15-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK15-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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// CHECK16-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK16-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK16-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK16-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK16-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK16-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK16-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK16-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK16-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK16-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK16-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK16-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK16-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK16-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK16-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK16-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK16-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK16-NEXT: ret void // CHECK16-NEXT: ret void
// //
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// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK16-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK16: omp.precond.then: // CHECK16: omp.precond.then:
// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4 // CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK16-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK16-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
// CHECK16-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK16-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK16: cond.true: // CHECK16: cond.true:
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// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
// CHECK16-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK16-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
// CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK16: omp.inner.for.body: // CHECK16: omp.inner.for.body:
// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28 // CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28
// CHECK16-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 // CHECK16-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 // CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK16-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 // CHECK16-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28 // CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK16-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK16-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK16-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !28 // CHECK16-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !28
// CHECK16-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28 // CHECK16-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !28 // CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !28
// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK16: omp.inner.for.inc: // CHECK16: omp.inner.for.inc:
// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 // CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
// CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28 // CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28
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// CHECK16-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK16-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK16-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK16-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK16-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK16-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK16-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK16-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK16-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK16-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK16-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK16-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK16-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK16-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK16-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK16-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK16-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32* [[CONV1]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK16-NEXT: ret void // CHECK16-NEXT: ret void
// //
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// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK16-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK16-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
// CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK16: omp.inner.for.body: // CHECK16: omp.inner.for.body:
// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40 // CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
// CHECK16-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 // CHECK16-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 // CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK16-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 // CHECK16-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40 // CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK16-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK16-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK16-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4, !llvm.access.group !40 // CHECK16-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4, !llvm.access.group !40
// CHECK16-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40 // CHECK16-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]), !llvm.access.group !40 // CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP21]]), !llvm.access.group !40
// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK16: omp.inner.for.inc: // CHECK16: omp.inner.for.inc:
// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 // CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40 // CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40
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// CHECK16-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK16-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK16-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK16-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP7]] to i32
// CHECK16-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK16-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK16-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32 // CHECK16-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP8]] to i32
// CHECK16-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4 // CHECK16-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
// CHECK16-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK16-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK16-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 // CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]]) // CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], i32 1073741859, i32 [[TMP10]], i32 [[TMP11]], i32 1, i32 [[TMP9]])
// CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK16: omp.dispatch.cond: // CHECK16: omp.dispatch.cond:
// CHECK16-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK16-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK16-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK16-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK16-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK16-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK16-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK16-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK16-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK16-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK16-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK16-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK16-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK16-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK16-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK16-NEXT: ret void // CHECK16-NEXT: ret void
// //
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// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK16: omp.inner.for.body: // CHECK16: omp.inner.for.body:
// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
// CHECK16-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK16-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58 // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK16-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK16-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK16-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK16-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58 // CHECK16-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK16-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58 // CHECK16-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58 // CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..22 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !58
// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK16: omp.inner.for.inc: // CHECK16: omp.inner.for.inc:
// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 // CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58
// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58 // CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58
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// CHECK16-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK16-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK16-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK16-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK16-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK16-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK16-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK16-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK16-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK16-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK16-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK16-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]]) // CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
// CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK16: omp.dispatch.cond: // CHECK16: omp.dispatch.cond:
// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK16-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK16-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK16-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 // CHECK16-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
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// CHECK16-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK16-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
// CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK16-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK16-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK16-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 // CHECK16-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
// CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK16-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32* // CHECK16-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK16-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK16-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 // CHECK16-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK16-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK16-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]]) // CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*, i64)* @.omp_outlined..29 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]], i64 [[TMP3]])
// CHECK16-NEXT: ret void // CHECK16-NEXT: ret void
// //
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// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK16: omp.inner.for.body: // CHECK16: omp.inner.for.body:
// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !70
// CHECK16-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK16-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70 // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK16-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 // CHECK16-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK16-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK16-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70 // CHECK16-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK16-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70 // CHECK16-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70 // CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..30 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !70
// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK16: omp.inner.for.inc: // CHECK16: omp.inner.for.inc:
// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70 // CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !70
// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70 // CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !70
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// CHECK16-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK16-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK16-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK16-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK16-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK16-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK16-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 // CHECK16-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// CHECK16-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4 // CHECK16-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_LB]], align 4
// CHECK16-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
// CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]]) // CHECK16-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1073741859, i32 [[TMP4]], i32 [[TMP5]], i32 1, i32 [[TMP3]])
// CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK16-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK16: omp.dispatch.cond: // CHECK16: omp.dispatch.cond:
// CHECK16-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) // CHECK16-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
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clang/test/OpenMP/teams_distribute_simd_codegen.cpp

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// CHECK1-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 // CHECK1-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[I_ADDR]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], i32* [[CONV3]], [100 x i32]* [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], i32* [[CONV3]], [100 x i32]* [[TMP1]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
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// CHECK2-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: store [100 x i32]* [[A]], [100 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 // CHECK2-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[I_ADDR]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], i32* [[CONV3]], [100 x i32]* [[TMP1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], i32* [[CONV3]], [100 x i32]* [[TMP1]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
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// CHECK21: cond.false: // CHECK21: cond.false:
// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK21-NEXT: br label [[COND_END]] // CHECK21-NEXT: br label [[COND_END]]
// CHECK21: cond.end: // CHECK21: cond.end:
// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
// CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK21-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK21-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
// CHECK21-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK21-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK21: omp_if.then: // CHECK21: omp_if.then:
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK21: omp.inner.for.cond: // CHECK21: omp.inner.for.cond:
// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4
// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
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// CHECK22: cond.false: // CHECK22: cond.false:
// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK22-NEXT: br label [[COND_END]] // CHECK22-NEXT: br label [[COND_END]]
// CHECK22: cond.end: // CHECK22: cond.end:
// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] // CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK22-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK22-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
// CHECK22-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK22-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 // CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK22: omp_if.then: // CHECK22: omp_if.then:
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK22: omp.inner.for.cond: // CHECK22: omp.inner.for.cond:
// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 // CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4
// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
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// CHECK23: cond.false: // CHECK23: cond.false:
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK23-NEXT: br label [[COND_END]] // CHECK23-NEXT: br label [[COND_END]]
// CHECK23: cond.end: // CHECK23: cond.end:
// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
// CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK23-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK23-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
// CHECK23-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK23-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK23: omp_if.then: // CHECK23: omp_if.then:
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK23: omp.inner.for.cond: // CHECK23: omp.inner.for.cond:
// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5
// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
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// CHECK24: cond.false: // CHECK24: cond.false:
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK24-NEXT: br label [[COND_END]] // CHECK24-NEXT: br label [[COND_END]]
// CHECK24: cond.end: // CHECK24: cond.end:
// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] // CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK24-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK24-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
// CHECK24-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK24-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 // CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK24: omp_if.then: // CHECK24: omp_if.then:
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK24: omp.inner.for.cond: // CHECK24: omp.inner.for.cond:
// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5
// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
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// CHECK33-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK33-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK33-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK33-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK33-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK33-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK33-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK33-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK33-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK33-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK33-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK33-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) // CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK33-NEXT: ret void // CHECK33-NEXT: ret void
// //
// //
// CHECK33-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK33-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
// CHECK33-NEXT: entry: // CHECK33-NEXT: entry:
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// CHECK34-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK34-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK34-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK34-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK34-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK34-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK34-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK34-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK34-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK34-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK34-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK34-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK34-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK34-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) // CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK34-NEXT: ret void // CHECK34-NEXT: ret void
// //
// //
// CHECK34-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK34-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
// CHECK34-NEXT: entry: // CHECK34-NEXT: entry:
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// CHECK37-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 // CHECK37-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
// CHECK37-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK37-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK37-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK37-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK37-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK37-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK37-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK37-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK37-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK37-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK37-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK37-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK37-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK37-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK37-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK37-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK37-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK37-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK37-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK37-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK37-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK37-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK37-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK37-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK37-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 // CHECK37-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1
// CHECK37-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK37-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK37-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[TOBOOL2]] to i8 // CHECK37-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK37-NEXT: store i8 [[FROMBOOL4]], i8* [[CONV3]], align 1 // CHECK37-NEXT: store i8 [[FROMBOOL4]], i8* [[CONV3]], align 1
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// CHECK37: cond.false: // CHECK37: cond.false:
// CHECK37-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK37-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK37-NEXT: br label [[COND_END]] // CHECK37-NEXT: br label [[COND_END]]
// CHECK37: cond.end: // CHECK37: cond.end:
// CHECK37-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] // CHECK37-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
// CHECK37-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK37-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK37-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK37-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK37-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK37-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
// CHECK37-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK37-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK37-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK37-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK37-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK37-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK37: omp_if.then: // CHECK37: omp_if.then:
// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK37-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK37: omp.inner.for.cond: // CHECK37: omp.inner.for.cond:
// CHECK37-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK37-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK37-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 // CHECK37-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5
// CHECK37-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK37-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
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// CHECK37-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK37-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK37-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK37-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK37-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK37-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK37-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK37-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK37-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK37-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK37-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK37-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK37-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK37-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK37-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK37-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK37-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK37-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK37-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK37-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK37-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK37-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK37-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) // CHECK37-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK37-NEXT: ret void // CHECK37-NEXT: ret void
// //
// //
// CHECK37-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK37-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK37-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK37-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
// CHECK37-NEXT: entry: // CHECK37-NEXT: entry:
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// CHECK38-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 // CHECK38-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
// CHECK38-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK38-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK38-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK38-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK38-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK38-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK38-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* // CHECK38-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK38-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK38-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK38-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK38-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK38-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK38-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK38-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK38-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK38-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK38-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK38-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK38-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK38-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK38-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK38-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK38-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK38-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 // CHECK38-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1
// CHECK38-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK38-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK38-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[TOBOOL2]] to i8 // CHECK38-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK38-NEXT: store i8 [[FROMBOOL4]], i8* [[CONV3]], align 1 // CHECK38-NEXT: store i8 [[FROMBOOL4]], i8* [[CONV3]], align 1
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// CHECK38: cond.false: // CHECK38: cond.false:
// CHECK38-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK38-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK38-NEXT: br label [[COND_END]] // CHECK38-NEXT: br label [[COND_END]]
// CHECK38: cond.end: // CHECK38: cond.end:
// CHECK38-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] // CHECK38-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
// CHECK38-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK38-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK38-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK38-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK38-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK38-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
// CHECK38-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK38-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK38-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK38-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK38-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK38-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK38: omp_if.then: // CHECK38: omp_if.then:
// CHECK38-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK38-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK38: omp.inner.for.cond: // CHECK38: omp.inner.for.cond:
// CHECK38-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK38-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK38-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 // CHECK38-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5
// CHECK38-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK38-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
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// CHECK38-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK38-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
// CHECK38-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) // CHECK38-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
// CHECK38-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8 // CHECK38-NEXT: store i64 [[TE]], i64* [[TE_ADDR]], align 8
// CHECK38-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8 // CHECK38-NEXT: store i64 [[TH]], i64* [[TH_ADDR]], align 8
// CHECK38-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 // CHECK38-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK38-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32* // CHECK38-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK38-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32* // CHECK38-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK38-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8 // CHECK38-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK38-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK38-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK38-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK38-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK38-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) // CHECK38-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK38-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]]) // CHECK38-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK38-NEXT: ret void // CHECK38-NEXT: ret void
// //
// //
// CHECK38-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK38-LABEL: define {{[^@]+}}@.omp_outlined..1
// CHECK38-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK38-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
// CHECK38-NEXT: entry: // CHECK38-NEXT: entry:
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// CHECK39: cond.false: // CHECK39: cond.false:
// CHECK39-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK39-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK39-NEXT: br label [[COND_END]] // CHECK39-NEXT: br label [[COND_END]]
// CHECK39: cond.end: // CHECK39: cond.end:
// CHECK39-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] // CHECK39-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
// CHECK39-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK39-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK39-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK39-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK39-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK39-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
// CHECK39-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK39-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK39-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK39-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK39-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK39-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK39: omp_if.then: // CHECK39: omp_if.then:
// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK39-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK39: omp.inner.for.cond: // CHECK39: omp.inner.for.cond:
// CHECK39-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 // CHECK39-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
// CHECK39-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 // CHECK39-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
// CHECK39-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK39-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
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// CHECK40: cond.false: // CHECK40: cond.false:
// CHECK40-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK40-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK40-NEXT: br label [[COND_END]] // CHECK40-NEXT: br label [[COND_END]]
// CHECK40: cond.end: // CHECK40: cond.end:
// CHECK40-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] // CHECK40-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
// CHECK40-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 // CHECK40-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK40-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 // CHECK40-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK40-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK40-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
// CHECK40-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 4 // CHECK40-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK40-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK40-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK40-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK40-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK40: omp_if.then: // CHECK40: omp_if.then:
// CHECK40-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK40-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK40: omp.inner.for.cond: // CHECK40: omp.inner.for.cond:
// CHECK40-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 // CHECK40-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
// CHECK40-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 // CHECK40-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
// CHECK40-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK40-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
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clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp

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// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
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// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK9: omp.precond.then: // CHECK9: omp.precond.then:
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK9: omp.dispatch.cond: // CHECK9: omp.dispatch.cond:
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
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// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
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// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK10: omp.precond.then: // CHECK10: omp.precond.then:
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]]) // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK10: omp.dispatch.cond: // CHECK10: omp.dispatch.cond:
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] // CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
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clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp

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// CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]]
// CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8*
// CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* // CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8, !llvm.access.group !5 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue: // CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc: // CHECK1: omp.inner.for.inc:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1
// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
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// CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK1: omp.inner.for.cond.cleanup: // CHECK1: omp.inner.for.cond.cleanup:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body: // CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 // CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11 // CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]]
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// CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 // CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]]
// CHECK2-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK2-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8*
// CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* // CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8, !llvm.access.group !5 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue: // CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc: // CHECK2: omp.inner.for.inc:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1
// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
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// CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
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// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// CHECK2: omp.inner.for.cond.cleanup: // CHECK2: omp.inner.for.cond.cleanup:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body: // CHECK2: omp.inner.for.body:
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 // CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11 // CHECK2-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]]
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// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK9: omp.inner.for.body: // CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !4 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4
// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !4 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4
// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4
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// CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 // CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK10: omp.inner.for.body: // CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !4 // CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4
// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !4 // CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4
// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4
// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4
// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4
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clang/test/OpenMP/teams_firstprivate_codegen.cpp

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// CHECK1-NEXT: [[G1:%.*]] = alloca i32, align 128 // CHECK1-NEXT: [[G1:%.*]] = alloca i32, align 128
// CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G1]], i64 [[TMP3]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G1]], i64 [[TMP3]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
// CHECK1-NEXT: store i32 1, i32* [[G1]], align 128 // CHECK1-NEXT: store i32 1, i32* [[G1]], align 128
// CHECK1-NEXT: store i32 2, i32* [[CONV]], align 8 // CHECK1-NEXT: store i32 2, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK1-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8 // CHECK1-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK1-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8 // CHECK1-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8
// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
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// CHECK2-NEXT: [[G1:%.*]] = alloca i32, align 128 // CHECK2-NEXT: [[G1:%.*]] = alloca i32, align 128
// CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G1]], i64 [[TMP3]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G1]], i64 [[TMP3]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
// CHECK2-NEXT: store i32 1, i32* [[G1]], align 128 // CHECK2-NEXT: store i32 1, i32* [[G1]], align 128
// CHECK2-NEXT: store i32 2, i32* [[CONV]], align 8 // CHECK2-NEXT: store i32 2, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK2-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8 // CHECK2-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
// CHECK2-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8 // CHECK2-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8
// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
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// CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
// CHECK9: omp.arraycpy.done4: // CHECK9: omp.arraycpy.done4:
// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
// CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0
// CHECK9-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0
// CHECK9-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* // CHECK9-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
// CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* // CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false)
// CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 8 // CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 4
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2
// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK9: arraydestroy.body: // CHECK9: arraydestroy.body:
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
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// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116
// CHECK9-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] { // CHECK9-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK9-NEXT: ret void // CHECK9-NEXT: ret void
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
// CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
// CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
// CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
// CHECK10: omp.arraycpy.done4: // CHECK10: omp.arraycpy.done4:
// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
// CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) // CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] // CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0
// CHECK10-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0
// CHECK10-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* // CHECK10-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
// CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* // CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false)
// CHECK10-NEXT: store i32 2, i32* [[CONV1]], align 8 // CHECK10-NEXT: store i32 2, i32* [[CONV1]], align 4
// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
// CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2
// CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK10: arraydestroy.body: // CHECK10: arraydestroy.body:
// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
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// //
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116
// CHECK10-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] { // CHECK10-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] {
// CHECK10-NEXT: entry: // CHECK10-NEXT: entry:
// CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
// CHECK10-NEXT: ret void // CHECK10-NEXT: ret void
// //
// //
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
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clang/test/utils/update_cc_test_checks/Inputs/generated-funcs-regex.c.expected

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// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// //
// CHECK-LABEL: @{{__omp_offloading_[a-z0-9]+_[a-z0-9]+_foo_l[0-9]+}}( // CHECK-LABEL: @{{__omp_offloading_[a-z0-9]+_[a-z0-9]+_foo_l[0-9]+}}(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 // CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK-NEXT: call void @use(i32 [[TMP0]]) // CHECK-NEXT: call void @use(i32 [[TMP0]])
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //