[X86][AMX] Don't emit tilerelease for old AMX instrisic.

[LuoYuanke]

Summary

We should avoid mixing old AMX instrinsic with new AMX intrinsic. For
old AMX intrinsic, user is responsible for invoking tile release. This
patch is to check if there is any tile config generated by compiler. If
so it emit tilerelease instruction, otherwise it don't emit the
instruction.

[pengfei]

LGTM.

llvm/lib/Target/X86/X86MachineFunctionInfo.h

215

This can be void, i.e.,
void setHasVirtualTileReg() { HasVirtualTileReg = true; }

[LuoYuanke]

llvm/lib/Target/X86/X86MachineFunctionInfo.h

215

True for current patch. Not sure we may set it to false someday.

[xiangzhangllvm]

llvm/lib/Target/X86/X86FastTileConfig.cpp

293–294

Another way to escape add a variable in X86MachineFunctionInfo is

if (Changed)
  add tilerelease at MF.end()

[LuoYuanke]

llvm/lib/Target/X86/X86FastTileConfig.cpp

293–294

There may be multi exit, so insert tilerelease to end block is not enough.

[xiangzhangllvm]

llvm/lib/Target/X86/X86FastTileConfig.cpp

293–294

Make sense, here not merge the multi exits to one exit yet.

llvm/lib/Target/X86/X86FastTileConfig.cpp

 
 class X86FastTileConfig : public MachineFunctionPass {
   // context
   MachineFunction *MF = nullptr;
   const X86Subtarget *ST = nullptr;
   const TargetRegisterInfo *TRI = nullptr;
   const TargetInstrInfo *TII = nullptr;
   MachineRegisterInfo *MRI = nullptr;
+  X86MachineFunctionInfo *X86FI = nullptr;
 
   MachineInstr *getTileConfigPoint();
   void tileConfig();
 
 public:
   X86FastTileConfig() : MachineFunctionPass(ID) {}
 
   bool fastTileConfig();
for (MachineBasicBlock &MBB : *MF) {
     for (MachineInstr &MI : MBB)
       if (MI.getOpcode() == X86::PLDTILECFGV)
         CFGs.push_back(&MI);
     for (auto *MI : CFGs)
       materializeTileCfg(MI);
     if (!CFGs.empty())
       Changed = true;
   }
+  if (Changed)
+    X86FI->setHasVirtualTileReg(true);
   return Changed;
 }
 
 bool X86FastTileConfig::runOnMachineFunction(MachineFunction &MFunc) {
   MF = &MFunc;
   MRI = &MFunc.getRegInfo();
   ST = &MFunc.getSubtarget<X86Subtarget>();
   TRI = ST->getRegisterInfo();
   TII = MFunc.getSubtarget().getInstrInfo();
+  X86FI = MFunc.getInfo<X86MachineFunctionInfo>();
 
   return fastTileConfig();
 }
 
 FunctionPass *llvm::createX86FastTileConfigPass() {
   return new X86FastTileConfig();
 }

llvm/lib/Target/X86/X86FrameLowering.cpp

if (Terminator == MBB.end() || !isTailCallOpcode(Terminator->getOpcode())) {
     if (Offset) {
       // Check for possible merge with preceding ADD instruction.
       Offset += mergeSPUpdates(MBB, Terminator, true);
       emitSPUpdate(MBB, Terminator, DL, Offset, /*InEpilogue=*/true);
     }
   }
 
   // Emit tilerelease for AMX kernel.
-  const MachineRegisterInfo &MRI = MF.getRegInfo();
-  const TargetRegisterClass *RC = TRI->getRegClass(X86::TILERegClassID);
-  for (unsigned I = 0; I < RC->getNumRegs(); I++)
-    if (!MRI.reg_nodbg_empty(X86::TMM0 + I)) {
-      BuildMI(MBB, Terminator, DL, TII.get(X86::TILERELEASE));
-      break;
-    }
+  if (X86FI->hasVirtualTileReg())
 }
 
 StackOffset X86FrameLowering::getFrameIndexReference(const MachineFunction &MF,
                                                      int FI,
                                                      Register &FrameReg) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
 
   bool IsFixed = MFI.isFixedObjectIndex(FI);

llvm/lib/Target/X86/X86MachineFunctionInfo.h

class X86MachineFunctionInfo : public MachineFunctionInfo {
   /// True if this function has any preallocated calls.
   bool HasPreallocatedCall = false;
 
   /// Whether this function has an extended frame record [Ctx, RBP, Return
   /// addr]. If so, bit 60 of the in-memory frame pointer will be 1 to enable
   /// other tools to detect the extended record.
   bool HasSwiftAsyncContext = false;
 
+  /// True if this function has tile virtual register. This is used to
+  /// determine if we should insert tilerelease in frame lowering.
+  bool HasVirtualTileReg = false;
+
   Optional<int> SwiftAsyncContextFrameIdx;
 
   ValueMap<const Value *, size_t> PreallocatedIds;
   SmallVector<size_t, 0> PreallocatedStackSizes;
   SmallVector<SmallVector<size_t, 4>, 0> PreallocatedArgOffsets;
 
 private:
   /// ForwardedMustTailRegParms - A list of virtual and physical registers
public:
   void setHasDynAlloca(bool v) { HasDynAlloca = v; }
 
   bool hasPreallocatedCall() const { return HasPreallocatedCall; }
   void setHasPreallocatedCall(bool v) { HasPreallocatedCall = v; }
 
   bool hasSwiftAsyncContext() const { return HasSwiftAsyncContext; }
   void setHasSwiftAsyncContext(bool v) { HasSwiftAsyncContext = v; }
 
+  bool hasVirtualTileReg() const { return HasVirtualTileReg; }
+  void setHasVirtualTileReg(bool v) { HasVirtualTileReg = v; }
+
   Optional<int> getSwiftAsyncContextFrameIdx() const {
     return SwiftAsyncContextFrameIdx;
   }
   void setSwiftAsyncContextFrameIdx(int v) { SwiftAsyncContextFrameIdx = v; }
 
   size_t getPreallocatedIdForCallSite(const Value *CS) {
     auto Insert = PreallocatedIds.insert({CS, PreallocatedIds.size()});
     if (Insert.second) {

llvm/lib/Target/X86/X86PreTileConfig.cpp

 ///
 /// This pass calculates all points that ldtilecfg need to be inserted to and
 /// insert them. It reports error if the reachability conditions aren't met.
 //
 //===----------------------------------------------------------------------===//
 
 #include "X86.h"
 #include "X86InstrBuilder.h"
+#include "X86MachineFunctionInfo.h"
 #include "X86RegisterInfo.h"
 #include "X86Subtarget.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
void X86PreTileConfig::collectShapeInfo(MachineInstr &MI) {
   }
 }
 
 bool X86PreTileConfig::runOnMachineFunction(MachineFunction &MF) {
   const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
   const TargetInstrInfo *TII = ST.getInstrInfo();
   const TargetRegisterInfo *TRI = ST.getRegisterInfo();
   const TargetRegisterClass *RC = TRI->getRegClass(X86::TILERegClassID);
+  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
 
   BitVector AMXRegs(TRI->getNumRegs());
   for (unsigned I = 0; I < RC->getNumRegs(); I++)
     AMXRegs.set(X86::TMM0 + I);
 
   // Iterate MF to collect information.
   MRI = &MF.getRegInfo();
   MLI = &getAnalysis<MachineLoopInfo>();
for (auto *Pred : MBB->predecessors()) {
           CfgLiveInBBs.push_back(Pred);
       }
     }
   }
 
   // There's no AMX instruction if we didn't find a tile config live in point.
   if (CfgNeedInsert.empty())
     return false;
+  X86FI->setHasVirtualTileReg(true);
 
   // Avoid to insert ldtilecfg before any shape defs.
   SmallVector<MachineBasicBlock *, 8> WorkList;
   for (auto &I : ShapeBBs) {
     // TODO: We can hoist shapes across BBs here.
     if (BBVisitedInfo[I.first].HasAMXRegLiveIn)
       REPORT_CONFIG_FAIL
     if (BBVisitedInfo[I.first].FirstAMX &&

llvm/test/CodeGen/X86/AMX/amx-bf16-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile -mattr=+amx-bf16 -verify-machineinstrs | FileCheck %s
 
 define void @test_amx() {
 ; CHECK-LABEL: test_amx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    tdpbf16ps %tmm7, %tmm4, %tmm3
-; CHECK-NEXT:    tilerelease
 ; CHECK-NEXT:    retq
   call void @llvm.x86.tdpbf16ps(i8 3, i8 4, i8 7)
   ret void
 }
 
 declare void @llvm.x86.tdpbf16ps(i8 %tile0, i8 %tile1, i8 %tile2)

llvm/test/CodeGen/X86/AMX/amx-int8-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -verify-machineinstrs | FileCheck %s
 
 define void @test_amx() {
 ; CHECK-LABEL: test_amx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    tdpbssd %tmm7, %tmm4, %tmm3
 ; CHECK-NEXT:    tdpbsud %tmm7, %tmm4, %tmm3
 ; CHECK-NEXT:    tdpbusd %tmm7, %tmm0, %tmm3
 ; CHECK-NEXT:    tdpbuud %tmm1, %tmm4, %tmm3
-; CHECK-NEXT:    tilerelease
 ; CHECK-NEXT:    retq
   call void @llvm.x86.tdpbssd(i8 3, i8 4, i8 7)
 
   call void @llvm.x86.tdpbsud(i8 3, i8 4, i8 7)
 
   call void @llvm.x86.tdpbusd(i8 3, i8 0, i8 7)
 
   call void @llvm.x86.tdpbuud(i8 3, i8 4, i8 1)
   ret void
 }
 
 declare void @llvm.x86.tdpbssd(i8 %tile0, i8 %tile1, i8 %tile2)
 declare void @llvm.x86.tdpbsud(i8 %tile0, i8 %tile1, i8 %tile2)
 declare void @llvm.x86.tdpbusd(i8 %tile0, i8 %tile1, i8 %tile2)
 declare void @llvm.x86.tdpbuud(i8 %tile0, i8 %tile1, i8 %tile2)

llvm/test/CodeGen/X86/AMX/amx-tile-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile -verify-machineinstrs | FileCheck %s
 
 define void @test_amx(i8* %pointer, i8* %base, i64 %stride) {
 ; CHECK-LABEL: test_amx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ldtilecfg (%rdi)
 ; CHECK-NEXT:    sttilecfg (%rdi)
 ; CHECK-NEXT:    tilerelease
 ; CHECK-NEXT:    tilezero %tmm3
 ; CHECK-NEXT:    tileloadd (%rsi,%rdx), %tmm3
 ; CHECK-NEXT:    tileloaddt1 (%rsi,%rdx), %tmm3
 ; CHECK-NEXT:    tilestored %tmm3, (%rsi,%rdx)
-; CHECK-NEXT:    tilerelease
 ; CHECK-NEXT:    retq
   call void @llvm.x86.ldtilecfg(i8* %pointer)
 
   call void @llvm.x86.sttilecfg(i8* %pointer)
 
   call void @llvm.x86.tilerelease()
 
   call void @llvm.x86.tilezero(i8 3)