[PowerPC] use lvx + splat directly for aligned splat load

[shchenz]

Summary

This is to address review comments for https://reviews.llvm.org/D106555#inline-1079417

We can use lvx + splat 0(or biggest index on LE) directly for some aligned splat load instead of lvx + splat with a constructed mask.

[shchenz]

for power 9, use lxsibzx as it has the same latency with lvx but has more useable registers.

[shchenz]

gentle ping

[shchenz]

gentle ping

[nemanjai]

LGTM.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4473

Nit: can probably be added to line 4471 (except of course change the body to
AddrOp = N->getOperand(1)

[shchenz]

Thanks for your review @nemanjai

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4473

Will fix this in the commit.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

bool PPCDAGToDAGISel::trySETCC(SDNode *N) {
   return true;
 }
 
 /// Does this node represent a load/store node whose address can be represented
 /// with a register plus an immediate that's a multiple of \p Val:
 bool PPCDAGToDAGISel::isOffsetMultipleOf(SDNode *N, unsigned Val) const {
   LoadSDNode *LDN = dyn_cast<LoadSDNode>(N);
   StoreSDNode *STN = dyn_cast<StoreSDNode>(N);
+  MemIntrinsicSDNode *MIN = dyn_cast<MemIntrinsicSDNode>(N);
   SDValue AddrOp;
-  if (LDN)
-    AddrOp = LDN->getOperand(1);
+  if (LDN || (MIN && MIN->getOpcode() == PPCISD::LD_SPLAT))
+    AddrOp = N->getOperand(1);
   else if (STN)
     AddrOp = STN->getOperand(2);
 
   // If the address points a frame object or a frame object with an offset,
   // we need to check the object alignment.
   short Imm = 0;
   if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(
           AddrOp.getOpcode() == ISD::ADD ? AddrOp.getOperand(0) :
                                            AddrOp)) {
     // If op0 is a frame index that is under aligned, we can't do it either,
     // because it is translated to r31 or r1 + slot + offset. We won't know the
case PPCISD::LD_SPLAT: {
     // direct move, we should be able to get the best selection in the .td file.
     if (!Subtarget->hasAltivec() || Subtarget->hasDirectMove())
       break;
 
     EVT Type = N->getValueType(0);
     if (Type != MVT::v16i8 && Type != MVT::v8i16)
       break;
 
+    // If the alignment for the load is 16 or bigger, we don't need the
+    // permutated mask to get the required value. The value must be the 0
+    // element in big endian target or 7/15 in little endian target in the
+    // result vsx register of lvx instruction.
+    // Select the instruction in the .td file.
+    if (cast<MemIntrinsicSDNode>(N)->getAlign() >= Align(16) &&
+        isOffsetMultipleOf(N, 16))
+      break;
+
     SDValue ZeroReg =
         CurDAG->getRegister(Subtarget->isPPC64() ? PPC::ZERO8 : PPC::ZERO,
                             Subtarget->isPPC64() ? MVT::i64 : MVT::i32);
     unsigned LIOpcode = Subtarget->isPPC64() ? PPC::LI8 : PPC::LI;
     // v16i8 LD_SPLAT addr
     // ======>
     // Mask = LVSR/LVSL 0, addr
     // LoadLow = LVX 0, addr

llvm/lib/Target/PowerPC/PPCInstrVSX.td

 def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">;
 def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">;
 def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">;
 def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">;
 def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">;
 def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">;
 def NoP10Vector: Predicate<"!Subtarget->hasP10Vector()">;
 
+def PPCldsplatAlign16 : PatFrag<(ops node:$ptr), (PPCldsplat node:$ptr), [{
+  return cast<MemIntrinsicSDNode>(N)->getAlign() >= Align(16) &&
+         isOffsetMultipleOf(N, 16);
+}]>;
+
 //--------------------- VSX-specific instruction formats ---------------------//
 // By default, all VSX instructions are to be selected over their Altivec
 // counter parts and they do not have unmodeled sideeffects.
 let AddedComplexity = 400, hasSideEffects = 0 in {
 multiclass XX3Form_Rcr<bits<6> opcode, bits<7> xo, string asmbase,
                     string asmstr, InstrItinClass itin, Intrinsic Int,
                     ValueType OutTy, ValueType InTy> {
   let BaseName = asmbase in {

 defm : ScalToVecWPermute<
   v2i64, (i64 (load ForceXForm:$src)),
   (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2),
   (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v2f64, (f64 (load ForceXForm:$src)),
   (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2),
   (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>;
+
+// Splat loads.
+def : Pat<(v8i16 (PPCldsplatAlign16 ForceXForm:$A)),
+          (v8i16 (VSPLTH 7, (LVX ForceXForm:$A)))>;
+def : Pat<(v16i8 (PPCldsplatAlign16 ForceXForm:$A)),
+          (v16i8 (VSPLTB 15, (LVX ForceXForm:$A)))>;
 } // HasVSX, NoP9Vector, IsLittleEndian
 
 let Predicates = [HasVSX, NoP9Vector, IsBigEndian] in {
   def : Pat<(v2f64 (int_ppc_vsx_lxvd2x ForceXForm:$src)),
             (LXVD2X ForceXForm:$src)>;
   def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, ForceXForm:$dst),
             (STXVD2X $rS, ForceXForm:$dst)>;
+
+  // Splat loads.
+  def : Pat<(v8i16 (PPCldsplatAlign16 ForceXForm:$A)),
+            (v8i16 (VSPLTH 0, (LVX ForceXForm:$A)))>;
+  def : Pat<(v16i8 (PPCldsplatAlign16 ForceXForm:$A)),
+            (v16i8 (VSPLTB 0, (LVX ForceXForm:$A)))>;
 } // HasVSX, NoP9Vector, IsBigEndian
 
 // Any VSX subtarget that only has loads and stores that load in big endian
 // order regardless of endianness. This is really pre-Power9 subtargets.
 let Predicates = [HasVSX, HasOnlySwappingMemOps] in {
   def : Pat<(v2f64 (PPClxvd2x ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;
 
   // Stores.

llvm/test/CodeGen/PowerPC/load-and-splat.ll

 ; P9-LABEL: test_aligned_v8i16_1:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    lxsihzx v2, 0, r3
 ; P9-NEXT:    vsplth v2, v2, 3
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: test_aligned_v8i16_1:
 ; P8:       # %bb.0: # %entry
-; P8-NEXT:    lhzx r3, 0, r3
-; P8-NEXT:    mtvsrwz v2, r3
-; P8-NEXT:    vsplth v2, v2, 3
+; P8-NEXT:    lvx v2, 0, r3
+; P8-NEXT:    vsplth v2, v2, 7
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test_aligned_v8i16_1:
 ; P7:       # %bb.0: # %entry
-; P7-NEXT:    li r4, 1
 ; P7-NEXT:    lvx v2, 0, r3
-; P7-NEXT:    lvsl v4, 0, r3
-; P7-NEXT:    lvx v3, r4, r3
-; P7-NEXT:    vperm v2, v2, v3, v4
 ; P7-NEXT:    vsplth v2, v2, 0
 ; P7-NEXT:    blr
 ;
 ; P9-AIX32-LABEL: test_aligned_v8i16_1:
 ; P9-AIX32:       # %bb.0: # %entry
 ; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
 ; P9-AIX32-NEXT:    vsplth v2, v2, 3
 ; P9-AIX32-NEXT:    blr
 ;
 ; P8-AIX32-LABEL: test_aligned_v8i16_1:
 ; P8-AIX32:       # %bb.0: # %entry
-; P8-AIX32-NEXT:    lhzx r3, 0, r3
-; P8-AIX32-NEXT:    mtvsrwz v2, r3
-; P8-AIX32-NEXT:    vsplth v2, v2, 3
+; P8-AIX32-NEXT:    lvx v2, 0, r3
+; P8-AIX32-NEXT:    vsplth v2, v2, 0
 ; P8-AIX32-NEXT:    blr
 ;
 ; P7-AIX32-LABEL: test_aligned_v8i16_1:
 ; P7-AIX32:       # %bb.0: # %entry
-; P7-AIX32-NEXT:    li r4, 1
 ; P7-AIX32-NEXT:    lvx v2, 0, r3
-; P7-AIX32-NEXT:    lvsl v4, 0, r3
-; P7-AIX32-NEXT:    lvx v3, r4, r3
-; P7-AIX32-NEXT:    vperm v2, v2, v3, v4
 ; P7-AIX32-NEXT:    vsplth v2, v2, 0
 ; P7-AIX32-NEXT:    blr
 entry:
   %0 = load i16, i16* %Ptr, align 16
   %splat.splatinsert = insertelement <8 x i16> poison, i16 %0, i32 0
   %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
   ret <8 x i16> %splat.splat
 }
 
 define <8 x i16> @test_aligned_v8i16_2(i16* %Ptr) {
 ; P9-LABEL: test_aligned_v8i16_2:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    addi r3, r3, 32
 ; P9-NEXT:    lxsihzx v2, 0, r3
 ; P9-NEXT:    vsplth v2, v2, 3
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: test_aligned_v8i16_2:
 ; P8:       # %bb.0: # %entry
-; P8-NEXT:    lhz r3, 32(r3)
-; P8-NEXT:    mtvsrwz v2, r3
-; P8-NEXT:    vsplth v2, v2, 3
+; P8-NEXT:    addi r3, r3, 32
+; P8-NEXT:    lvx v2, 0, r3
+; P8-NEXT:    vsplth v2, v2, 7
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test_aligned_v8i16_2:
 ; P7:       # %bb.0: # %entry
-; P7-NEXT:    li r4, 1
 ; P7-NEXT:    addi r3, r3, 32
 ; P7-NEXT:    lvx v2, 0, r3
-; P7-NEXT:    lvx v3, r4, r3
-; P7-NEXT:    lvsl v4, 0, r3
-; P7-NEXT:    vperm v2, v2, v3, v4
 ; P7-NEXT:    vsplth v2, v2, 0
 ; P7-NEXT:    blr
 ;
 ; P9-AIX32-LABEL: test_aligned_v8i16_2:
 ; P9-AIX32:       # %bb.0: # %entry
 ; P9-AIX32-NEXT:    addi r3, r3, 32
 ; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
 ; P9-AIX32-NEXT:    vsplth v2, v2, 3
 ; P9-AIX32-NEXT:    blr
 ;
 ; P8-AIX32-LABEL: test_aligned_v8i16_2:
 ; P8-AIX32:       # %bb.0: # %entry
-; P8-AIX32-NEXT:    lhz r3, 32(r3)
-; P8-AIX32-NEXT:    mtvsrwz v2, r3
-; P8-AIX32-NEXT:    vsplth v2, v2, 3
+; P8-AIX32-NEXT:    addi r3, r3, 32
+; P8-AIX32-NEXT:    lvx v2, 0, r3
+; P8-AIX32-NEXT:    vsplth v2, v2, 0
 ; P8-AIX32-NEXT:    blr
 ;
 ; P7-AIX32-LABEL: test_aligned_v8i16_2:
 ; P7-AIX32:       # %bb.0: # %entry
-; P7-AIX32-NEXT:    li r4, 1
 ; P7-AIX32-NEXT:    addi r3, r3, 32
 ; P7-AIX32-NEXT:    lvx v2, 0, r3
-; P7-AIX32-NEXT:    lvx v3, r4, r3
-; P7-AIX32-NEXT:    lvsl v4, 0, r3
-; P7-AIX32-NEXT:    vperm v2, v2, v3, v4
 ; P7-AIX32-NEXT:    vsplth v2, v2, 0
 ; P7-AIX32-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i16, i16* %Ptr, i64 16
   %0 = load i16, i16* %add.ptr, align 16
   %splat.splatinsert = insertelement <8 x i16> poison, i16 %0, i32 0
   %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
   ret <8 x i16> %splat.splat
 }
 
 define <16 x i8> @test_aligned_v16i8_1(i8* %Ptr) {
 ; P9-LABEL: test_aligned_v16i8_1:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    lxsibzx v2, 0, r3
 ; P9-NEXT:    vspltb v2, v2, 7
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: test_aligned_v16i8_1:
 ; P8:       # %bb.0: # %entry
-; P8-NEXT:    lbzx r3, 0, r3
-; P8-NEXT:    mtvsrwz v2, r3
-; P8-NEXT:    vspltb v2, v2, 7
+; P8-NEXT:    lvx v2, 0, r3
+; P8-NEXT:    vspltb v2, v2, 15
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test_aligned_v16i8_1:
 ; P7:       # %bb.0: # %entry
-; P7-NEXT:    lvsl v2, 0, r3
-; P7-NEXT:    lvx v3, 0, r3
-; P7-NEXT:    vperm v2, v3, v3, v2
+; P7-NEXT:    lvx v2, 0, r3
 ; P7-NEXT:    vspltb v2, v2, 0
 ; P7-NEXT:    blr
 ;
 ; P9-AIX32-LABEL: test_aligned_v16i8_1:
 ; P9-AIX32:       # %bb.0: # %entry
 ; P9-AIX32-NEXT:    lxsibzx v2, 0, r3
 ; P9-AIX32-NEXT:    vspltb v2, v2, 7
 ; P9-AIX32-NEXT:    blr
 ;
 ; P8-AIX32-LABEL: test_aligned_v16i8_1:
 ; P8-AIX32:       # %bb.0: # %entry
-; P8-AIX32-NEXT:    lbzx r3, 0, r3
-; P8-AIX32-NEXT:    mtvsrwz v2, r3
-; P8-AIX32-NEXT:    vspltb v2, v2, 7
+; P8-AIX32-NEXT:    lvx v2, 0, r3
+; P8-AIX32-NEXT:    vspltb v2, v2, 0
 ; P8-AIX32-NEXT:    blr
 ;
 ; P7-AIX32-LABEL: test_aligned_v16i8_1:
 ; P7-AIX32:       # %bb.0: # %entry
-; P7-AIX32-NEXT:    lvsl v2, 0, r3
-; P7-AIX32-NEXT:    lvx v3, 0, r3
-; P7-AIX32-NEXT:    vperm v2, v3, v3, v2
+; P7-AIX32-NEXT:    lvx v2, 0, r3
 ; P7-AIX32-NEXT:    vspltb v2, v2, 0
 ; P7-AIX32-NEXT:    blr
 entry:
   %0 = load i8, i8* %Ptr, align 16
   %splat.splatinsert = insertelement <16 x i8> poison, i8 %0, i32 0
   %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
   ret <16 x i8> %splat.splat
 }
 
 define <16 x i8> @test_aligned_v16i8_2(i8* %Ptr) {
 ; P9-LABEL: test_aligned_v16i8_2:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    addi r3, r3, 16
 ; P9-NEXT:    lxsibzx v2, 0, r3
 ; P9-NEXT:    vspltb v2, v2, 7
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: test_aligned_v16i8_2:
 ; P8:       # %bb.0: # %entry
-; P8-NEXT:    lbz r3, 16(r3)
-; P8-NEXT:    mtvsrwz v2, r3
-; P8-NEXT:    vspltb v2, v2, 7
+; P8-NEXT:    addi r3, r3, 16
+; P8-NEXT:    lvx v2, 0, r3
+; P8-NEXT:    vspltb v2, v2, 15
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test_aligned_v16i8_2:
 ; P7:       # %bb.0: # %entry
 ; P7-NEXT:    addi r3, r3, 16
-; P7-NEXT:    lvsl v2, 0, r3
-; P7-NEXT:    lvx v3, 0, r3
-; P7-NEXT:    vperm v2, v3, v3, v2
+; P7-NEXT:    lvx v2, 0, r3
 ; P7-NEXT:    vspltb v2, v2, 0
 ; P7-NEXT:    blr
 ;
 ; P9-AIX32-LABEL: test_aligned_v16i8_2:
 ; P9-AIX32:       # %bb.0: # %entry
 ; P9-AIX32-NEXT:    addi r3, r3, 16
 ; P9-AIX32-NEXT:    lxsibzx v2, 0, r3
 ; P9-AIX32-NEXT:    vspltb v2, v2, 7
 ; P9-AIX32-NEXT:    blr
 ;
 ; P8-AIX32-LABEL: test_aligned_v16i8_2:
 ; P8-AIX32:       # %bb.0: # %entry
-; P8-AIX32-NEXT:    lbz r3, 16(r3)
-; P8-AIX32-NEXT:    mtvsrwz v2, r3
-; P8-AIX32-NEXT:    vspltb v2, v2, 7
+; P8-AIX32-NEXT:    addi r3, r3, 16
+; P8-AIX32-NEXT:    lvx v2, 0, r3
+; P8-AIX32-NEXT:    vspltb v2, v2, 0
 ; P8-AIX32-NEXT:    blr
 ;
 ; P7-AIX32-LABEL: test_aligned_v16i8_2:
 ; P7-AIX32:       # %bb.0: # %entry
 ; P7-AIX32-NEXT:    addi r3, r3, 16
-; P7-AIX32-NEXT:    lvsl v2, 0, r3
-; P7-AIX32-NEXT:    lvx v3, 0, r3
-; P7-AIX32-NEXT:    vperm v2, v3, v3, v2
+; P7-AIX32-NEXT:    lvx v2, 0, r3
 ; P7-AIX32-NEXT:    vspltb v2, v2, 0
 ; P7-AIX32-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %Ptr, i64 16
   %0 = load i8, i8* %add.ptr, align 16
   %splat.splatinsert = insertelement <16 x i8> poison, i8 %0, i32 0
   %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
   ret <16 x i8> %splat.splat
 }