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[AArch64] Change EON pattern to match more often.
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Authored by gberry on Jul 20 2015, 9:57 AM.

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Reviewers

t.p.northover
jmolloy

Summary

Change EON pattern to match pattern after DAG reassociation.

Fixes bug PR22751 (https://llvm.org/bugs/show_bug.cgi?id=22751).

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gberry updated this revision to Diff 30167.Jul 20 2015, 9:57 AM

gberry retitled this revision from to [AArch64] Change EON pattern to match more often..

gberry updated this object.

gberry added reviewers: jmolloy, t.p.northover.

gberry added subscribers: llvm-commits, mcrosier.

Herald added subscribers: rengolin, aemerson. · View Herald TranscriptJul 20 2015, 9:57 AM

The code change seems reasonable -- DAGCombine seems to canonicalise even simple examples to this form. But the tests are a little shaky:

test/CodeGen/AArch64/eon.ll
5	This is almost certainly too weak. It'll grab the f from ".file", and even if it didn't do that it often matches the ".size complex_function_name, .Lcomplex_function_name_end0 - complex_function_name". I usually find "CHECK-LABEL: f:" works better, colons are far less common in assembly.

Fix test CHECK-LABELs to be more discriminating.

LGTM. Thanks!

Tim.

This revision is now accepted and ready to land.Jul 20 2015, 11:31 AM

Committed revision 242694.

Revision Contents

Path

Size

lib/

Target/

AArch64/

AArch64InstrInfo.td

2 lines

test/

CodeGen/

AArch64/

eon.ll

30 lines

Diff 30167

lib/Target/AArch64/AArch64InstrInfo.td

This file is larger than 256 KB, so syntax highlighting is disabled by default.

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	// (register)			// (register)
	defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;			defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
	defm BICS : LogicalRegS<0b11, 1, "bics",			defm BICS : LogicalRegS<0b11, 1, "bics",
	BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;			BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
	defm AND : LogicalReg<0b00, 0, "and", and>;			defm AND : LogicalReg<0b00, 0, "and", and>;
	defm BIC : LogicalReg<0b00, 1, "bic",			defm BIC : LogicalReg<0b00, 1, "bic",
	BinOpFrag<(and node:$LHS, (not node:$RHS))>>;			BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
	defm EON : LogicalReg<0b10, 1, "eon",			defm EON : LogicalReg<0b10, 1, "eon",
	BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;			BinOpFrag<(not (xor node:$LHS, node:$RHS))>>;
	defm EOR : LogicalReg<0b10, 0, "eor", xor>;			defm EOR : LogicalReg<0b10, 0, "eor", xor>;
	defm ORN : LogicalReg<0b01, 1, "orn",			defm ORN : LogicalReg<0b01, 1, "orn",
	BinOpFrag<(or node:$LHS, (not node:$RHS))>>;			BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
	defm ORR : LogicalReg<0b01, 0, "orr", or>;			defm ORR : LogicalReg<0b01, 0, "orr", or>;

	def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;			def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
	def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;			def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;

	▲ Show 20 Lines • Show All 5,032 Lines • Show Last 20 Lines

test/CodeGen/AArch64/eon.ll

This file was added.

				; RUN: llc -mtriple=aarch64-none-linux-gnu < %s \| FileCheck %s

				; Check that the eon instruction is generated instead of eor,movn
				define i64 @f(i64 %a, i64 %b, i64 %c) {
				; CHECK-LABEL: f
				t.p.northoverUnsubmitted Not Done Reply Inline Actions This is almost certainly too weak. It'll grab the f from ".file", and even if it didn't do that it often matches the ".size complex_function_name, .Lcomplex_function_name_end0 - complex_function_name". I usually find "CHECK-LABEL: f:" works better, colons are far less common in assembly. t.p.northover: This is almost certainly too weak. It'll grab the f from ".file", and even if it didn't do that…
				; CHECK: eon
				; CHECK: ret
				entry:
				%shl = shl i64 %b, 4
				%neg = xor i64 %a, -1
				%xor = xor i64 %shl, %neg
				ret i64 %xor
				}

				; Same check with mutliple uses of %neg
				define i64 @f2(i64 %a, i64 %b, i64 %c) {
				; CHECK-LABEL: f2
				; CHECK: eon
				; CHECK: eon
				; CHECK: lsl
				; CHECK: ret
				entry:
				%shl = shl i64 %b, 4
				%neg = xor i64 %shl, -1
				%xor = xor i64 %neg, %a
				%xor1 = xor i64 %c, %neg
				%shl2 = shl i64 %xor, %xor1
				ret i64 %shl2
				}