[ORC][ORC-RT] Enable the MachO platform for arm64

[benlangmuir]

Summary

Enables the arm64 MachO platform, adds basic tests, and implements the missing TLV relocations and runtime wrapper function. The TLV relocations are just handled as GOT accesses.

[lhames]

Very cool. Thanks Ben!

compiler-rt/lib/orc/CMakeLists.txt

 # Build for all components of the ORC runtime support library.
 
 # ORC runtime library implementation files.
 set(ORC_SOURCES
   extensible_rtti.cpp
   log_error_to_stderr.cpp
   macho_platform.cpp
   elfnix_platform.cpp
   run_program_wrapper.cpp
   )
 
 # Implementation files for all ORC architectures.
 set(ALL_ORC_ASM_SOURCES
   macho_tlv.x86-64.S
+  macho_tlv.arm64.S
   elfnix_tls.x86-64.S
 )
 
 set(ORC_IMPL_HEADERS
 # Implementation headers will go here.
   adt.h
   c_api.h
   common.h

 add_compiler_rt_component(orc)
 
 # ORC uses C++ standard library headers.
 if (TARGET cxx-headers OR HAVE_LIBCXX)
   set(ORC_DEPS cxx-headers)
 endif()
 
 if (APPLE)
-  add_asm_sources(ORC_ASM_SOURCES macho_tlv.x86-64.S)
+  add_asm_sources(ORC_ASM_SOURCES
+    macho_tlv.x86-64.S
+    macho_tlv.arm64.S
+    )
 
   add_compiler_rt_object_libraries(RTOrc
     OS ${ORC_SUPPORTED_OS}
     ARCHS ${ORC_SUPPORTED_ARCH}
     SOURCES ${ORC_SOURCES} ${ORC_ASM_SOURCES}
     ADDITIONAL_HEADERS ${ORC_IMPL_HEADERS}
     CFLAGS ${ORC_CFLAGS}
     DEPS ${ORC_DEPS})

compiler-rt/lib/orc/macho_tlv.arm64.S

+//===-- macho_tlv.arm64.s ---------------------------------------*- ASM -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is a part of the ORC runtime support library.
+//
+//===----------------------------------------------------------------------===//
+
+// The content of this file is arm64-only
+#if defined(__arm64__) || defined(__aarch64__)
+
+#define REGISTER_SAVE_SPACE_SIZE     32 * 24
+
+        .text
+
+  // returns address of TLV in x0, all other registers preserved
+  .globl ___orc_rt_macho_tlv_get_addr
+___orc_rt_macho_tlv_get_addr:
+        sub  sp,  sp, #REGISTER_SAVE_SPACE_SIZE
+        stp x29, x30, [sp, #16 * 1]
+        stp x27, x28, [sp, #16 * 2]
+        stp x25, x26, [sp, #16 * 3]
+        stp x23, x24, [sp, #16 * 4]
+        stp x21, x22, [sp, #16 * 5]
+        stp x19, x20, [sp, #16 * 6]
+        stp x17, x18, [sp, #16 * 7]
+        stp x15, x16, [sp, #16 * 8]
+        stp x13, x14, [sp, #16 * 9]
+        stp x11, x12, [sp, #16 * 10]
+        stp  x9, x10, [sp, #16 * 11]
+        stp  x7,  x8, [sp, #16 * 12]
+        stp  x5,  x6, [sp, #16 * 13]
+        stp  x3,  x4, [sp, #16 * 14]
+        stp  x1,  x2, [sp, #16 * 15]
+        stp q30, q31, [sp, #32 * 8]
+        stp q28, q29, [sp, #32 * 9]
+        stp q26, q27, [sp, #32 * 10]
+        stp q24, q25, [sp, #32 * 11]
+        stp q22, q23, [sp, #32 * 12]
+        stp q20, q21, [sp, #32 * 13]
+        stp q18, q19, [sp, #32 * 14]
+        stp q16, q17, [sp, #32 * 15]
+        stp q14, q15, [sp, #32 * 16]
+        stp q12, q13, [sp, #32 * 17]
+        stp q10, q11, [sp, #32 * 18]
+        stp  q8,  q9, [sp, #32 * 19]
+        stp  q6,  q7, [sp, #32 * 20]
+        stp  q4,  q5, [sp, #32 * 21]
+        stp  q2,  q3, [sp, #32 * 22]
+        stp  q0,  q1, [sp, #32 * 23]
+
+        bl ___orc_rt_macho_tlv_get_addr_impl
+
+        ldp  q0,  q1, [sp, #32 * 23]
+        ldp  q2,  q3, [sp, #32 * 22]
+        ldp  q4,  q5, [sp, #32 * 21]
+        ldp  q6,  q7, [sp, #32 * 20]
+        ldp  q8,  q9, [sp, #32 * 19]
+        ldp q10, q11, [sp, #32 * 18]
+        ldp q12, q13, [sp, #32 * 17]
+        ldp q14, q15, [sp, #32 * 16]
+        ldp q16, q17, [sp, #32 * 15]
+        ldp q18, q19, [sp, #32 * 14]
+        ldp q20, q21, [sp, #32 * 13]
+        ldp q22, q23, [sp, #32 * 12]
+        ldp q24, q25, [sp, #32 * 11]
+        ldp q26, q27, [sp, #32 * 10]
+        ldp q28, q29, [sp, #32 * 9]
+        ldp q30, q31, [sp, #32 * 8]
+        ldp  x1,  x2, [sp, #16 * 15]
+        ldp  x3,  x4, [sp, #16 * 14]
+        ldp  x5,  x6, [sp, #16 * 13]
+        ldp  x7,  x8, [sp, #16 * 12]
+        ldp  x9, x10, [sp, #16 * 11]
+        ldp x11, x12, [sp, #16 * 10]
+        ldp x13, x14, [sp, #16 * 9]
+        ldp x15, x16, [sp, #16 * 8]
+        ldp x17, x18, [sp, #16 * 7]
+        ldp x19, x20, [sp, #16 * 6]
+        ldp x21, x22, [sp, #16 * 5]
+        ldp x23, x24, [sp, #16 * 4]
+        ldp x25, x26, [sp, #16 * 3]
+        ldp x27, x28, [sp, #16 * 2]
+        ldp x29, x30, [sp, #16 * 1]
+        add  sp,  sp, #REGISTER_SAVE_SPACE_SIZE
+        ret
+
+#endif // defined(__arm64__) || defined(__aarch64__)

compiler-rt/test/orc/TestCases/Darwin/arm64/lit.local.cfg.py

+if config.root.host_arch not in ['aarch64', 'arm64']:
+  config.unsupported = True
+
+if config.target_arch not in ['aarch64', 'arm64']:
+  config.unsupported = True
 No newline at end of file

compiler-rt/test/orc/TestCases/Darwin/arm64/trivial-cxa-atexit.S

+// Test that the runtime correctly interposes ___cxa_atexit.
+//
+// RUN: %clang -c -o %t %s
+// RUN: %llvm_jitlink %t
+
+  .section  __TEXT,__text,regular,pure_instructions
+  .build_version macos, 12, 0 sdk_version 12, 0
+
+# main registers the atexit and sets the test result to one.
+  .globl  _main                           ; -- Begin function main
+  .p2align  2
+_main:                                  ; @main
+; %bb.0:
+  sub sp, sp, #32                     ; =32
+  stp x29, x30, [sp, #16]             ; 16-byte Folded Spill
+  add x29, sp, #16                    ; =16
+  stur  wzr, [x29, #-4]
+  adrp  x8, __ZGVZ4mainE6onExit@PAGE
+  add x8, x8, __ZGVZ4mainE6onExit@PAGEOFF
+  ldarb w8, [x8]
+  and w8, w8, #0x1
+  and w8, w8, #0xff
+  cbnz  w8, LBB0_3
+; %bb.1:
+  adrp  x0, __ZGVZ4mainE6onExit@PAGE
+  add x0, x0, __ZGVZ4mainE6onExit@PAGEOFF
+  bl  ___cxa_guard_acquire
+  cbz w0, LBB0_3
+; %bb.2:
+  adrp  x0, __ZN6OnExitD1Ev@GOTPAGE
+  ldr x0, [x0, __ZN6OnExitD1Ev@GOTPAGEOFF]
+  adrp  x1, __ZZ4mainE6onExit@PAGE
+  add x1, x1, __ZZ4mainE6onExit@PAGEOFF
+  adrp  x2, ___dso_handle@PAGE
+  add x2, x2, ___dso_handle@PAGEOFF
+  bl  ___cxa_atexit
+  adrp  x0, __ZGVZ4mainE6onExit@PAGE
+  add x0, x0, __ZGVZ4mainE6onExit@PAGEOFF
+  bl  ___cxa_guard_release
+LBB0_3:
+  mov x0, #1
+  bl  _llvm_jitlink_setTestResultOverride
+  mov w0, #0
+  ldp x29, x30, [sp, #16]             ; 16-byte Folded Reload
+  add sp, sp, #32                     ; =32
+  ret
+                                        ; -- End function
+
+# OnExit destructor resets the test result override to zero.
+  .globl  __ZN6OnExitD1Ev                 ; -- Begin function _ZN6OnExitD1Ev
+  .weak_def_can_be_hidden __ZN6OnExitD1Ev
+  .p2align  2
+__ZN6OnExitD1Ev:                        ; @_ZN6OnExitD1Ev
+; %bb.0:
+  sub sp, sp, #32                     ; =32
+  stp x29, x30, [sp, #16]             ; 16-byte Folded Spill
+  add x29, sp, #16                    ; =16
+  str x0, [sp, #8]
+  ldr x0, [sp, #8]
+  str x0, [sp]                        ; 8-byte Folded Spill
+  bl  __ZN6OnExitD2Ev
+  ldr x0, [sp]                        ; 8-byte Folded Reload
+  ldp x29, x30, [sp, #16]             ; 16-byte Folded Reload
+  add sp, sp, #32                     ; =32
+  ret
+                                        ; -- End function
+  .globl  __ZN6OnExitD2Ev                 ; -- Begin function _ZN6OnExitD2Ev
+  .weak_def_can_be_hidden __ZN6OnExitD2Ev
+  .p2align  2
+__ZN6OnExitD2Ev:                        ; @_ZN6OnExitD2Ev
+; %bb.0:
+  sub sp, sp, #32                     ; =32
+  stp x29, x30, [sp, #16]             ; 16-byte Folded Spill
+  add x29, sp, #16                    ; =16
+  str x0, [sp, #8]
+  ldr x8, [sp, #8]
+  str x8, [sp]                        ; 8-byte Folded Spill
+  mov x0, #0
+  bl  _llvm_jitlink_setTestResultOverride
+  ldr x0, [sp]                        ; 8-byte Folded Reload
+  ldp x29, x30, [sp, #16]             ; 16-byte Folded Reload
+  add sp, sp, #32                     ; =32
+  ret
+                                        ; -- End function
+.zerofill __DATA,__bss,__ZZ4mainE6onExit,1,0 ; @_ZZ4mainE6onExit
+.zerofill __DATA,__bss,__ZGVZ4mainE6onExit,8,3 ; @_ZGVZ4mainE6onExit
+.subsections_via_symbols

compiler-rt/test/orc/TestCases/Darwin/arm64/trivial-objc-methods.S

+// RUN: %clang -c -o %t %s
+// RUN: %llvm_jitlink -dlopen libobjc.A.dylib %t
+//
+// Test that Objective-C class and instance methods work.
+
+  .section  __TEXT,__text,regular,pure_instructions
+  .build_version macos, 12, 0 sdk_version 12, 0
+  .p2align  2                               ; -- Begin function +[ZeroGen classZero]
+"+[ZeroGen classZero]":                 ; @"\01+[ZeroGen classZero]"
+  .cfi_startproc
+; %bb.0:
+  sub sp, sp, #16                     ; =16
+  .cfi_def_cfa_offset 16
+  str x0, [sp, #8]
+  str x1, [sp]
+  mov w0, #0
+  add sp, sp, #16                     ; =16
+  ret
+  .cfi_endproc
+                                        ; -- End function
+  .p2align  2                               ; -- Begin function -[ZeroGen objZero]
+"-[ZeroGen objZero]":                   ; @"\01-[ZeroGen objZero]"
+  .cfi_startproc
+; %bb.0:
+  sub sp, sp, #16                     ; =16
+  .cfi_def_cfa_offset 16
+  str x0, [sp, #8]
+  str x1, [sp]
+  mov w0, #0
+  add sp, sp, #16                     ; =16
+  ret
+  .cfi_endproc
+                                        ; -- End function
+  .globl  _main                           ; -- Begin function main
+  .p2align  2
+_main:                                  ; @main
+  .cfi_startproc
+; %bb.0:
+  sub sp, sp, #48                     ; =48
+  stp  x29, x30, [sp, #32]             ; 16-byte Folded Spill
+  add x29, sp, #32                    ; =32
+  .cfi_def_cfa w29, 16
+  .cfi_offset w30, -8
+  .cfi_offset w29, -16
+  stur  wzr, [x29, #-4]
+  adrp  x8, _OBJC_CLASSLIST_REFERENCES_$_@PAGE
+  str x8, [sp, #8]                    ; 8-byte Folded Spill
+  ldr  x0, [x8, _OBJC_CLASSLIST_REFERENCES_$_@PAGEOFF]
+  bl  _objc_alloc_init
+  ldr x8, [sp, #8]                    ; 8-byte Folded Reload
+  str x0, [sp, #16]
+  ldr  x0, [x8, _OBJC_CLASSLIST_REFERENCES_$_@PAGEOFF]
+  adrp  x8, _OBJC_SELECTOR_REFERENCES_@PAGE
+  ldr  x1, [x8, _OBJC_SELECTOR_REFERENCES_@PAGEOFF]
+  bl  _objc_msgSend
+  cbz w0, LBB2_2
+; %bb.1:
+  mov w8, #1
+  stur  w8, [x29, #-4]
+  b LBB2_5
+LBB2_2:
+  ldr x0, [sp, #16]
+  adrp  x8, _OBJC_SELECTOR_REFERENCES_.2@PAGE
+  ldr x1, [x8, _OBJC_SELECTOR_REFERENCES_.2@PAGEOFF]
+  bl  _objc_msgSend
+  cbz w0, LBB2_4
+; %bb.3:
+  mov w8, #1
+  stur  w8, [x29, #-4]
+  b LBB2_5
+LBB2_4:
+  stur  wzr, [x29, #-4]
+LBB2_5:
+  ldur  w0, [x29, #-4]
+  ldp  x29, x30, [sp, #32]             ; 16-byte Folded Reload
+  add sp, sp, #48                     ; =48
+  ret
+  .cfi_endproc
+                                        ; -- End function
+  .section  __TEXT,__objc_classname,cstring_literals
+l_OBJC_CLASS_NAME_:                     ; @OBJC_CLASS_NAME_
+  .asciz  "ZeroGen"
+
+  .section  __TEXT,__objc_methname,cstring_literals
+l_OBJC_METH_VAR_NAME_:                  ; @OBJC_METH_VAR_NAME_
+  .asciz  "classZero"
+
+  .section  __TEXT,__objc_methtype,cstring_literals
+l_OBJC_METH_VAR_TYPE_:                  ; @OBJC_METH_VAR_TYPE_
+  .asciz  "i16@0:8"
+
+  .section  __DATA,__objc_const
+  .p2align  3                               ; @"_OBJC_$_CLASS_METHODS_ZeroGen"
+__OBJC_$_CLASS_METHODS_ZeroGen:
+  .long 24                              ; 0x18
+  .long 1                               ; 0x1
+  .quad l_OBJC_METH_VAR_NAME_
+  .quad l_OBJC_METH_VAR_TYPE_
+  .quad "+[ZeroGen classZero]"
+
+  .p2align  3                               ; @"_OBJC_METACLASS_RO_$_ZeroGen"
+__OBJC_METACLASS_RO_$_ZeroGen:
+  .long 1                               ; 0x1
+  .long 40                              ; 0x28
+  .long 40                              ; 0x28
+  .space  4
+  .quad 0
+  .quad l_OBJC_CLASS_NAME_
+  .quad __OBJC_$_CLASS_METHODS_ZeroGen
+  .quad 0
+  .quad 0
+  .quad 0
+  .quad 0
+
+  .section  __DATA,__objc_data
+  .globl  _OBJC_METACLASS_$_ZeroGen       ; @"OBJC_METACLASS_$_ZeroGen"
+  .p2align  3
+_OBJC_METACLASS_$_ZeroGen:
+  .quad _OBJC_METACLASS_$_NSObject
+  .quad _OBJC_METACLASS_$_NSObject
+  .quad __objc_empty_cache
+  .quad 0
+  .quad __OBJC_METACLASS_RO_$_ZeroGen
+
+  .section  __TEXT,__objc_methname,cstring_literals
+l_OBJC_METH_VAR_NAME_.1:                ; @OBJC_METH_VAR_NAME_.1
+  .asciz  "objZero"
+
+  .section  __DATA,__objc_const
+  .p2align  3                               ; @"_OBJC_$_INSTANCE_METHODS_ZeroGen"
+__OBJC_$_INSTANCE_METHODS_ZeroGen:
+  .long 24                              ; 0x18
+  .long 1                               ; 0x1
+  .quad l_OBJC_METH_VAR_NAME_.1
+  .quad l_OBJC_METH_VAR_TYPE_
+  .quad "-[ZeroGen objZero]"
+
+  .p2align  3                               ; @"_OBJC_CLASS_RO_$_ZeroGen"
+__OBJC_CLASS_RO_$_ZeroGen:
+  .long 0                               ; 0x0
+  .long 8                               ; 0x8
+  .long 8                               ; 0x8
+  .space  4
+  .quad 0
+  .quad l_OBJC_CLASS_NAME_
+  .quad __OBJC_$_INSTANCE_METHODS_ZeroGen
+  .quad 0
+  .quad 0
+  .quad 0
+  .quad 0
+
+  .section  __DATA,__objc_data
+  .globl  _OBJC_CLASS_$_ZeroGen           ; @"OBJC_CLASS_$_ZeroGen"
+  .p2align  3
+_OBJC_CLASS_$_ZeroGen:
+  .quad _OBJC_METACLASS_$_ZeroGen
+  .quad _OBJC_CLASS_$_NSObject
+  .quad __objc_empty_cache
+  .quad 0
+  .quad __OBJC_CLASS_RO_$_ZeroGen
+
+  .section  __DATA,__objc_classrefs,regular,no_dead_strip
+  .p2align  3                               ; @"OBJC_CLASSLIST_REFERENCES_$_"
+_OBJC_CLASSLIST_REFERENCES_$_:
+  .quad _OBJC_CLASS_$_ZeroGen
+
+  .section  __DATA,__objc_selrefs,literal_pointers,no_dead_strip
+  .p2align  3                               ; @OBJC_SELECTOR_REFERENCES_
+_OBJC_SELECTOR_REFERENCES_:
+  .quad l_OBJC_METH_VAR_NAME_
+
+  .p2align  3                               ; @OBJC_SELECTOR_REFERENCES_.2
+_OBJC_SELECTOR_REFERENCES_.2:
+  .quad l_OBJC_METH_VAR_NAME_.1
+
+  .section  __DATA,__objc_classlist,regular,no_dead_strip
+  .p2align  3                               ; @"OBJC_LABEL_CLASS_$"
+l_OBJC_LABEL_CLASS_$:
+  .quad _OBJC_CLASS_$_ZeroGen
+
+  .section  __DATA,__objc_imageinfo,regular,no_dead_strip
+L_OBJC_IMAGE_INFO:
+  .long 0
+  .long 64
+
+.subsections_via_symbols

compiler-rt/test/orc/TestCases/Darwin/arm64/trivial-static-initializer.S

+// Test that basic MachO static initializers work. The main function in this
+// test returns the value of 'x', which is initially 1 in the data section,
+// and reset to 0 if the _static_init function is run. If the static initializer
+// does not run then main will return 1, causing the test to be treated as a
+// failure.
+//
+// RUN: %clang -c -o %t %s
+// RUN: %llvm_jitlink %t
+
+  .section  __TEXT,__text,regular,pure_instructions
+  .build_version macos, 12, 0 sdk_version 12, 0
+
+# static initializer sets the value of 'x' to zero.
+  .globl  _static_init
+  .p2align  2
+_static_init:
+  .cfi_startproc
+; %bb.0:
+  adrp  x8, _x@PAGE
+  str wzr, [x8, _x@PAGEOFF]
+  ret
+  .cfi_endproc
+
+# main returns the value of 'x', which is defined as 1 in the data section..
+  .globl  _main
+  .p2align  2
+_main:
+  sub sp, sp, #16
+  str wzr, [sp, #12]
+  adrp  x8, _x@PAGE
+  ldr w0, [x8, _x@PAGEOFF]
+  add sp, sp, #16
+  ret
+
+  .section  __DATA,__data
+  .globl  _x
+  .p2align  2
+_x:
+  .long 1
+
+  .section  __DATA,__mod_init_func,mod_init_funcs
+  .p2align  3
+  .quad _static_init
+.subsections_via_symbols
 No newline at end of file

compiler-rt/test/orc/TestCases/Darwin/arm64/trivial-tlv.S

+// Test that basic MachO TLVs work by adding together TLVs with values
+// 0, 1, and -1, and returning the result (0 for success). This setup
+// tests both zero-initialized (__thread_bss) and non-zero-initialized
+// (__thread_data) secitons.
+//
+// RUN: %clang -c -o %t %s
+// RUN: %llvm_jitlink %t
+
+  .section  __TEXT,__text,regular,pure_instructions
+  .build_version macos, 12, 0 sdk_version 12, 0
+  .globl  _main                           ; -- Begin function main
+  .p2align  2
+_main:                                  ; @main
+  .cfi_startproc
+; %bb.0:
+  sub sp, sp, #32                     ; =32
+  stp x29, x30, [sp, #16]             ; 16-byte Folded Spill
+  add x29, sp, #16                    ; =16
+  .cfi_def_cfa w29, 16
+  .cfi_offset w30, -8
+  .cfi_offset w29, -16
+  adrp  x0, _x@TLVPPAGE
+  ldr x0, [x0, _x@TLVPPAGEOFF]
+  ldr x8, [x0]
+  blr x8
+  mov x8, x0
+  adrp  x0, _y@TLVPPAGE
+  ldr x0, [x0, _y@TLVPPAGEOFF]
+  ldr x9, [x0]
+  blr x9
+  mov x9, x0
+  adrp  x0, _z@TLVPPAGE
+  ldr x0, [x0, _z@TLVPPAGEOFF]
+  ldr x10, [x0]
+  blr x10
+  stur  wzr, [x29, #-4]
+  ldr w8, [x8]
+  ldr w9, [x9]
+  add w8, w8, w9
+  ldr w9, [x0]
+  add w0, w8, w9
+  ldp x29, x30, [sp, #16]             ; 16-byte Folded Reload
+  add sp, sp, #32                     ; =32
+  ret
+  .cfi_endproc
+                                        ; -- End function
+.tbss _x$tlv$init, 4, 2                 ; @x
+
+  .section  __DATA,__thread_vars,thread_local_variables
+  .globl  _x
+_x:
+  .quad __tlv_bootstrap
+  .quad 0
+  .quad _x$tlv$init
+
+  .section  __DATA,__thread_data,thread_local_regular
+  .p2align  2                               ; @y
+_y$tlv$init:
+  .long 4294967295                      ; 0xffffffff
+
+  .section  __DATA,__thread_vars,thread_local_variables
+  .globl  _y
+_y:
+  .quad __tlv_bootstrap
+  .quad 0
+  .quad _y$tlv$init
+
+  .section  __DATA,__thread_data,thread_local_regular
+  .p2align  2                               ; @z
+_z$tlv$init:
+  .long 1                               ; 0x1
+
+  .section  __DATA,__thread_vars,thread_local_variables
+  .globl  _z
+_z:
+  .quad __tlv_bootstrap
+  .quad 0
+  .quad _z$tlv$init
+
+.subsections_via_symbols

llvm/include/llvm/ExecutionEngine/JITLink/MachO_arm64.h

enum MachOARM64RelocationKind : Edge::Kind {
   Branch26 = Edge::FirstRelocation,
   Pointer32,
   Pointer64,
   Pointer64Anon,
   Page21,
   PageOffset12,
   GOTPage21,
   GOTPageOffset12,
+  TLVPage21,
+  TLVPageOffset12,
   PointerToGOT,
   PairedAddend,
   LDRLiteral19,
   Delta32,
   Delta64,
   NegDelta32,
   NegDelta64,
 };

llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp

getRelocationKind(const MachO::relocation_info &RI) {
     case MachO::ARM64_RELOC_POINTER_TO_GOT:
       if (RI.r_pcrel && RI.r_extern && RI.r_length == 2)
         return PointerToGOT;
       break;
     case MachO::ARM64_RELOC_ADDEND:
       if (!RI.r_pcrel && !RI.r_extern && RI.r_length == 2)
         return PairedAddend;
       break;
+    case MachO::ARM64_RELOC_TLVP_LOAD_PAGE21:
+      if (RI.r_pcrel && RI.r_extern && RI.r_length == 2)
+        return TLVPage21;
+      break;
+    case MachO::ARM64_RELOC_TLVP_LOAD_PAGEOFF12:
+      if (!RI.r_pcrel && RI.r_extern && RI.r_length == 2)
+        return TLVPageOffset12;
+      break;
     }
 
     return make_error<JITLinkError>(
         "Unsupported arm64 relocation: address=" +
         formatv("{0:x8}", RI.r_address) +
         ", symbolnum=" + formatv("{0:x6}", RI.r_symbolnum) +
         ", kind=" + formatv("{0:x1}", RI.r_type) +
         ", pc_rel=" + (RI.r_pcrel ? "true" : "false") +
for (auto &S : Obj.sections()) {
           if (auto TargetSymbolOrErr = findSymbolByAddress(TargetAddress))
             TargetSymbol = &*TargetSymbolOrErr;
           else
             return TargetSymbolOrErr.takeError();
           Addend = TargetAddress - TargetSymbol->getAddress();
           break;
         }
         case Page21:
+        case TLVPage21:
         case GOTPage21: {
           if (auto TargetSymbolOrErr = findSymbolByIndex(RI.r_symbolnum))
             TargetSymbol = TargetSymbolOrErr->GraphSymbol;
           else
             return TargetSymbolOrErr.takeError();
           uint32_t Instr = *(const ulittle32_t *)FixupContent;
           if ((Instr & 0xffffffe0) != 0x90000000)
             return make_error<JITLinkError>("PAGE21/GOTPAGE21 target is not an "
                                             "ADRP instruction with a zero "
                                             "addend");
           break;
         }
         case PageOffset12: {
           if (auto TargetSymbolOrErr = findSymbolByIndex(RI.r_symbolnum))
             TargetSymbol = TargetSymbolOrErr->GraphSymbol;
           else
             return TargetSymbolOrErr.takeError();
           uint32_t Instr = *(const ulittle32_t *)FixupContent;
           uint32_t EncodedAddend = (Instr & 0x003FFC00) >> 10;
           if (EncodedAddend != 0)
             return make_error<JITLinkError>("GOTPAGEOFF12 target has non-zero "
                                             "encoded addend");
           break;
         }
+        case TLVPageOffset12:
         case GOTPageOffset12: {
           if (auto TargetSymbolOrErr = findSymbolByIndex(RI.r_symbolnum))
             TargetSymbol = TargetSymbolOrErr->GraphSymbol;
           else
             return TargetSymbolOrErr.takeError();
           uint32_t Instr = *(const ulittle32_t *)FixupContent;
           if ((Instr & 0xfffffc00) != 0xf9400000)
             return make_error<JITLinkError>("GOTPAGEOFF12 target is not an LDR "
class PerGraphGOTAndPLTStubsBuilder_MachO_arm64
     : public PerGraphGOTAndPLTStubsBuilder<
           PerGraphGOTAndPLTStubsBuilder_MachO_arm64> {
 public:
   using PerGraphGOTAndPLTStubsBuilder<
       PerGraphGOTAndPLTStubsBuilder_MachO_arm64>::PerGraphGOTAndPLTStubsBuilder;
 
   bool isGOTEdgeToFix(Edge &E) const {
     return E.getKind() == GOTPage21 || E.getKind() == GOTPageOffset12 ||
+           E.getKind() == TLVPage21 || E.getKind() == TLVPageOffset12 ||
            E.getKind() == PointerToGOT;
   }
 
   Symbol &createGOTEntry(Symbol &Target) {
     auto &GOTEntryBlock = G.createContentBlock(
         getGOTSection(), getGOTEntryBlockContent(), 0, 8, 0);
     GOTEntryBlock.addEdge(Pointer64, 0, Target, 0);
     return G.addAnonymousSymbol(GOTEntryBlock, 0, 8, false, false);
   }
 
   void fixGOTEdge(Edge &E, Symbol &GOTEntry) {
-    if (E.getKind() == GOTPage21 || E.getKind() == GOTPageOffset12) {
+    if (E.getKind() == GOTPage21 || E.getKind() == GOTPageOffset12 ||
+        E.getKind() == TLVPage21 || E.getKind() == TLVPageOffset12) {
       // Update the target, but leave the edge addend as-is.
       E.setTarget(GOTEntry);
     } else if (E.getKind() == PointerToGOT) {
       E.setTarget(GOTEntry);
       E.setKind(Delta32);
     } else
       llvm_unreachable("Not a GOT edge?");
   }
Error applyFixup(LinkGraph &G, Block &B, const Edge &E) const {
     }
     case Pointer64:
     case Pointer64Anon: {
       uint64_t Value = E.getTarget().getAddress() + E.getAddend();
       *(ulittle64_t *)FixupPtr = Value;
       break;
     }
     case Page21:
+    case TLVPage21:
     case GOTPage21: {
       assert((E.getKind() != GOTPage21 || E.getAddend() == 0) &&
              "GOTPAGE21 with non-zero addend");
       uint64_t TargetPage =
           (E.getTarget().getAddress() + E.getAddend()) &
             ~static_cast<uint64_t>(4096 - 1);
       uint64_t PCPage = FixupAddress & ~static_cast<uint64_t>(4096 - 1);
 
case PageOffset12: {
       if (TargetOffset & ((1 << ImmShift) - 1))
         return make_error<JITLinkError>("PAGEOFF12 target is not aligned");
 
       uint32_t EncodedImm = (TargetOffset >> ImmShift) << 10;
       uint32_t FixedInstr = RawInstr | EncodedImm;
       *(ulittle32_t *)FixupPtr = FixedInstr;
       break;
     }
+    case TLVPageOffset12:
     case GOTPageOffset12: {
       assert(E.getAddend() == 0 && "GOTPAGEOF12 with non-zero addend");
 
       uint32_t RawInstr = *(ulittle32_t *)FixupPtr;
       assert((RawInstr & 0xfffffc00) == 0xf9400000 &&
              "RawInstr isn't a 64-bit LDR immediate");
 
       uint32_t TargetOffset = E.getTarget().getAddress() & 0xfff;
const char *getMachOARM64RelocationKindName(Edge::Kind R) {
   case Page21:
     return "Page21";
   case PageOffset12:
     return "PageOffset12";
   case GOTPage21:
     return "GOTPage21";
   case GOTPageOffset12:
     return "GOTPageOffset12";
+  case TLVPage21:
+    return "TLVPage21";
+  case TLVPageOffset12:
+    return "TLVPageOffset12";
   case PointerToGOT:
     return "PointerToGOT";
   case PairedAddend:
     return "PairedAddend";
   case LDRLiteral19:
     return "LDRLiteral19";
   case Delta32:
     return "Delta32";

llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp

for (auto &Name : InitSectionNames) {
     if (Name.startswith(SegName) && Name.substr(7) == SectName)
       return true;
   }
   return false;
 }
 
 bool MachOPlatform::supportedTarget(const Triple &TT) {
   switch (TT.getArch()) {
+  case Triple::aarch64:
   case Triple::x86_64:
     return true;
   default:
     return false;
   }
 }
 
 MachOPlatform::MachOPlatform(