[CodeGen] Don't lower consecutive select instructions with different kind if target don't support it

[D.Kharlamov]

Summary

Some targets(f.e. ARM) can't lower some SelectKind's . Don't expand/not expand consecutive selects if some of it has different legality.

[dmgreen]

Hello. I think this makes sense, but is it targeted at Arm or for some other backend? At least under MVE we don't really not support ScalarCondVectorVal selects, even if they can be a bit inefficient (less branches but more vector code).

[D.Kharlamov]

Hello. It's for private target. It has same TargetLowering::isSelectSupported() as in ARM target. This patch removes inconsistency when selects are not lowered by CodegenPrepare.

[dmgreen]

OK. That makes sense. It was just that the test case here we made work already in the backend :) It's not really an unsupported case. It looks like it makes a good testcase though.

llvm/lib/CodeGen/CodeGenPrepare.cpp

6721

Perhaps change "have the same kind" to "are equally supported"?

llvm/lib/CodeGen/CodeGenPrepare.cpp

 }
 
 /// If we have a SelectInst that will likely profit from branch prediction,
 /// turn it into a branch.
 bool CodeGenPrepare::optimizeSelectInst(SelectInst *SI) {
   if (DisableSelectToBranch)
     return false;
 
-  // Find all consecutive select instructions that share the same condition.
+  auto GetSelectKind = [](const SelectInst *SI) {
+    if (SI->getCondition()->getType()->isVectorTy())
+      return TargetLowering::VectorMaskSelect;
+    if (SI->getType()->isVectorTy())
+      return TargetLowering::ScalarCondVectorVal;
+    return TargetLowering::ScalarValSelect;
+  };
+
+  bool IsSelectSupported = TLI->isSelectSupported(GetSelectKind(SI));
+  // Find all consecutive select instructions that share the same condition and
+  // have same kind.
   SmallVector<SelectInst *, 2> ASI;
   ASI.push_back(SI);
   for (BasicBlock::iterator It = ++BasicBlock::iterator(SI);
        It != SI->getParent()->end(); ++It) {
     SelectInst *I = dyn_cast<SelectInst>(&*It);
-    if (I && SI->getCondition() == I->getCondition()) {
+    if (I && SI->getCondition() == I->getCondition() &&
+        IsSelectSupported == TLI->isSelectSupported(GetSelectKind(I))) {
       ASI.push_back(I);
     } else {
       break;
     }
   }
 
   SelectInst *LastSI = ASI.back();
   // Increment the current iterator to skip all the rest of select instructions
   // because they will be either "not lowered" or "all lowered" to branch.
   CurInstIterator = std::next(LastSI->getIterator());
 
   bool VectorCond = !SI->getCondition()->getType()->isIntegerTy(1);
 
   // Can we convert the 'select' to CF ?
   if (VectorCond || SI->getMetadata(LLVMContext::MD_unpredictable))
     return false;
 
-  TargetLowering::SelectSupportKind SelectKind;
-  if (VectorCond)
-    SelectKind = TargetLowering::VectorMaskSelect;
-  else if (SI->getType()->isVectorTy())
-    SelectKind = TargetLowering::ScalarCondVectorVal;
-  else
-    SelectKind = TargetLowering::ScalarValSelect;
-
-  if (TLI->isSelectSupported(SelectKind) &&
+  if (IsSelectSupported &&
       (!isFormingBranchFromSelectProfitable(TTI, TLI, SI) || OptSize ||
        llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI.get())))
     return false;
 
   // The DominatorTree needs to be rebuilt by any consumers after this
   // transformation. We simply reset here rather than setting the ModifiedDT
   // flag to avoid restarting the function walk in runOnFunction for each
   // select optimized.

llvm/test/CodeGen/Thumb2/mve-selectcc.ll

 define i32 @e() {
 ; CHECK-LABEL: e:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    adr r0, .LCPI14_0
 ; CHECK-NEXT:    vmov.i32 q1, #0x4
 ; CHECK-NEXT:    vldrw.u32 q0, [r0]
 ; CHECK-NEXT:    movs r0, #0
 ; CHECK-NEXT:    vmov q2, q0
-; CHECK-NEXT:  .LBB14_1: @ %vector.body
+; CHECK-NEXT:    b .LBB14_2
+; CHECK-NEXT:  .LBB14_1: @ %select.end
+; CHECK-NEXT:    @ in Loop: Header=BB14_2 Depth=1
+; CHECK-NEXT:    vmov q2, q3
+; CHECK-NEXT:  .LBB14_2: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    adds r0, #4
-; CHECK-NEXT:    vadd.i32 q2, q2, q1
-; CHECK-NEXT:    cmp r0, #8
-; CHECK-NEXT:    cset r1, eq
-; CHECK-NEXT:    cmp r1, #0
-; CHECK-NEXT:    csetm r1, ne
-; CHECK-NEXT:    subs.w r2, r0, #8
-; CHECK-NEXT:    vdup.32 q3, r1
-; CHECK-NEXT:    csel r0, r0, r2, ne
-; CHECK-NEXT:    vbic q2, q2, q3
-; CHECK-NEXT:    vand q3, q3, q0
-; CHECK-NEXT:    vorr q2, q3, q2
+; CHECK-NEXT:    adds r1, r0, #4
+; CHECK-NEXT:    vmov q3, q0
+; CHECK-NEXT:    subs.w r0, r1, #8
+; CHECK-NEXT:    csel r0, r1, r0, ne
+; CHECK-NEXT:    cmp r1, #8
+; CHECK-NEXT:    beq .LBB14_1
+; CHECK-NEXT:  @ %bb.3: @ %select.false
+; CHECK-NEXT:    @ in Loop: Header=BB14_2 Depth=1
+; CHECK-NEXT:    vadd.i32 q3, q2, q1
 ; CHECK-NEXT:    b .LBB14_1
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  @ %bb.2:
+; CHECK-NEXT:  @ %bb.4:
 ; CHECK-NEXT:  .LCPI14_0:
 ; CHECK-NEXT:    .long 0 @ 0x0
 ; CHECK-NEXT:    .long 1 @ 0x1
 ; CHECK-NEXT:    .long 2 @ 0x2
 ; CHECK-NEXT:    .long 3 @ 0x3
 entry:
   br label %vector.body