[ARM] Fix inline assembly referencing floating point registers on soft-float targets

[kpdev42]

Summary

Fixes PR: https://bugs.llvm.org/show_bug.cgi?id=52230

[nickdesaulniers]

thanks for the patch

clang/lib/Basic/Targets/ARM.h

class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {
   unsigned CRC : 1;
   unsigned Crypto : 1;
   unsigned SHA2 : 1;
   unsigned AES : 1;
   unsigned DSP : 1;
   unsigned Unaligned : 1;
   unsigned DotProd : 1;
   unsigned HasMatMul : 1;
+  unsigned FPRegsDisabled : 1;
 
   enum {
     LDREX_B = (1 << 0), /// byte (8-bit)
     LDREX_H = (1 << 1), /// half (16-bit)
     LDREX_W = (1 << 2), /// word (32-bit)
     LDREX_D = (1 << 3), /// double (64-bit)
   };
 

clang/lib/Basic/Targets/ARM.cpp

bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
   SoftFloat = false;
   // Note that SoftFloatABI is initialized in our constructor.
   HWDiv = 0;
   DotProd = 0;
   HasMatMul = 0;
   HasFloat16 = true;
   ARMCDECoprocMask = 0;
   HasBFloat16 = false;
+  FPRegsDisabled = false;
 
   // This does not diagnose illegal cases like having both
   // "+vfpv2" and "+vfpv3" or having "+neon" and "-fp64".
   for (const auto &Feature : Features) {
     if (Feature == "+soft-float") {
       SoftFloat = true;
     } else if (Feature == "+vfp2sp" || Feature == "+vfp2") {
       FPU |= VFP2FPU;
for (const auto &Feature : Features) {
     } else if (Feature == "+i8mm") {
       HasMatMul = 1;
     } else if (Feature.size() == strlen("+cdecp0") && Feature >= "+cdecp0" &&
                Feature <= "+cdecp7") {
       unsigned Coproc = Feature.back() - '0';
       ARMCDECoprocMask |= (1U << Coproc);
     } else if (Feature == "+bf16") {
       HasBFloat16 = true;
+    } else if (Feature == "-fpregs") {
+      FPRegsDisabled = true;
     }
   }
 
   switch (ArchVersion) {
   case 6:
     if (ArchProfile == llvm::ARM::ProfileKind::M)
       LDREX = 0;
     else if (ArchKind == llvm::ARM::ArchKind::ARMV6K)
if (isThumb()) {
       return true;
     }
     break;
   case 's': // An integer constant, but allowing only relocatable values.
     return true;
   case 't': // s0-s31, d0-d31, or q0-q15
   case 'w': // s0-s15, d0-d7, or q0-q3
   case 'x': // s0-s31, d0-d15, or q0-q7
+    if (FPRegsDisabled)
+      return false;
     Info.setAllowsRegister();
     return true;
   case 'j': // An immediate integer between 0 and 65535 (valid for MOVW)
     // only available in ARMv6T2 and above
     if (CPUAttr.equals("6T2") || ArchVersion >= 7) {
       Info.setRequiresImmediate(0, 65535);
       return true;
     }

clang/test/Sema/arm_inline_asm_constraints_no_fp_regs.c

+// REQUIRES: arm-registered-target
+// RUN: %clang_cc1 -triple arm -target-feature -fpregs -verify=arm-nofp %s
+
+// w: A 32, 64, or 128-bit floating-point/SIMD register: s0-s31, d0-d31, or q0-q15.
+float test_w(float x) {
+  __asm__("vsqrt.f32 %0, %1"
+          : "=w"(x)
+          : "w"(x)); // No error expected.
+  // arm-nofp-error@7 {{invalid output constraint '=w' in asm}}
+  return x;
+}
+
+// x: A 32, 64, or 128-bit floating-point/SIMD register: s0-s15, d0-d7, or q0-q3.
+float test_x(float x) {
+  __asm__("vsqrt.f32 %0, %1"
+          : "=x"(x)
+          : "x"(x)); // No error expected.
+  // arm-nofp-error@16 {{invalid output constraint '=x' in asm}}
+  return x;
+}
+
+// t: A 32, 64, or 128-bit floating-point/SIMD register: s0-s31, d0-d15, or q0-q7.
+float test_t(float x) {
+  __asm__("vsqrt.f32 %0, %1"
+          : "=t"(x)
+          : "t"(x)); // No error expected.
+  // arm-nofp-error@25 {{invalid output constraint '=t' in asm}}
+  return x;
+}