Add missing builtins to the PPC back end for ABI compliance (vol. 4)

[nemanjai]

Summary

This is the back end portion of the fourth round of additions to meet the ABI requirements for the ELF v2 ABI.
The back end portion of review D11184.

[wschmidt]

LGTM.

[nemanjai]

Committed revision 242167.

include/llvm/IR/IntrinsicsPowerPC.td

 def int_ppc_vsx_xvdivsp : PowerPC_VSX_Vec_FFF_Intrinsic<"xvdivsp">;
 
 // Vector round-to-infinity (ceil)
 def int_ppc_vsx_xvrspip :
       Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xvrdpip :
       Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
 
+// Vector reciprocal estimate
+def int_ppc_vsx_xvresp : GCCBuiltin<"__builtin_vsx_xvresp">,
+      Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvredp : GCCBuiltin<"__builtin_vsx_xvredp">,
+      Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
+
 // Vector rsqrte
 def int_ppc_vsx_xvrsqrtesp : GCCBuiltin<"__builtin_vsx_xvrsqrtesp">,
       Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xvrsqrtedp : GCCBuiltin<"__builtin_vsx_xvrsqrtedp">,
       Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
 
 // Vector compare
 def int_ppc_vsx_xvcmpeqdp :

lib/Target/PowerPC/PPCInstrVSX.td

def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
           (SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>;
 
 // Divides.
 def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B),
           (XVDIVSP $A, $B)>;
 def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B),
           (XVDIVDP $A, $B)>;
 
+// Reciprocal estimate
+def : Pat<(int_ppc_vsx_xvresp v4f32:$A),
+          (XVRESP $A)>;
+def : Pat<(int_ppc_vsx_xvredp v2f64:$A),
+          (XVREDP $A)>;
+
 // Recip. square root estimate
 def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A),
           (XVRSQRTESP $A)>;
 def : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A),
           (XVRSQRTEDP $A)>;
 
 } // AddedComplexity
 } // HasVSX

test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll

entry:
   %1 = load <4 x float>, <4 x float>* @vfb, align 16
   %2 = call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %0, <4 x float> %1)
   store <4 x i32> %2, <4 x i32>* @vbir, align 16
   ret void
 ; CHECK-LABEL: @test10
 ; CHECK: xvcmpgtsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 }
 
+; Function Attrs: nounwind
+define <4 x float> @emit_xvresp(<4 x float> %a) {
+entry:
+  %a.addr = alloca <4 x float>, align 16
+  store <4 x float> %a, <4 x float>* %a.addr, align 16
+  %0 = load <4 x float>, <4 x float>* %a.addr, align 16
+  %1 = call <4 x float> @llvm.ppc.vsx.xvresp(<4 x float> %0)
+  ret <4 x float> %1
+; CHECK-LABEL: @emit_xvresp
+; CHECK: xvresp {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define <2 x double> @emit_xvredp(<2 x double> %a) {
+entry:
+  %a.addr = alloca <2 x double>, align 16
+  store <2 x double> %a, <2 x double>* %a.addr, align 16
+  %0 = load <2 x double>, <2 x double>* %a.addr, align 16
+  %1 = call <2 x double> @llvm.ppc.vsx.xvredp(<2 x double> %0)
+  ret <2 x double> %1
+; CHECK-LABEL: @emit_xvredp
+; CHECK: xvredp {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Function Attrs: nounwind readnone
+declare <4 x float> @llvm.ppc.vsx.xvresp(<4 x float>)
+
+; Function Attrs: nounwind readnone
+declare <2 x double> @llvm.ppc.vsx.xvredp(<2 x double>)
+
 ; Function Attrs: nounwind readnone
 declare <2 x double> @llvm.ceil.v2f64(<2 x double>)
 
 ; Function Attrs: nounwind readnone
 declare <4 x float> @llvm.ceil.v4f32(<4 x float>)
 
 ; Function Attrs: nounwind readnone
 declare <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double>, <2 x double>)