[X86] WIP Prefer VEX encoding in X86 assembler.

[craig.topper]

Summary

An alternative version of D111538 and D111505. Attempting to create different operands for the VEX and EVEX instructions so that the AsmMatcher will infer an order for them. This is similar to how we normally prefer VEX over EVEX. The VEX register classes are smaller so they get ordered before the EVEX register classes.

Naming of the new operand types isn't great. Patch needs more comments. Had to make a hack to the EVEX2VEX emitter. Not sure if that's the best fix for it.

Maybe we should change the operands for the EVEX instructions instead of the VEX instructions.

Mainly posting this as inspiration for Yuanke. I don't know if I have time to finish this myself

[LuoYuanke]

Thank Craig for the patch. I may prefer https://reviews.llvm.org/D111505 because it is more generic.

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
 
   // These instructions are only available with {vex}, {vex2} or {vex3} prefix
   if (MCID.TSFlags & X86II::ExplicitVEXPrefix &&
       (ForcedVEXEncoding != VEXEncoding_VEX &&
        ForcedVEXEncoding != VEXEncoding_VEX2 &&
        ForcedVEXEncoding != VEXEncoding_VEX3))
     return Match_Unsupported;
 
-  // These instructions match ambiguously with their VEX encoded counterparts
-  // and appear first in the matching table. Reject them unless we're forcing
-  // EVEX encoding.
-  // FIXME: We really need a way to break the ambiguity.
-  switch (Opc) {
-  case X86::VCVTSD2SIZrm_Int:
-  case X86::VCVTSD2SI64Zrm_Int:
-  case X86::VCVTSS2SIZrm_Int:
-  case X86::VCVTSS2SI64Zrm_Int:
-  case X86::VCVTTSD2SIZrm:   case X86::VCVTTSD2SIZrm_Int:
-  case X86::VCVTTSD2SI64Zrm: case X86::VCVTTSD2SI64Zrm_Int:
-  case X86::VCVTTSS2SIZrm:   case X86::VCVTTSS2SIZrm_Int:
-  case X86::VCVTTSS2SI64Zrm: case X86::VCVTTSS2SI64Zrm_Int:
-    if (ForcedVEXEncoding != VEXEncoding_EVEX)
-      return Match_Unsupported;
-    break;
-  }
-
   return Match_Success;
 }
 
 bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
                                               OperandVector &Operands,
                                               MCStreamer &Out,
                                               uint64_t &ErrorInfo,
                                               bool MatchingInlineAsm) {

llvm/lib/Target/X86/AsmParser/X86Operand.h

bool isMem8() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 8);
   }
   bool isMem16() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 16);
   }
   bool isMem32() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 32);
   }
+  bool isMem32VEX() const {
+    return Kind == Memory && (!Mem.Size || Mem.Size == 32);
+  }
   bool isMem64() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 64);
   }
+  bool isMem64VEX() const {
+    return Kind == Memory && (!Mem.Size || Mem.Size == 64);
+  }
   bool isMem80() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 80);
   }
   bool isMem128() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 128);
   }
   bool isMem256() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 256);

llvm/lib/Target/X86/X86InstrFragmentsSIMD.td

def sse_load_f64 : PatFrags<(ops node:$ptr),
                             [(v2f64 (simple_load node:$ptr)),
                              (v2f64 (X86vzload64 node:$ptr)),
                              (v2f64 (scalar_to_vector (loadf64 node:$ptr)))]>;
 
 def shmem : X86MemOperand<"printwordmem", X86Mem16AsmOperand>;
 def ssmem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>;
 def sdmem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand>;
 
+def ssmem_vex : X86MemOperand<"printdwordmem", X86Mem32VEXAsmOperand>;
+def sdmem_vex : X86MemOperand<"printqwordmem", X86Mem64VEXAsmOperand>;
+
 def fp16imm0 : PatLeaf<(f16 fpimm), [{
   return N->isExactlyValue(+0.0);
 }]>;
 
 def fp32imm0 : PatLeaf<(f32 fpimm), [{
   return N->isExactlyValue(+0.0);
 }]>;
 

llvm/lib/Target/X86/X86InstrInfo.td

let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in {
   def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; }
   def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; }
   def X86Mem256_RC512Operand  : AsmOperandClass { let Name = "Mem256_RC512"; }
   def X86Mem512_RC512Operand  : AsmOperandClass { let Name = "Mem512_RC512"; }
 
   def X86SibMemOperand : AsmOperandClass { let Name = "SibMem"; }
 }
 
+let RenderMethod = "addMemOperands", SuperClasses = [X86Mem32AsmOperand] in {
+  def X86Mem32VEXAsmOperand  : AsmOperandClass { let Name = "Mem32VEX"; }
+}
+let RenderMethod = "addMemOperands", SuperClasses = [X86Mem64AsmOperand] in {
+  def X86Mem64VEXAsmOperand  : AsmOperandClass { let Name = "Mem64VEX"; }
+}
+
 def X86AbsMemAsmOperand : AsmOperandClass {
   let Name = "AbsMem";
   let SuperClasses = [X86MemAsmOperand];
 }
 
 class X86MemOperand<string printMethod,
           AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> {
   let PrintMethod = printMethod;

llvm/lib/Target/X86/X86InstrSSE.td

def rm_Int : SI<opc, MRMSrcMem, (outs DstRC:$dst),
                       asm#"{"#mem#"}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
                   []>, Sched<[sched.Folded, sched.ReadAfterFold]>;
 }
 }
 
 let Uses = [MXCSR], mayRaiseFPException = 1 in {
 let Predicates = [UseAVX] in {
 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, i32, v2f64,
-                  X86cvts2si, sdmem, sse_load_f64, "cvtsd2si",
+                  X86cvts2si, sdmem_vex, sse_load_f64, "cvtsd2si",
                   WriteCvtSD2I, SSEPackedDouble>, XD, VEX, VEX_LIG;
 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, i64, v2f64,
-                    X86cvts2si, sdmem, sse_load_f64, "cvtsd2si",
+                    X86cvts2si, sdmem_vex, sse_load_f64, "cvtsd2si",
                     WriteCvtSD2I, SSEPackedDouble>, XD, VEX, VEX_W, VEX_LIG;
 }
 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, i32, v2f64, X86cvts2si,
                  sdmem, sse_load_f64, "cvtsd2si", WriteCvtSD2I,
                  SSEPackedDouble>, XD;
 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, i64, v2f64, X86cvts2si,
                    sdmem, sse_load_f64, "cvtsd2si", WriteCvtSD2I,
                    SSEPackedDouble>, XD, REX_W;

 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
                 (CVTSI2SDrm_Int VR128:$dst, i32mem:$src), 0, "att">;
 
 /// SSE 1 Only
 
 // Aliases for intrinsics
 let Predicates = [UseAVX], Uses = [MXCSR], mayRaiseFPException = 1 in {
 defm VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, i32, v4f32, X86cvtts2Int,
-                                ssmem, sse_load_f32, "cvttss2si",
+                                ssmem_vex, sse_load_f32, "cvttss2si",
                                 WriteCvtSS2I, SSEPackedSingle>, XS, VEX, VEX_LIG;
 defm VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, i64, v4f32,
-                               X86cvtts2Int, ssmem, sse_load_f32,
+                               X86cvtts2Int, ssmem_vex, sse_load_f32,
                                "cvttss2si", WriteCvtSS2I, SSEPackedSingle>,
                                XS, VEX, VEX_LIG, VEX_W;
 defm VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, i32, v2f64, X86cvtts2Int,
-                                sdmem, sse_load_f64, "cvttsd2si",
+                                sdmem_vex, sse_load_f64, "cvttsd2si",
                                 WriteCvtSS2I, SSEPackedDouble>, XD, VEX, VEX_LIG;
 defm VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, i64, v2f64,
-                              X86cvtts2Int, sdmem, sse_load_f64,
+                              X86cvtts2Int, sdmem_vex, sse_load_f64,
                               "cvttsd2si", WriteCvtSS2I, SSEPackedDouble>,
                               XD, VEX, VEX_LIG, VEX_W;
 }
 let Uses = [MXCSR], mayRaiseFPException = 1 in {
 defm CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, i32, v4f32, X86cvtts2Int,
                                     ssmem, sse_load_f32, "cvttss2si",
                                     WriteCvtSS2I, SSEPackedSingle>, XS;
 defm CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, i64, v4f32,
                                    X86cvtts2Int, ssmem, sse_load_f32,
                                    "cvttss2si", WriteCvtSS2I, SSEPackedSingle>,
                                    XS, REX_W;
 defm CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, i32, v2f64, X86cvtts2Int,
                                     sdmem, sse_load_f64, "cvttsd2si",
                                     WriteCvtSD2I, SSEPackedDouble>, XD;
 defm CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, i64, v2f64,
                                   X86cvtts2Int, sdmem, sse_load_f64,
                                   "cvttsd2si", WriteCvtSD2I, SSEPackedDouble>,
                                   XD, REX_W;
 }
 
 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
                 (VCVTTSS2SIrr_Int GR32:$dst, VR128:$src), 0, "att">;
 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
-                (VCVTTSS2SIrm_Int GR32:$dst, f32mem:$src), 0, "att">;
+                (VCVTTSS2SIrm_Int GR32:$dst, ssmem_vex:$src), 0, "att">;
 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
                 (VCVTTSD2SIrr_Int GR32:$dst, VR128:$src), 0, "att">;
 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
-                (VCVTTSD2SIrm_Int GR32:$dst, f64mem:$src), 0, "att">;
+                (VCVTTSD2SIrm_Int GR32:$dst, sdmem_vex:$src), 0, "att">;
 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
                 (VCVTTSS2SI64rr_Int GR64:$dst, VR128:$src), 0, "att">;
 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
-                (VCVTTSS2SI64rm_Int GR64:$dst, f32mem:$src), 0, "att">;
+                (VCVTTSS2SI64rm_Int GR64:$dst, ssmem_vex:$src), 0, "att">;
 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
                 (VCVTTSD2SI64rr_Int GR64:$dst, VR128:$src), 0, "att">;
 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
-                (VCVTTSD2SI64rm_Int GR64:$dst, f64mem:$src), 0, "att">;
+                (VCVTTSD2SI64rm_Int GR64:$dst, sdmem_vex:$src), 0, "att">;
 
 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
                 (CVTTSS2SIrr_Int GR32:$dst, VR128:$src), 0, "att">;
 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
                 (CVTTSS2SIrm_Int GR32:$dst, f32mem:$src), 0, "att">;
 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
                 (CVTTSD2SIrr_Int GR32:$dst, VR128:$src), 0, "att">;
 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
                 (CVTTSD2SIrm_Int GR32:$dst, f64mem:$src), 0, "att">;
 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
                 (CVTTSS2SI64rr_Int GR64:$dst, VR128:$src), 0, "att">;
 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
                 (CVTTSS2SI64rm_Int GR64:$dst, f32mem:$src), 0, "att">;
 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
                 (CVTTSD2SI64rr_Int GR64:$dst, VR128:$src), 0, "att">;
 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
                 (CVTTSD2SI64rm_Int GR64:$dst, f64mem:$src), 0, "att">;
 
 let Predicates = [UseAVX], Uses = [MXCSR], mayRaiseFPException = 1 in {
 defm VCVTSS2SI   : sse12_cvt_sint<0x2D, VR128, GR32, i32, v4f32, X86cvts2si,
-                                  ssmem, sse_load_f32, "cvtss2si",
+                                  ssmem_vex, sse_load_f32, "cvtss2si",
                                   WriteCvtSS2I, SSEPackedSingle>, XS, VEX, VEX_LIG;
 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, i64, v4f32, X86cvts2si,
-                                  ssmem, sse_load_f32, "cvtss2si",
+                                  ssmem_vex, sse_load_f32, "cvtss2si",
                                   WriteCvtSS2I, SSEPackedSingle>, XS, VEX, VEX_W, VEX_LIG;
 }
 let Uses = [MXCSR], mayRaiseFPException = 1 in {
 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, i32, v4f32, X86cvts2si,
                                ssmem, sse_load_f32, "cvtss2si",
                                WriteCvtSS2I, SSEPackedSingle>, XS;
 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, i64, v4f32, X86cvts2si,
                                  ssmem, sse_load_f32, "cvtss2si",
defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, i128mem, v4f32, v4i32, memop,
                             SSEPackedSingle, WriteCvtI2PS>,
                             PS, Requires<[UseSSE2]>;
 }
 
 // AVX aliases
 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
                 (VCVTSS2SIrr_Int GR32:$dst, VR128:$src), 0, "att">;
 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
-                (VCVTSS2SIrm_Int GR32:$dst, ssmem:$src), 0, "att">;
+                (VCVTSS2SIrm_Int GR32:$dst, ssmem_vex:$src), 0, "att">;
 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
                 (VCVTSD2SIrr_Int GR32:$dst, VR128:$src), 0, "att">;
 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
-                (VCVTSD2SIrm_Int GR32:$dst, sdmem:$src), 0, "att">;
+                (VCVTSD2SIrm_Int GR32:$dst, sdmem_vex:$src), 0, "att">;
 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
                 (VCVTSS2SI64rr_Int GR64:$dst, VR128:$src), 0, "att">;
 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
-                (VCVTSS2SI64rm_Int GR64:$dst, ssmem:$src), 0, "att">;
+                (VCVTSS2SI64rm_Int GR64:$dst, ssmem_vex:$src), 0, "att">;
 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
                 (VCVTSD2SI64rr_Int GR64:$dst, VR128:$src), 0, "att">;
 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
-                (VCVTSD2SI64rm_Int GR64:$dst, sdmem:$src), 0, "att">;
+                (VCVTSD2SI64rm_Int GR64:$dst, sdmem_vex:$src), 0, "att">;
 
 // SSE aliases
 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
                 (CVTSS2SIrr_Int GR32:$dst, VR128:$src), 0, "att">;
 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
                 (CVTSS2SIrm_Int GR32:$dst, ssmem:$src), 0, "att">;
 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
                 (CVTSD2SIrr_Int GR32:$dst, VR128:$src), 0, "att">;

llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp

for (unsigned i = 0, e = EVEXInst->Operands.size(); i < e; i++) {
 
       if (OpRec1 == OpRec2)
         continue;
 
       if (isRegisterOperand(OpRec1) && isRegisterOperand(OpRec2)) {
         if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
           return false;
       } else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
+        if (OpRec1->getValueAsString("PrintMethod") != OpRec2->getValueAsString("PrintMethod"))
           return false;
       } else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
         if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type")) {
           return false;
         }
       } else
         return false;
     }
 

llvm/utils/TableGen/X86RecognizableInstr.cpp

OperandType RecognizableInstr::typeFromString(const std::string &s,
   TYPE("f128mem",             TYPE_M)
   TYPE("f256mem",             TYPE_M)
   TYPE("f512mem",             TYPE_M)
   TYPE("FR128",               TYPE_XMM)
   TYPE("FR64",                TYPE_XMM)
   TYPE("FR64X",               TYPE_XMM)
   TYPE("f64mem",              TYPE_M)
   TYPE("sdmem",               TYPE_M)
+  TYPE("sdmem_vex",           TYPE_M)
   TYPE("FR16X",               TYPE_XMM)
   TYPE("FR32",                TYPE_XMM)
   TYPE("FR32X",               TYPE_XMM)
   TYPE("f32mem",              TYPE_M)
   TYPE("f16mem",              TYPE_M)
   TYPE("ssmem",               TYPE_M)
+  TYPE("ssmem_vex",           TYPE_M)
   TYPE("shmem",               TYPE_M)
   TYPE("RST",                 TYPE_ST)
   TYPE("RSTi",                TYPE_ST)
   TYPE("i128mem",             TYPE_M)
   TYPE("i256mem",             TYPE_M)
   TYPE("i512mem",             TYPE_M)
   TYPE("i64i32imm_brtarget",  TYPE_REL)
   TYPE("i16imm_brtarget",     TYPE_REL)

 RecognizableInstr::memoryEncodingFromString(const std::string &s,
                                             uint8_t OpSize) {
   ENCODING("i16mem",          ENCODING_RM)
   ENCODING("i32mem",          ENCODING_RM)
   ENCODING("i64mem",          ENCODING_RM)
   ENCODING("i8mem",           ENCODING_RM)
   ENCODING("shmem",           ENCODING_RM)
   ENCODING("ssmem",           ENCODING_RM)
+  ENCODING("ssmem_vex",       ENCODING_RM)
   ENCODING("sdmem",           ENCODING_RM)
+  ENCODING("sdmem_vex",       ENCODING_RM)
   ENCODING("f128mem",         ENCODING_RM)
   ENCODING("f256mem",         ENCODING_RM)
   ENCODING("f512mem",         ENCODING_RM)
   ENCODING("f64mem",          ENCODING_RM)
   ENCODING("f32mem",          ENCODING_RM)
   ENCODING("f16mem",          ENCODING_RM)
   ENCODING("i128mem",         ENCODING_RM)
   ENCODING("i256mem",         ENCODING_RM)