[X86][Costmodel] Load/store i8 Stride=4 VF=4 interleaving costs

[lebedev.ri]

Summary

While we already model this tuple, the store cost is divergent from reality, so fix it.

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/1n4bPh7Tn - for intels Block RThroughput: =4.0; for ryzens, Block RThroughput: <=2.0
So pick cost of 4.

For store we have:
https://godbolt.org/z/r8K9sveqo - for intels Block RThroughput: =4.0; for ryzens, Block RThroughput: <=2.0
So pick cost of 4.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

[RKSimon]

LGTM

llvm/lib/Target/X86/X86TargetTransformInfo.cpp

static const CostTblEntry AVX2InterleavedStoreTbl[] = {
 
       {3, MVT::v2i8, 4},   // interleave 3 x 2i8 into 6i8 (and store)
       {3, MVT::v4i8, 4},   // interleave 3 x 4i8 into 12i8 (and store)
       {3, MVT::v8i8, 6},  // interleave 3 x 8i8 into 24i8 (and store)
       {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store)
       {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store)
 
       {4, MVT::v2i8, 4},  // interleave 4 x 2i8 into 8i8 (and store)
-      {4, MVT::v4i8, 9},   // interleave 4 x 4i8 into 16i8 (and store)
+      {4, MVT::v4i8, 4},   // interleave 4 x 4i8 into 16i8 (and store)
       {4, MVT::v8i8, 10},  // interleave 4 x 8i8 into 32i8 (and store)
       {4, MVT::v16i8, 10}, // interleave 4 x 16i8 into 64i8 (and store)
       {4, MVT::v32i8, 12}, // interleave 4 x 32i8 into 128i8 (and store)
 
       {4, MVT::v2i16, 2},  // interleave 4 x 2i16 into 8i16 (and store)
       {4, MVT::v4i16, 6},  // interleave 4 x 4i16 into 16i16 (and store)
       {4, MVT::v8i16, 10},  // interleave 4 x 8i16 into 32i16 (and store)
       {4, MVT::v16i16, 32},  // interleave 4 x 16i16 into 64i16 (and store)

llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-4.ll

 ; AVX1: LV: Found an estimated cost of 17 for VF 2 For instruction:   store i8 %v3, i8* %out3, align 1
 ; AVX1: LV: Found an estimated cost of 33 for VF 4 For instruction:   store i8 %v3, i8* %out3, align 1
 ; AVX1: LV: Found an estimated cost of 67 for VF 8 For instruction:   store i8 %v3, i8* %out3, align 1
 ; AVX1: LV: Found an estimated cost of 134 for VF 16 For instruction:   store i8 %v3, i8* %out3, align 1
 ; AVX1: LV: Found an estimated cost of 332 for VF 32 For instruction:   store i8 %v3, i8* %out3, align 1
 ;
 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction:   store i8 %v3, i8* %out3, align 1
 ; AVX2: LV: Found an estimated cost of 5 for VF 2 For instruction:   store i8 %v3, i8* %out3, align 1
-; AVX2: LV: Found an estimated cost of 10 for VF 4 For instruction:   store i8 %v3, i8* %out3, align 1
+; AVX2: LV: Found an estimated cost of 5 for VF 4 For instruction:   store i8 %v3, i8* %out3, align 1
 ; AVX2: LV: Found an estimated cost of 11 for VF 8 For instruction:   store i8 %v3, i8* %out3, align 1
 ; AVX2: LV: Found an estimated cost of 12 for VF 16 For instruction:   store i8 %v3, i8* %out3, align 1
 ; AVX2: LV: Found an estimated cost of 16 for VF 32 For instruction:   store i8 %v3, i8* %out3, align 1
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   store i8 %v3, i8* %out3, align 1
 ; AVX512: LV: Found an estimated cost of 11 for VF 2 For instruction:   store i8 %v3, i8* %out3, align 1
 ; AVX512: LV: Found an estimated cost of 11 for VF 4 For instruction:   store i8 %v3, i8* %out3, align 1
 ; AVX512: LV: Found an estimated cost of 11 for VF 8 For instruction:   store i8 %v3, i8* %out3, align 1