[libunwind] Fix cfi_register for float registers.

[danielkiss]

Summary

Fixes D110144.
registers.getFloatRegister is not const in ARM therefor can't be called here.

[mstorsjo]

Hmm, is there something fundamental in the change from D110144 that makes it unneeded on arm specifically? If that’s the case, this is probably fine.

[danielkiss]

Register in Register is not supported by EHABI and https://docs.microsoft.com/en-us/cpp/build/arm-exception-handling.
It is feasible by DWARF but I don't think it is used on arm.

[mstorsjo]

In D110731#3033683, @danielkiss wrote:

Register in Register is not supported by EHABI and https://docs.microsoft.com/en-us/cpp/build/arm-exception-handling.

Yeah, and this issue only arises in DwarfInstructions.hpp anyway, so it's confined to that case.

It is feasible by DWARF but I don't think it is used on arm.

Just to undestand the context on the original fix from D110144 - does anything automatically generate either of them (.cfi_undefined or .cfi_register) today, or is it only for handling cases with handwritten unwind info? Regarding "I don't think it is used on arm" - isn't it, in principle, just as plausible to want to use it in handwritten code on arm as it is on aarch64?

But I guess this change is fine. FWIW, dwarf on arm on windows is mostly a workaround since LLVM can't generate the proper windows arm unwind info (but it can for aarch64). And if I understand things correctly, Apple mostly uses sjlj on arm (except on armv7k, which is used on apple watch, where they do use dwarf/compact encoding).

[mstorsjo]

Adding the mailing list as subscriber, for visibility

[danielkiss]

As I know .cfi_undefined is not emitted and .cfi_register is emitted for general purpose registers only, while both appear in hand written assembly for floating point registers on aarch64.
It is possible to write assembly code that misses this support on arm with dwarf.

[mstorsjo]

In D110731#3035927, @danielkiss wrote:

As I know .cfi_undefined is not emitted and .cfi_register is emitted for general purpose registers only, while both appear in hand written assembly for floating point registers on aarch64.
It is possible to write assembly code that misses this support on arm with dwarf.

Ok, thanks for the clarification.

With that in mind I guess this approach is fine until there's a real need for that construct on arm, on a platform that uses dwarf then.

[mstorsjo]

Thanks!

libunwind/src/DwarfInstructions.hpp

double DwarfInstructions<A, R>::getSavedFloatRegister(
   switch (savedReg.location) {
   case CFI_Parser<A>::kRegisterInCFA:
     return addressSpace.getDouble(cfa + (pint_t)savedReg.value);
 
   case CFI_Parser<A>::kRegisterAtExpression:
     return addressSpace.getDouble(
         evaluateExpression((pint_t)savedReg.value, addressSpace,
                             registers, cfa));
-  case CFI_Parser<A>::kRegisterInRegister:
-    return registers.getFloatRegister((int)savedReg.value);
   case CFI_Parser<A>::kRegisterUndefined:
     return 0.0;
+  case CFI_Parser<A>::kRegisterInRegister:
+#ifndef _LIBUNWIND_TARGET_ARM
+    return registers.getFloatRegister((int)savedReg.value);
+#endif
   case CFI_Parser<A>::kRegisterIsExpression:
   case CFI_Parser<A>::kRegisterUnused:
   case CFI_Parser<A>::kRegisterOffsetFromCFA:
     // FIX ME
     break;
   }
   _LIBUNWIND_ABORT("unsupported restore location for float register");
 }