[X86][ISel] Lowering llvm.thread.pointer

[FreddyYe]

This patch is to align with gcc's behavior on __builtin_thread_pointer () on Linux. Example output of gcc: https://godbolt.org/z/9oTTW53qe
Related bugzilla of gcc: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96200, https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96955

[FreddyYe]

clean test.

[pengfei]

llvm/lib/Target/X86/X86ISelLowering.cpp

26770

X86::FS, X86::GS?

26772

Can we use this method directly? https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/CodeGen/MachineMemOperand.h#L63

26773

We don't use else after return.

26774

Not sure we have to limit it to Linux here. I found other targets don't do this check.
Besides, we already have check in https://github.com/llvm/llvm-project/blob/main/clang/lib/CodeGen/CGBuiltin.cpp#L5040
If we don't support tls, we won't go here. But if we do, we should return the right thread pointer.

llvm/test/CodeGen/X86/thread_pointer.ll

49

Do we have to use i64? Especially we are testing X32 and X86 at the same time.

[LuoYuanke]

llvm/lib/Target/X86/X86ISelLowering.cpp

26770

X86::FS, X86::GS?

Should be X86AS::FS and X86AS::GS.

26771

Not sure about the chain. It accesses memory.

llvm/test/CodeGen/X86/thread_pointer.ll

22

The first entry of the TLS store the pointer of itself. Right?

[FreddyYe]

Address comments.

[FreddyYe]

Address part of comments. Thanks for review.

llvm/lib/Target/X86/X86ISelLowering.cpp

26774

Yes. X86 supports TLS in many Targets. But what I'm sure is the ELF targets has defined thread pointer on document. See the last comment here: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96200

[pengfei]

llvm/lib/Target/X86/X86ISelLowering.cpp

26774

I think it makes sense to error out if we are not sure of it. Please add an error test, add fixme there and check x86_64-apple-darwin, x86_64-pc-windows etc.

[FreddyYe]

Address comments.

[pengfei]

LGTM, thanks.

llvm/lib/Target/X86/X86ISelLowering.cpp

case Intrinsic::x86_mmx_psrai_d: {
     // the sse2/mmx shift instructions reads 64 bits. Copy the 32 bits to an
     // MMX register.
     ShAmt = DAG.getNode(X86ISD::MMX_MOVW2D, DL, MVT::x86mmx, ShAmt);
     return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Op.getValueType(),
                        DAG.getTargetConstant(NewIntrinsic, DL,
                                              getPointerTy(DAG.getDataLayout())),
                        Op.getOperand(1), ShAmt);
   }
+  case Intrinsic::thread_pointer: {
+    if (Subtarget.isTargetELF()) {
+      SDLoc dl(Op);
+      EVT PtrVT = getPointerTy(DAG.getDataLayout());
+      // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
+      Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(
+          *DAG.getContext(), Subtarget.is64Bit() ? X86AS::FS : X86AS::GS));
+      return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
+                         DAG.getIntPtrConstant(0, dl), MachinePointerInfo(Ptr));
+    }
+    report_fatal_error(
+        "Target OS doesn't support __builtin_thread_pointer() yet.");
+  }
   }
 }
 
 static SDValue getAVX2GatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
                                  SDValue Src, SDValue Mask, SDValue Base,
                                  SDValue Index, SDValue ScaleOp, SDValue Chain,
                                  const X86Subtarget &Subtarget) {
   SDLoc dl(Op);

llvm/test/CodeGen/X86/thread_pointer-error.ll

+; FIXME: Targets below should support this builtin after they document the thread pointer for X86.
+; CHECK-ERROR: LLVM ERROR: Target OS doesn't support __builtin_thread_pointer() yet.
+
+; RUN: not --crash llc < %s -o /dev/null -mtriple=i686-pc-win32 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-pc-win32 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+; RUN: not --crash llc < %s -o /dev/null -mtriple=i686-pc-windows-gnu 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-pc-windows-gnu 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+; RUN: not --crash llc < %s -o /dev/null -mtriple=i686-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-pc-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+declare i8* @llvm.thread.pointer()
+
+define i8* @thread_pointer() nounwind {
+  %1 = tail call i8* @llvm.thread.pointer()
+  ret i8* %1
+}

llvm/test/CodeGen/X86/thread_pointer.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -mtriple=i386-linux-gnu | FileCheck %s --check-prefix=X86
+
+declare i8* @llvm.thread.pointer()
+
+define i8* @thread_pointer() nounwind {
+; X64-LABEL: thread_pointer:
+; X64:       # %bb.0:
+; X64-NEXT:    movq %fs:0, %rax
+; X64-NEXT:    retq
+;
+; X32-LABEL: thread_pointer:
+; X32:       # %bb.0:
+; X32-NEXT:    movl %fs:0, %eax
+; X32-NEXT:    retq
+;
+; X86-LABEL: thread_pointer:
+; X86:       # %bb.0:
+; X86-NEXT:    movl %gs:0, %eax
+; X86-NEXT:    retl
+  %1 = tail call i8* @llvm.thread.pointer()
+  ret i8* %1
+}
+
+define i32 @thread_pointer2(i32 %i) nounwind {
+; X64-LABEL: thread_pointer2:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    movslq %edi, %rax
+; X64-NEXT:    movl %fs:(,%rax,4), %eax
+; X64-NEXT:    retq
+;
+; X32-LABEL: thread_pointer2:
+; X32:       # %bb.0: # %entry
+; X32-NEXT:    movl %fs:0, %eax
+; X32-NEXT:    movl (%eax,%edi,4), %eax
+; X32-NEXT:    retq
+;
+; X86-LABEL: thread_pointer2:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl %gs:(,%eax,4), %eax
+; X86-NEXT:    retl
+entry:
+  %0 = tail call i8* @llvm.thread.pointer()
+  %1 = bitcast i8* %0 to i32*
+  %arrayidx = getelementptr inbounds i32, i32* %1, i32 %i
+  %2 = load i32, i32* %arrayidx, align 4
+  ret i32 %2
+}