[asan] Added TargetInstrInfo::isStackAdjustIntrinsic used to identify intrinsics, which adjust the stack when lowered to native.

[kstoimenov]

Summary

Used in the follow-up ASan patch to identify ASan intrinsics, which adjust the stack.

[eugenis]

I wonder if it is better to handle it through hasCopyImplyingStackAdjustment. This way it stays within the x86 target.

See how llvm::Intrinsic::x86_flags_write_u64 is done.

llvm/include/llvm/CodeGen/TargetInstrInfo.h

public:
   unsigned getReturnOpcode() const { return ReturnOpcode; }
 
   /// Returns the actual stack pointer adjustment made by an instruction
   /// as part of a call sequence. By default, only call frame setup/destroy
   /// instructions adjust the stack, but targets may want to override this
   /// to enable more fine-grained adjustment, or adjust by a different value.
   virtual int getSPAdjust(const MachineInstr &MI) const;
 
+  /// Returns true if the instruction is an intrinsic which will be lowered to
+  /// an natitive instruction manupulating the stack.
+  virtual bool isStackAdjustIntrinsic(const MachineInstr &MI) const {
+    return false;
+  }
+
   /// Return true if the instruction is a "coalescable" extension instruction.
   /// That is, it's like a copy where it's legal for the source to overlap the
   /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
   /// expected the pre-extension value is available as a subreg of the result
   /// register. This also returns the sub-register index in SubIdx.
   virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
                                      Register &DstReg, unsigned &SubIdx) const {
     return false;

llvm/lib/Target/X86/X86InstrInfo.h

else
       I.getOperand(1).setImm(V);
   }
 
   /// getSPAdjust - This returns the stack pointer adjustment made by
   /// this instruction. For x86, we need to handle more complex call
   /// sequences involving PUSHes.
   int getSPAdjust(const MachineInstr &MI) const override;
 
+  // On X86 platform returns true for instrinsics lowered to calls.
+  bool isStackAdjustIntrinsic(const MachineInstr &MI) const override;
+
   /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
   /// extension instruction. That is, it's like a copy where it's legal for the
   /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
   /// true, then it's expected the pre-extension value is available as a subreg
   /// of the result register. This also returns the sub-register index in
   /// SubIdx.
   bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
                              Register &DstReg, unsigned &SubIdx) const override;

llvm/lib/Target/X86/X86InstrInfo.cpp

int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
   case X86::PUSH64r:
   case X86::PUSH64rmm:
   case X86::PUSH64rmr:
   case X86::PUSH64i32:
     return 8;
   }
 }
 
+/// Returns true for the sanitizer access check as it will be lowered to
+// a call.
+bool X86InstrInfo::isStackAdjustIntrinsic(const MachineInstr &MI) const {
+  return MI.getOpcode() == X86::ASAN_CHECK_MEMACCESS;
+}
+
 /// Return true and the FrameIndex if the specified
 /// operand and follow operands form a reference to the stack frame.
 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
                                   int &FrameIndex) const {
   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
       MI.getOperand(Op + X86::AddrDisp).isImm() &&