[mips] Promote the result of SETCC nodes to GPR width.

[vkalintiris]

Summary

This patch modifies the existing comparison, branch, conditional-move
and select patterns, and adds new ones where needed. Also, the updated
SLT{u,i,iu} set of instructions generate a GPR width result.

The majority of the code changes in the Mips back-end fix the wrong
assumption that the result of SETCC nodes always produce an i32 value.
The changes in the common code path account for the fact that in 64-bit
MIPS targets, i1 is promoted to i32 instead of i64.

[vkalintiris]

Rebased.

[dsanders]

Sorry for taking so long to get to this one.

It's generally looking good. Most of my comments are nits, minor issues, and questions.

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

1164

This should probably be picking registers from FGRCC64 rather than FGRCC32.

lib/Target/Mips/Mips32r6InstrInfo.td

801–874

Just to make the patch a bit more readable: Could you separate the change to the multiclass style into another patch?

Also, indentation and unnecessary reordering. (the contents of Cmp_Pats used to be at the start of this hunk)

lib/Target/Mips/Mips64r6InstrInfo.td

78–79

This is because operands are still 32-bit instead of GPR-width, right?

109–110

ISA_MIPS32R6 and GPR_64 together is only possible for ISA_MIPS64R6.

I see that there are four pre-existing cases of ISA_MIPS32R6 in this file and they look like bugs to me.

111

Why codegen only?

113

FIELD_CMP_FORMAT_S should be FIELD_CMP_FORMAT_D

lib/Target/Mips/MipsCondMov.td

157–176

iPTR is i32 on N32 but mov[zn] is still a 64-bit move.

179–180

This can fit on one line. Similarly below

lib/Target/Mips/MipsISelLowering.cpp

638–639

I think this should be more general. E.g.:

if (SetCC.getValueType().getSizeInBits() > False.getValueType().getSizeInBits())
  SetCC = DAG.getNode(ISD::TRUNCATE, DL, False.getValueType, SetCC);

655–656

Likewise

1702–1703

I don't see the reason for this assert at the moment. Is it a requirement of createCMovFP()? If so, shouldn't it be asserted inside that function?

lib/Target/Mips/MipsRegisterInfo.td

393–394

'This class allows' -> 'These classes allow'

test/CodeGen/Mips/atomic.ll

351

Do you know why we still get this redundant sign extend? I was expecting it to disappear once the result type was i64.

test/CodeGen/Mips/cmov.ll

466–467

Is this still true?

test/CodeGen/Mips/countleading.ll

7

Well spotted

test/CodeGen/Mips/fcmp.ll

36

I think you're missing the signext attribute on the result of the function.

Likewise below

45

This one is doubly-redundant. cmp.eq.s produces GPR-width 0 and -1 and we're also about to zero-extend 1-bit to GPR-width. I'm surprised the latter reason didn't remove it.

test/CodeGen/Mips/llvm-ir/select.ll

158 ↗

(On Diff #34669)

Why remove this signext? Likewise below.

[vkalintiris]

WIP - Clean-up patch to make it diff-friendly.

[vkalintiris]

Addressed reviewer comments.

lib/Target/Mips/MipsISelLowering.cpp

1702–1703

I forgot to remove this before creating the review request. I wrote the assert when I was developing this patch because it fired in one case.

test/CodeGen/Mips/atomic.ll

351

In this case, it's a truncation from i64 to i32. There's a problem with RetCC_MipsN at the moment and we use V0 instead of V0_64. We'll have to fix this in a follow-up patch. The same is true for the rest of the truncations (SLLs) in rest of your questions.

test/CodeGen/Mips/cmov.ll

466–467

No, I added two new test cases.

[vkalintiris]

Rebased & fixed sel.{s,d} commands for microMIPS{32,64}r6.

[dsanders]

I think we're nearly there. Most of these are either minor issues or nits.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

14154

Looking at this again, I notice that getZExtOrTrunc() can only produce ZERO_EXTEND or TRUNCATE. We lose the getZeroExtendInReg() path. Could you bring back the special case?

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

990

Could you tell me which case made this necessary?

lib/Target/Mips/MicroMips64r6InstrInfo.td

144–146

Indentation

lib/Target/Mips/Mips64r6InstrInfo.td

78–79

This is because operands are still 32-bit instead of GPR-width, right?

Could you reply to this comment?

111

Naming nit: I think this should be 'Mips64r6' since these instruction definitions are not valid for Mips32r6.

116–117

80 cols?

lib/Target/Mips/MipsCondMov.td

267–276

This isn't quite right. iPTR is i32 for N32 but comparisons should produce i64.

291–293

This isn't quite right. iPTR is i32 for N32 but comparisons should produce i64.

lib/Target/Mips/MipsISelLowering.cpp

268–270

It ought to be based on the ABI rather than the architecture. Can you use MipsABIInfo::AreGprs64bit()?

469

It ought to be based on the ABI rather than the architecture. Can you use MipsABIInfo::AreGprs64bit()?

3956–3957

It ought to be based on the ABI rather than the architecture. Can you use MipsABIInfo::AreGprs64bit()?

lib/Target/Mips/MipsSEISelLowering.h

71–72 ↗

(On Diff #41639)

Did you mean to include this? There's no implementation.

test/CodeGen/Mips/atomic.ll

351

Ah ok. This is the problem you showed me last week where the N32 calling convention is being partially handled by the O32 implementation.

Do you think it's best to fix that before or after this patch?

test/CodeGen/Mips/llvm-ir/select.ll

158 ↗

(On Diff #41639)

Why remove this signext? Likewise below.

Could you reply to this comment?

[vkalintiris]

• Fix conditional-move patterns to use i64 comparisons on N32/N64 instead of iPTR.
• Restore PromoteIntOp_ANY_EXTEND() to its original state and solve the problem during DAG's building.
• Address a few other nits.

[vkalintiris]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

14154

With this input:

(select (i64 (setcc ...)), (i32 N1), (i32 N2))

We'll get SCC:i64 and Temp:i64. The ISD::SHL node below will try to create a shift operation with:

(i32 (shl i64, i32))

which is not valid. Given that the boolean contents are either all 0 or all 1, we can use getZextOrTrunc(), right?

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

990

The initial problem came from test/Codegen/atomic.ll:

t17: i8,i1,ch = AtomicCmpSwapWithSuccess<Volatile LDST1[%ptr]> t0, t2, t14, t16
  t18: i32 = any_extend t17:1
t20: ch,glue = CopyToReg t17:2, Register:i32 %V0, t18
t21: ch = MipsISD::Ret t20, Register:i32 %V0, t20:1

The boolean result of AtomicCmpSwapWithSuccess will be promoted to i64 by the call to GetPromotedInteger() in the previous line.

I decided to fix this by consulting getSetCCResultType() in the initial SelectionDAG builder when we construct an AtomicCmpSwapWithSuccess node.

lib/Target/Mips/Mips64r6InstrInfo.td

78–79

Sorry, I missed this. You're correct, that's why we have to use a custom inserter.

test/CodeGen/Mips/atomic.ll

351

I've already started writing the necessary patches in order to fix this. I believe it would be better to submit this patch first, and deal with the N32/N64 problem later.

test/CodeGen/Mips/llvm-ir/select.ll

158 ↗

(On Diff #41639)

Sorry, I missed this. I wanted to minimize the number of changes that I had to do in the test cases. The patch that fixes the N32/N64 ABI problem rewrites a lot of these tests and adds the signext back.

[vkalintiris]

Use getTypeToTransformTo() when the type from getSetCCResultType() is *not*
legal.

[dsanders]

Thanks for your patience on this, I think we're nearly there. Just a couple missed comments and a bit more on the removal of the ZERO_EXTEND_INREG case.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

14154

That's not what I'm getting at. Previously, we had two cases ZERO_EXTEND and ZERO_EXTEND_INREG. This patch adds the possibility of TRUNCATE which makes sense to me. However, it also changes the ZERO_EXTEND_INREG cases to ZERO_EXTEND and it's this removal that I don't understand.

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

990

Ok, that makes sense to me.

lib/Target/Mips/MicroMipsInstrInfo.td

674–678

Indentation (GPR32Opnd should line up with the ")

test/CodeGen/Mips/atomic.ll

351

Makes sense to me.

test/CodeGen/Mips/fcmp.ll

36

Could you comment on this?

45

Could you comment on this?

test/CodeGen/Mips/llvm-ir/select.ll

158 ↗

(On Diff #44856)

Ok then. I think answers one of my questions for that patch too.

[vkalintiris]

Rebase & addressed comments.

[vkalintiris]

test/CodeGen/Mips/fcmp.ll

36

My earlier comment covers both cases:

In this case, it's a truncation from i64 to i32. There's a problem with RetCC_MipsN at the moment and we use V0 instead of V0_64. We'll have to fix this in a follow-up patch. The same is true for the rest of the truncations (SLLs) in rest of your questions.

The aforementioned RetCC patch is in D16220.

[dsanders]

LGTM. Thanks for working on this.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (!LegalOperations ||
       // cast from setcc result type to select result type
       if (LegalTypes) {
         SCC  = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()),
                             N0, N1, CC);
         if (N2.getValueType().bitsLT(SCC.getValueType()))
           Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2),
                                         N2.getValueType());
         else
-          Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
-                             N2.getValueType(), SCC);
+          Temp = DAG.getZExtOrTrunc(SCC, SDLoc(N2), N2.getValueType());
       } else {
         SCC  = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
         Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
                            N2.getValueType(), SCC);
       }
 
       AddToWorklist(SCC.getNode());
       AddToWorklist(Temp.getNode());

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
   // use the new one.
   ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
   return Res;
 }
 
 /// Promote the overflow flag of an overflowing arithmetic node.
 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
   // Simply change the return type of the boolean result.
-  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
+  EVT NVT = getSetCCResultType(N->getValueType(1));
   EVT ValueVTs[] = { N->getValueType(0), NVT };
   SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
   SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
                             DAG.getVTList(ValueVTs), Ops);
 
   // Modified the sum result - switch anything that used the old sum to use
   // the new one.
   ReplaceValueWith(SDValue(N, 0), Res);
case ISD::SETLE:
     NewLHS = SExtPromotedInteger(NewLHS);
     NewRHS = SExtPromotedInteger(NewRHS);
     break;
   }
 }
 
 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
   SDValue Op = GetPromotedInteger(N->getOperand(0));
   return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
   SDValue Op2 = GetPromotedInteger(N->getOperand(2));
   return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
                        N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
                        N->getOrdering(), N->getSynchScope());
 }

lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

do {
     }
     // When recursively update nodes with new nodes, it is possible to have
     // new uses of From due to CSE. If this happens, replace the new uses of
     // From with To.
   } while (!From.use_empty());
 }
 
 void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {
-  assert(Result.getValueType() ==
-         TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
+  assert(((Result.getValueType() ==
+           TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType())) ||
+          (Result.getValueType() == getSetCCResultType(Op.getValueType()))) &&
          "Invalid type for promoted integer");
   AnalyzeNewValue(Result);
 
   SDValue &OpEntry = PromotedIntegers[Op];
   assert(!OpEntry.getNode() && "Node is already promoted!");
   OpEntry = Result;
 }
 

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
 
   SDValue OutChain = Gather.getValue(1);
   if (!ConstantMemory)
     PendingLoads.push_back(OutChain);
   setValue(&I, Gather);
 }
 
 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  LLVMContext &Ctx = *DAG.getContext();
+
   SDLoc dl = getCurSDLoc();
   AtomicOrdering SuccessOrder = I.getSuccessOrdering();
   AtomicOrdering FailureOrder = I.getFailureOrdering();
   SynchronizationScope Scope = I.getSynchScope();
 
   SDValue InChain = getRoot();
 
   MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
-  SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
+  EVT CCVT = TLI.getSetCCResultType(DAG.getDataLayout(), Ctx, MVT::i1);
+
+  // Only use the result of getSetCCResultType if it is legal,
+  // otherwise just use the promoted result type (NVT).
+  if (!TLI.isTypeLegal(CCVT))
+    CCVT = TLI.getTypeToTransformTo(Ctx, MVT::i1);
+
+  SDVTList VTs = DAG.getVTList(MemVT, CCVT, MVT::Other);
   SDValue L = DAG.getAtomicCmpSwap(
       ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
       getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
       getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
       /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
 
   SDValue OutChain = L.getValue(2);
 

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
                                            uint64_t Address,
                                            const void *Decoder);
 
 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
                                            unsigned RegNo,
                                            uint64_t Address,
                                            const void *Decoder);
 
-static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeFGRCC32RegisterClass(MCInst &Inst, unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder);
+
+static DecodeStatus DecodeFGRCC64RegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
                                                const void *Decoder);
 
 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
                                               unsigned Insn,
                                               uint64_t Address,
                                               const void *Decoder);
 
 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
                                               unsigned RegNo,
if (Result != MCDisassembler::Fail) {
       Size = 2;
       return Result;
     }
 
     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
     if (Result == MCDisassembler::Fail)
       return MCDisassembler::Fail;
 
+    if (hasMips32r6() && isGP64()) {
+      DEBUG(dbgs() << "Trying MicroMipsR6_GP64 table (32-bit instructions):\n");
+      // Calling the auto-generated decoder function.
+      Result = decodeInstruction(DecoderTableMicroMipsR6_GP6432, Instr, Insn,
+                                 Address, this, STI);
+      if (Result != MCDisassembler::Fail) {
+        Size = 4;
+        return Result;
+      }
+    }
+
     if (hasMips32r6()) {
       DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
       // Calling the auto-generated decoder function.
       Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
                                  this, STI);
       if (Result != MCDisassembler::Fail) {
         Size = 4;
         return Result;
Result =
         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
     if (Result != MCDisassembler::Fail) {
       Size = 4;
       return Result;
     }
   }
 
   if (hasMips32r6() && isGP64()) {
-    DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
-    Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
-                               Address, this, STI);
+    DEBUG(dbgs() << "Trying Mips64r6 (GPR64) table (32-bit opcodes):\n");
+    Result = decodeInstruction(DecoderTableMips64r632, Instr, Insn, Address,
+                               this, STI);
     if (Result != MCDisassembler::Fail) {
       Size = 4;
       return Result;
     }
   }
 
   if (hasMips32r6()) {
     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
                                            const void *Decoder) {
   if (RegNo > 7)
     return MCDisassembler::Fail;
   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodeFGRCC32RegisterClass(MCInst &Inst, unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+
+  unsigned Reg = getReg(Decoder, Mips::FGRCC32RegClassID, RegNo);
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeFGRCC64RegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
                                                const void *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
-  unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
+  unsigned Reg = getReg(Decoder, Mips::FGRCC64RegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeMem(MCInst &Inst,
                               unsigned Insn,
                               uint64_t Address,
                               const void *Decoder) {
   int Offset = SignExtend32<16>(Insn & 0xffff);
   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 
   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   if (Inst.getOpcode() == Mips::SC ||

lib/Target/Mips/MicroMips32r6InstrInfo.td

 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
                                              II_CVT>;
 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
                                              II_CVT>;
 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
                                              II_CVT>, FGR_64;
 
 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
-                       RegisterOperand FGROpnd> {
+                       RegisterOperand FGRCCOpnd, RegisterOperand FGROpnd> {
   def CMP_AF_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
-      CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"af", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_UN_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
-      CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"un", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_EQ_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
-      CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"eq", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_UEQ_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
-      CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"ueq", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_LT_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
-      CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"lt", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_ULT_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
-      CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"ult", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_LE_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
-      CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"le", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_ULE_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
-      CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"ule", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SAF_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
-      CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"saf", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SUN_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
-      CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"sun", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SEQ_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
-      CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"seq", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
-      CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"sueq", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SLT_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
-      CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"slt", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SULT_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
-      CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"sult", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SLE_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
-      CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"sle", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SULE_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
-      CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"sule", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
 }
 
 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
                              RegisterOperand SrcRC, InstrItinClass Itin,
                              SDPatternOperator OpNode = null_frag>
     : HARDFLOAT, NeverHasSideEffects {
   dag OutOperandList = (outs DstRC:$ft);
   dag InOperandList  = (ins SrcRC:$fs);
class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
                                                    FGR32Opnd, II_ROUND>;
 class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
                                                    FGR64Opnd, II_ROUND>;
 class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
                                                    FGR32Opnd, II_ROUND>;
 class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
                                                    FGR64Opnd, II_ROUND>;
 
-class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
-class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
+class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGRCC32Opnd, FGR32Opnd>;
+class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGRCC32Opnd, FGR64Opnd> {
   // We must insert a SUBREG_TO_REG around $fd_in
   bit usesCustomInserter = 1;
 }
 
 class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
 class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
 class SELENZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
 class SELENZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;

 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
                    ISA_MICROMIPS32R6;
-defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
-defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
+defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGRCC32Opnd, FGR32Opnd>;
+defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGRCC32Opnd, FGR64Opnd>;
 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
                      ISA_MICROMIPS32R6;
 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
                      ISA_MICROMIPS32R6;
 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
                      ISA_MICROMIPS32R6;

 def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
                      ISA_MICROMIPS32R6;
 def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
                      ISA_MICROMIPS32R6;
 def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
                      ISA_MICROMIPS32R6;
 def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,
                      ISA_MICROMIPS32R6;
-def SEL_S_MMR6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
-def SEL_D_MMR6 : StdMMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
+def SEL_S_MMR6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6,
+                 HARDFLOAT;
+def SEL_D_MMR6 : StdMMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6,
+                 HARDFLOAT;
 def SELEQZ_S_MMR6 : StdMMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
                     ISA_MICROMIPS32R6;
 def SELEQZ_D_MMR6 : StdMMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
                     ISA_MICROMIPS32R6;
 def SELENZ_S_MMR6 : StdMMR6Rel, SELENZ_S_MMR6_ENC, SELENZ_S_MMR6_DESC,
                     ISA_MICROMIPS32R6;
 def SELENZ_D_MMR6 : StdMMR6Rel, SELENZ_D_MMR6_ENC, SELENZ_D_MMR6_DESC,
                     ISA_MICROMIPS32R6;

lib/Target/Mips/MicroMips64r6InstrInfo.td

 class DMODU_MM64R6_DESC : ArithLogicR<"dmodu", GPR32Opnd>;
 
 class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32,
                                   uimm5_inssize_plus1, MipsIns>;
 class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>;
 class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1,
                                  MipsIns>;
 
+class SEL_S_MM64R6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGRCC64Opnd, FGR32Opnd> {
+  // We must copy FGRCC64Opnd's subreg into FGR32.
+  bit usesCustomInserter = 1;
+}
+class SEL_D_MM64R6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGRCC64Opnd, FGR64Opnd>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMipsR6" in {
   def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC,
                      ISA_MICROMIPS64R6;
   def DINSU_MM64R6: R6MMR6Rel, DINSU_MM64R6_DESC, DINSU_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
   def DINSM_MM64R6: R6MMR6Rel, DINSM_MM64R6_DESC, DINSM_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
   def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC,
                    ISA_MICROMIPS64R6;
 }
+
+let DecoderNamespace = "MicroMipsR6_GP64" in {
+def SEL_S_MM64R6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MM64R6_DESC,
+                   ISA_MICROMIPS64R6, HARDFLOAT;
+def SEL_D_MM64R6 : StdMMR6Rel, SEL_D_MMR6_ENC, SEL_D_MM64R6_DESC,
+                   ISA_MICROMIPS64R6, HARDFLOAT;
+}

lib/Target/Mips/MicroMipsInstrInfo.td

let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
   def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
                  COMPACT_BRANCH_FM_MM<0x5>;
 
   /// Arithmetic Instructions (ALU Immediate)
   def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
                  ADDI_FM_MM<0xc>;
   def ADDi_MM  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
                  ADDI_FM_MM<0x4>;
-  def SLTi_MM  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
-                 SLTI_FM_MM<0x24>;
-  def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
-                 SLTI_FM_MM<0x2c>;
+  def SLTi_MM  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd,
+                                GPR32Opnd>, SLTI_FM_MM<0x24>;
+  def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd,
+                                GPR32Opnd>, SLTI_FM_MM<0x2c>;
   def ANDi_MM  : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
                  ADDI_FM_MM<0x34>;
   def ORi_MM   : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
                  ADDI_FM_MM<0x14>;
   def XORi_MM  : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
                  ADDI_FM_MM<0x1c>;
   def LUi_MM   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM_MM;
 
   def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
                      LW_FM_MM<0xc>;
 
   /// Arithmetic Instructions (3-Operand, R-Type)
   def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
                  ADD_FM_MM<0, 0x150>;
   def SUBu_MM  : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
                  ADD_FM_MM<0, 0x1d0>;
   def MUL_MM   : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
   def ADD_MM   : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
   def SUB_MM   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
-  def SLT_MM   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
-  def SLTu_MM  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
+  def SLT_MM   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd, GPR32Opnd>,
+                 ADD_FM_MM<0, 0x350>;
+  def SLTu_MM  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd, GPR32Opnd>,
                  ADD_FM_MM<0, 0x390>;
   def AND_MM   : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
                  ADD_FM_MM<0, 0x250>;
   def OR_MM    : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
                  ADD_FM_MM<0, 0x290>;
   def XOR_MM   : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
                  ADD_FM_MM<0, 0x310>;
   def NOR_MM   : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;

lib/Target/Mips/Mips32r6InstrInfo.td

 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Multiclasses
 //
 //===----------------------------------------------------------------------===//
 
 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
-                          RegisterOperand FGROpnd,
+                          RegisterOperand FGRCCOpnd, RegisterOperand FGROpnd,
                           SDPatternOperator Op = null_frag> {
   dag OutOperandList = (outs FGRCCOpnd:$fd);
   dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
   string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
   list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
 }
 
-multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
-                     RegisterOperand FGROpnd>{
-  let AdditionalPredicates = [NotInMicroMips] in {
-    def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,
-                      CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>,
-                      ISA_MIPS32R6, HARDFLOAT;
-    def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
-                       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
-                       ISA_MIPS32R6, HARDFLOAT;
-    def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
-                       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,
-                       ISA_MIPS32R6, HARDFLOAT;
-    def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
-                        CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
-                        ISA_MIPS32R6, HARDFLOAT;
-    def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
-                       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>,
-                       ISA_MIPS32R6, HARDFLOAT;
-    def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
-                        CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
-                        ISA_MIPS32R6, HARDFLOAT;
-    def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
-                       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>,
-                       ISA_MIPS32R6, HARDFLOAT;
-    def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
-                        CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
-                        ISA_MIPS32R6, HARDFLOAT;
-    def CMP_SAF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SAF>,
-                        CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>,
-                        ISA_MIPS32R6, HARDFLOAT;
-    def CMP_SUN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUN>,
-                        CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>,
-                        ISA_MIPS32R6, HARDFLOAT;
-    def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
-                        CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
-                        ISA_MIPS32R6, HARDFLOAT;
-    def CMP_SUEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUEQ>,
-                         CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>,
-                         ISA_MIPS32R6, HARDFLOAT;
-    def CMP_SLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLT>,
-                        CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>,
-                        ISA_MIPS32R6, HARDFLOAT;
-    def CMP_SULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULT>,
-                         CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>,
-                         ISA_MIPS32R6, HARDFLOAT;
-    def CMP_SLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLE>,
-                        CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>,
-                        ISA_MIPS32R6, HARDFLOAT;
-    def CMP_SULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULE>,
-                         CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>,
-                         ISA_MIPS32R6, HARDFLOAT;
-  }
+multiclass CMP_CC_M<FIELD_CMP_FORMAT Format, string Typestr,
+                    RegisterOperand FGRCCOpnd, RegisterOperand FGROpnd>{
+                  CMP_CONDN_DESC_BASE<"af", Typestr, FGRCCOpnd, FGROpnd>,
+                   CMP_CONDN_DESC_BASE<"un", Typestr, FGRCCOpnd, FGROpnd,
+                                       setuo>, ISA_MIPS32R6, HARDFLOAT;
+                   CMP_CONDN_DESC_BASE<"eq", Typestr, FGRCCOpnd, FGROpnd,
+                                       setoeq>, ISA_MIPS32R6, HARDFLOAT;
+                    CMP_CONDN_DESC_BASE<"ueq", Typestr, FGRCCOpnd, FGROpnd,
+                                        setueq>, ISA_MIPS32R6, HARDFLOAT;
+                   CMP_CONDN_DESC_BASE<"lt", Typestr, FGRCCOpnd, FGROpnd,
+                                       setolt>, ISA_MIPS32R6, HARDFLOAT;
+                    CMP_CONDN_DESC_BASE<"ult", Typestr, FGRCCOpnd, FGROpnd,
+                                        setult>, ISA_MIPS32R6, HARDFLOAT;
+                   CMP_CONDN_DESC_BASE<"le", Typestr, FGRCCOpnd, FGROpnd,
+                                       setole>, ISA_MIPS32R6, HARDFLOAT;
+                    CMP_CONDN_DESC_BASE<"ule", Typestr, FGRCCOpnd, FGROpnd,
+                                        setule>, ISA_MIPS32R6, HARDFLOAT;
+                    CMP_CONDN_DESC_BASE<"saf", Typestr, FGRCCOpnd, FGROpnd>,
+                    CMP_CONDN_DESC_BASE<"sun", Typestr, FGRCCOpnd, FGROpnd>,
+                    CMP_CONDN_DESC_BASE<"seq", Typestr, FGRCCOpnd, FGROpnd>,
+                     CMP_CONDN_DESC_BASE<"sueq", Typestr, FGRCCOpnd, FGROpnd>,
+                    CMP_CONDN_DESC_BASE<"slt", Typestr, FGRCCOpnd, FGROpnd>,
+                     CMP_CONDN_DESC_BASE<"sult", Typestr, FGRCCOpnd, FGROpnd>,
+                    CMP_CONDN_DESC_BASE<"sle", Typestr, FGRCCOpnd, FGROpnd>,
+                     CMP_CONDN_DESC_BASE<"sule", Typestr, FGRCCOpnd, FGROpnd>,
 }
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
   list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
 }
 
 class MUH_DESC    : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
 class MUHU_DESC   : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
 class MULU_DESC   : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
 
-class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
+class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGRCCOpnd,
+                         RegisterOperand FGROpnd> {
   dag OutOperandList = (outs FGROpnd:$fd);
   dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
   list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in,
                                                  FGROpnd:$ft,
                                                  FGROpnd:$fs))];
   string Constraints = "$fd_in = $fd";
 }
 
-class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
+class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGRCC32Opnd, FGR64Opnd> {
   // We must insert a SUBREG_TO_REG around $fd_in
   bit usesCustomInserter = 1;
 }
-class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
+
+class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGRCC32Opnd, FGR32Opnd>;
 
 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
     : MipsR6Arch<instr_asm> {
   dag OutOperandList = (outs GPROpnd:$rd);
   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
   list<dag> Pattern = [];
 }

 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
 def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
 let AdditionalPredicates = [NotInMicroMips] in {
   def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT;
 }
 def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
 def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
-defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
-defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
+defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGRCC32Opnd, FGR32Opnd>;
+defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGRCC32Opnd, FGR64Opnd>;
 def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
 def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
 def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
 def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
 def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
 def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
 def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;

 def : MipsPat<(setne VT:$lhs, VT:$rhs),
       (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
 }
 
 defm S : Cmp_Pats<f32, NOR, ZERO>, ISA_MIPS32R6;
 defm D : Cmp_Pats<f64, NOR, ZERO>, ISA_MIPS32R6;
 
 // i32 selects
 multiclass SelectInt_Pats<ValueType RC, Instruction OROp, Instruction XORiOp,
                           Instruction SLTiOp, Instruction SLTiuOp,
                           Instruction SELEQZOp, Instruction SELNEZOp,
                           SDPatternOperator imm_type, ValueType Opg> {
 // reg, immz
 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, RC:$f),
               (OROp (SELEQZOp RC:$t, RC:$cond), (SELNEZOp RC:$f, RC:$cond))>;
 def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, RC:$f),
               (OROp (SELNEZOp RC:$t, RC:$cond), (SELEQZOp RC:$f, RC:$cond))>;
 
 // reg, immZExt16[_64]
 def : MipsPat<(select (Opg (seteq RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
               (OROp (SELEQZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
                     (SELNEZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
 def : MipsPat<(select (Opg (setne RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
               (OROp (SELNEZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
                     (SELEQZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
 
 // reg, immSExt16Plus1
 def : MipsPat<(select (Opg (setgt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f),
               (OROp (SELEQZOp RC:$t, (SLTiOp RC:$cond, (Plus1 imm:$imm))),
                     (SELNEZOp RC:$f, (SLTiOp RC:$cond, (Plus1 imm:$imm))))>;
 def : MipsPat<(select (Opg (setugt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f),
               (OROp (SELEQZOp RC:$t, (SLTiuOp RC:$cond, (Plus1 imm:$imm))),
                     (SELNEZOp RC:$f, (SLTiuOp RC:$cond, (Plus1 imm:$imm))))>;
 
 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, immz),
               (SELEQZOp RC:$t, RC:$cond)>;
 def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, immz),
               (SELNEZOp RC:$t, RC:$cond)>;
 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), immz, RC:$f),
               (SELNEZOp RC:$f, RC:$cond)>;
 def : MipsPat<(select (Opg (setne RC:$cond, immz)), immz, RC:$f),
               (SELEQZOp RC:$f, RC:$cond)>;
 }
 
 defm : SelectInt_Pats<i32, OR, XORi, SLTi, SLTiu, SELEQZ, SELNEZ,
                       immZExt16, i32>, ISA_MIPS32R6;
 
 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
               (OR (SELNEZ i32:$t, i32:$cond),
                   (SELEQZ i32:$f, i32:$cond))>,
               ISA_MIPS32R6;
 def : MipsPat<(select i32:$cond, i32:$t, immz),
               (SELNEZ i32:$t, i32:$cond)>,
               ISA_MIPS32R6;
 def : MipsPat<(select i32:$cond, immz, i32:$f),
               (SELEQZ i32:$f, i32:$cond)>,
               ISA_MIPS32R6;

lib/Target/Mips/Mips64InstrInfo.td

 /// Arithmetic Instructions (ALU Immediate)
 def DADDi   : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
               ISA_MIPS3_NOT_32R6_64R6;
 def DADDiu  : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
                           immSExt16, add>,
               ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
 
 let isCodeGenOnly = 1 in {
-def SLTi64  : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
-              SLTI_FM<0xa>;
-def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
-              SLTI_FM<0xb>;
+def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd,
+                     GPR64Opnd>, SLTI_FM<0xa>;
+def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd,
+                      GPR64Opnd>, SLTI_FM<0xb>;
+def SLTi64_32 : SetCC_I<"slti", setlt, simm16, immSExt16, GPR64Opnd,
+                        GPR32Opnd>, SLTI_FM<0xa>;
+def SLTiu64_32 : SetCC_I<"sltiu", setult, simm16, immSExt16, GPR64Opnd,
+                         GPR32Opnd>, SLTI_FM<0xb>;
 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
              ADDI_FM<0xc>;
 def ORi64   : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
               ADDI_FM<0xd>;
 def XORi64  : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
               ADDI_FM<0xe>;
 def LUi64   : LoadUpper<"lui", GPR64Opnd, uimm16_64_relaxed>, LUI_FM;
 }
 
 /// Arithmetic Instructions (3-Operand, R-Type)
 def DADD   : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
              ISA_MIPS3;
 def DADDu  : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>,
              ISA_MIPS3;
 def DSUBu  : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
              ISA_MIPS3;
 def DSUB   : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
              ISA_MIPS3;
 
 let isCodeGenOnly = 1 in {
-def SLT64  : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
-def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
+def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd, GPR64Opnd>, ADD_FM<0, 0x2a>;
+def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd, GPR64Opnd>, ADD_FM<0, 0x2b>;
+def SLT64_32 : SetCC_R<"slt", setlt, GPR64Opnd, GPR32Opnd>, ADD_FM<0, 0x2a>;
+def SLTu64_32 : SetCC_R<"sltu", setult, GPR64Opnd, GPR32Opnd>, ADD_FM<0, 0x2b>;
 def AND64  : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
 def OR64   : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
 def XOR64  : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
 def NOR64  : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
 }
 
 /// Shift Instructions
 def DSLL   : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
          [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
          NoItinerary, FrmR, opstr> {
   let TwoOperandAliasConstraint = "$rt = $rs";
 }
 
 class SetCC64_R<string opstr, PatFrag cond_op> :
   InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
          !strconcat(opstr, "\t$rd, $rs, $rt"),
-         [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs,
-                                             GPR64Opnd:$rt)))],
+         [(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],
          II_SEQ_SNE, FrmR, opstr> {
   let TwoOperandAliasConstraint = "$rd = $rs";
 }
 
 class SetCC64_I<string opstr, PatFrag cond_op>:
   InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
          !strconcat(opstr, "\t$rt, $rs, $imm10"),
-         [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,
-                                             immSExt10_64:$imm10)))],
+         [(set GPR64Opnd:$rt, (cond_op GPR64Opnd:$rs, immSExt10_64:$imm10))],
          II_SEQI_SNEI, FrmI, opstr> {
   let TwoOperandAliasConstraint = "$rt = $rs";
 }
 
 class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op,
                     RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> :
   InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset),
          !strconcat(opstr, "\t$rs, $p, $offset"),
-         [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
+         [(brcond (i64 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
                   bb:$offset)], II_BBIT, FrmI, opstr> {
   let isBranch = 1;
   let isTerminator = 1;
   let hasDelaySlot = 1;
   let Defs = [AT];
 }
 
 class MFC2OP<string asmstr, RegisterOperand RO> :

 
 def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
 def : WrapperPat<tconstpool, DADDiu, GPR64>;
 def : WrapperPat<texternalsym, DADDiu, GPR64>;
 def : WrapperPat<tblockaddress, DADDiu, GPR64>;
 def : WrapperPat<tjumptable, DADDiu, GPR64>;
 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
 
-defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
-                  ZERO_64>;
+defm : BrcondPats1<GPR64, BEQ64, BNE64, ZERO_64, i64>;
+defm : BrcondPats1<GPR32, BEQ, BNE, ZERO, i64>;
 
-def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
+def : MipsPat<(brcond (i64 (setlt i64:$lhs, 1)), bb:$dst),
               (BLEZ64 i64:$lhs, bb:$dst)>;
-def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
+def : MipsPat<(brcond (i64 (setgt i64:$lhs, -1)), bb:$dst),
               (BGEZ64 i64:$lhs, bb:$dst)>;
+def : MipsPat<(brcond (i64 (setlt i32:$lhs, 1)), bb:$dst),
+              (BLEZ64 (SUBREG_TO_REG (i32 0), i32:$lhs, sub_32), bb:$dst)>;
+def : MipsPat<(brcond (i64 (setgt i32:$lhs, -1)), bb:$dst),
+              (BGEZ64 (SUBREG_TO_REG (i32 0), i32:$lhs, sub_32), bb:$dst)>;
 
 // setcc patterns
 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
-defm : SetlePats<GPR64, SLT64, SLTu64>;
+defm : SetlePats<GPR64, SLT64, SLTu64, XORi64>;
 defm : SetgtPats<GPR64, SLT64, SLTu64>;
-defm : SetgePats<GPR64, SLT64, SLTu64>;
-defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
+defm : SetgePats<GPR64, SLT64, SLTu64, XORi64>;
+defm : SetgeImmPats<GPR64, SLTi64, SLTiu64, XORi64>;
+
+defm : SeteqPats<GPR32, SLTiu64_32, XOR, SLTu64_32, ZERO>;
+defm : SetlePats<GPR32, SLT64_32, SLTu64_32, XORi64>;
+defm : SetgtPats<GPR32, SLT64_32, SLTu64_32>;
+defm : SetgePats<GPR32, SLT64_32, SLTu64_32, XORi64>;
+defm : SetgeImmPats<GPR32, SLTi64_32, SLTiu64_32, XORi64>;
 
 // truncate
 def : MipsPat<(trunc (assertsext GPR64:$src)),
               (EXTRACT_SUBREG GPR64:$src, sub_32)>;
 def : MipsPat<(trunc (assertzext GPR64:$src)),
               (EXTRACT_SUBREG GPR64:$src, sub_32)>;
 def : MipsPat<(i32 (trunc GPR64:$src)),
               (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
let AdditionalPredicates = [NotDSP] in {
   def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
                 (DADDu GPR64:$lhs, GPR64:$rhs)>;
   def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
                 (DADDiu GPR64:$lhs, imm:$imm)>;
 }
 
 // Octeon bbit0/bbit1 MipsPattern
 let Predicates = [HasMips64, HasCnMips] in {
-def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
+def : MipsPat<(brcond (i64 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
               (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;
-def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
+def : MipsPat<(brcond (i64 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
               (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
-def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
+def : MipsPat<(brcond (i64 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
               (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;
-def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
+def : MipsPat<(brcond (i64 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
               (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
 }
 
 // Atomic load patterns.
 def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>;
 def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>;
 def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>;
 def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>;

lib/Target/Mips/Mips64r6InstrInfo.td

 class DMUHU_DESC   : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, mulhu>;
 class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, mul>;
 class DMULU_DESC   : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>;
 class LDPC_DESC    : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
 class LLD_R6_DESC   : LL_R6_DESC_BASE<"lld", GPR64Opnd>;
 class SCD_R6_DESC   : SC_R6_DESC_BASE<"scd", GPR64Opnd>;
 class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
 class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
+class SEL64_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGRCC64Opnd, FGR32Opnd> {
+  // We must copy FGRCC64Opnd's subreg into FGR32.
+  bit usesCustomInserter = 1;
+}
+class SEL64_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGRCC64Opnd, FGR64Opnd>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let AdditionalPredicates = [NotInMicroMips] in {

 def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
 def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
 def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
 def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
 def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
-def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
-def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
-let DecoderNamespace = "Mips32r6_64r6_GP64" in {
-  def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
-  def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
+def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
+def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS64R6;
+let AdditionalPredicates = [NotInMicroMips],
+    DecoderNamespace = "Mips64r6" in {
+  def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS64R6;
+  def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS64R6;
+  def SEL64_S : SEL_S_ENC, SEL64_S_DESC, ISA_MIPS64R6, HARDFLOAT;
+  def SEL64_D : SEL_D_ENC, SEL64_D_DESC, ISA_MIPS64R6, HARDFLOAT;
+  defm S64: CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGRCC64Opnd, FGR32Opnd>,
+            ISA_MIPS64R6;
+  defm D64: CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGRCC64Opnd, FGR64Opnd>,
+            ISA_MIPS64R6;
 }
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Aliases
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
 
 //===----------------------------------------------------------------------===//
 //
 // Patterns and Pseudo Instructions
 //
 //===----------------------------------------------------------------------===//
 
-// i64 selects
-def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$t, i64:$cond),
-                    (SELEQZ64 i64:$f, i64:$cond))>,
-              ISA_MIPS64R6;
-def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
-              (OR64 (SELEQZ64 i64:$t, i64:$cond),
-                    (SELNEZ64 i64:$f, i64:$cond))>,
-              ISA_MIPS64R6;
-def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
+// comparisons supported via another comparison
+defm S64: Cmp_Pats<f32, NOR64, ZERO_64>, ISA_MIPS64R6;
+defm D64: Cmp_Pats<f64, NOR64, ZERO_64>, ISA_MIPS64R6;
+
+// i32 selects
+defm : SelectInt_Pats<i32, OR, XORi, SLTi, SLTiu, SELEQZ, SELNEZ,
+                      immZExt16, i64>, ISA_MIPS64R6;
+
+def : MipsPat<(select i64:$cond, i32:$t, i32:$f),
+              (OR (SELNEZ i32:$t, (EXTRACT_SUBREG i64:$cond, sub_32)),
+                  (SELEQZ i32:$f, (EXTRACT_SUBREG i64:$cond, sub_32)))>,
+      ISA_MIPS64R6;
+def : MipsPat<(select i64:$cond, i32:$t, immz),
+              (SELNEZ i32:$t, (EXTRACT_SUBREG i64:$cond, sub_32))>,
+def : MipsPat<(select i64:$cond, immz, i32:$f),
+              (SELEQZ i32:$f, (EXTRACT_SUBREG i64:$cond, sub_32))>,
+
+// i64 selects
+defm : SelectInt_Pats<i64, OR64, XORi64, SLTi64, SLTiu64, SELEQZ64, SELNEZ64,
+                      immZExt16_64, i64>, ISA_MIPS64R6;
+
+def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
               (OR64 (SELNEZ64 i64:$t, i64:$cond),
                     (SELEQZ64 i64:$f, i64:$cond))>,
-              ISA_MIPS64R6;
-def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
-              (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
-                    (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
-              ISA_MIPS64R6;
-def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
-                    (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
-              ISA_MIPS64R6;
-def : MipsPat<
-  (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
-  (OR64 (SELEQZ64 i64:$t,
-                  (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
-                                 sub_32)),
-        (SELNEZ64 i64:$f,
-                  (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
-                                 sub_32)))>,
-  ISA_MIPS64R6;
-def : MipsPat<
-  (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
-  (OR64 (SELEQZ64 i64:$t,
-                  (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
-                                 sub_32)),
-        (SELNEZ64 i64:$f,
-                  (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
-                                 sub_32)))>,
-  ISA_MIPS64R6;
-
-def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
-              (SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
-def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
-              (SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
-def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
-              (SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
-def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
-              (SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
 
 // i64 selects from an i32 comparison
-// One complicating factor here is that bits 32-63 of an i32 are undefined.
-// FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
-//        This would allow us to remove the sign-extensions here.
 def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
-                    (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
-              ISA_MIPS64R6;
-def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
-              (OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),
-                    (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,
-              ISA_MIPS64R6;
-def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
-                    (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
-              ISA_MIPS64R6;
-def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
-              (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
-                                                      immZExt16:$imm))),
-                    (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
-                                                      immZExt16:$imm))))>,
-              ISA_MIPS64R6;
-def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
-                                                      immZExt16:$imm))),
-                    (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
-                                                      immZExt16:$imm))))>,
-              ISA_MIPS64R6;
+def : MipsPat<(select (i64 (seteq i32:$cond, immz)), i64:$t, i64:$f),
+def : MipsPat<(select (i64 (setne i32:$cond, immz)), i64:$t, i64:$f),
+def : MipsPat<(select (i64 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
+      (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond, immZExt16:$imm))),
+            (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond, immZExt16:$imm))))>,
+      ISA_MIPS64R6;
+def : MipsPat<(select (i64 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
+      (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond, immZExt16:$imm))),
+            (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond, immZExt16:$imm))))>,
 
 def : MipsPat<(select i32:$cond, i64:$t, immz),
               (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
-              ISA_MIPS64R6;
-def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),
+def : MipsPat<(select (i64 (setne i32:$cond, immz)), i64:$t, immz),
               (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
-              ISA_MIPS64R6;
-def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),
+def : MipsPat<(select (i64 (seteq i32:$cond, immz)), i64:$t, immz),
               (SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,
-              ISA_MIPS64R6;
 def : MipsPat<(select i32:$cond, immz, i64:$f),
               (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
-              ISA_MIPS64R6;
-def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
+def : MipsPat<(select (i64 (setne i32:$cond, immz)), immz, i64:$f),
               (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
-              ISA_MIPS64R6;
-def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
+def : MipsPat<(select (i64 (seteq i32:$cond, immz)), immz, i64:$f),
               (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,
-              ISA_MIPS64R6;

lib/Target/Mips/MipsCondMov.td

class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
                   SDPatternOperator OpNode = null_frag> :
   InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
          !strconcat(opstr, "\t$fd, $fs, $fcc"),
          [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
          Itin, FrmFR, opstr>, HARDFLOAT {
   let Constraints = "$F = $fd";
 }
 
-// select patterns
-multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
-                     Instruction MOVZInst, Instruction SLTOp,
-                     Instruction SLTuOp, Instruction SLTiOp,
-                     Instruction SLTiuOp> {
-  def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
-                (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
-  def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
-                (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
-  def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
-                (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
-  def : MipsPat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
-                (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
-  def : MipsPat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
-                (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
-  def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
-                (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
-  def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)),
-                        DRC:$T, DRC:$F),
-                (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>;
-  def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)),
-                        DRC:$T, DRC:$F),
-                (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)),
-                          DRC:$F)>;
-}
-
-multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
-                     Instruction MOVZInst, Instruction XOROp> {
-  def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
-                (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
-  def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
-                (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
-}
-
-multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
-                     Instruction MOVZInst, Instruction XORiOp> {
-  def : MipsPat<
-            (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
-            (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
-}
-
-multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
-                    Instruction XOROp> {
-  def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
-                (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
-  def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
-                (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
-  def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
-                (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
-}
-
 // Instantiation of instructions.
 def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>,
                ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
 
 let isCodeGenOnly = 1 in {
   def MOVZ_I_I64   : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>,
                      ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
   def MOVZ_I64_I   : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>,

 
 let DecoderNamespace = "Mips64" in {
   def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
                  CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
   def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
                  CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
 }
 
-// Instantiation of conditional move patterns.
-defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
+// select patterns
+multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
+                     Instruction MOVZInst, Instruction SLTOp,
+                     Instruction SLTuOp, Instruction SLTiOp,
+                     Instruction SLTiuOp, ValueType VT> {
+// reg, reg
+def : MipsPat<(select (VT (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
+              (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
+def : MipsPat<(select (VT (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
+              (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
+def : MipsPat<(select (VT (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
+              (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
+def : MipsPat<(select (VT (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
+              (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
+
+// reg, imm
+def : MipsPat<(select (VT (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
+              (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
+def : MipsPat<(select (VT (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
+              (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
+def : MipsPat<
+        (select (VT (setgt CRC:$lhs, immSExt16Plus1:$rhs)), DRC:$T, DRC:$F),
+        (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>;
+def : MipsPat<
+        (select (VT (setugt CRC:$lhs, immSExt16Plus1:$rhs)), DRC:$T, DRC:$F),
+        (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>;
+}
+
+// We have to wrap the instantiation of the MovzPats0 patterns in another
+// multiclass that specifies the result type of the SETCC nodes. The patterns
+// with VT=i64 (or i32) will be ignored when GPR-width=i32 (or i64).
+multiclass MovzPats0_SuperClass<ValueType VT> {
+defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu, VT>,
        INSN_MIPS4_32_NOT_32R6_64R6;
-defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
-defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>, INSN_MIPS4_32_NOT_32R6_64R6;
+defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu, VT>,
+       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
+defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu, VT>,
+       INSN_MIPS4_32_NOT_32R6_64R6;
+defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu, VT>,
+       INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
+defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu, VT>,
+       INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
 
-defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
+defm : MovzPats0<GPR32, GPR32, MOVZ_I64_I, SLT64_32, SLTu64_32, SLTi64_32,
+                 SLTiu64_32, VT>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
+defm : MovzPats0<GPR32, GPR64, MOVZ_I64_I64, SLT64_32, SLTu64_32, SLTi64_32,
+                 SLTiu64_32, VT>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
+defm : MovzPats0<GPR32, FGR32, MOVZ_I64_S, SLT64_32, SLTu64_32, SLTi64_32,
+                 SLTiu64_32, VT>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
+defm : MovzPats0<GPR32, FGR64, MOVZ_I64_D64, SLT64_32, SLTu64_32, SLTi64_32,
+                 SLTiu64_32, VT>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64, FGR_64;
+
+defm : MovzPats0<GPR64, GPR32, MOVZ_I64_I, SLT64, SLTu64, SLTi64, SLTiu64, VT>,
        INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
-defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,
+defm : MovzPats0<GPR64, GPR64, MOVZ_I64_I64, SLT64, SLTu64, SLTi64, SLTiu64, VT>,
        INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
-defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>,
+defm : MovzPats0<GPR64, FGR32, MOVZ_I64_S, SLT64, SLTu64, SLTi64, SLTiu64, VT>,
        INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
-defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
+defm : MovzPats0<GPR64, FGR64, MOVZ_I64_D64, SLT64, SLTu64, SLTi64, SLTiu64, VT>,
+       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64, FGR_64;
+}
+
+defm : MovzPats0_SuperClass<i32>;
+defm : MovzPats0_SuperClass<i64>;
+
+multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
+                     Instruction MOVZInst, Instruction XOROp, ValueType VT> {
+def : MipsPat<(select (VT (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
+              (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
+def : MipsPat<(select (VT (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
+              (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
+}
+
+multiclass MovzPats1_SuperClass<ValueType VT> {
+defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR, VT>, INSN_MIPS4_32_NOT_32R6_64R6;
+defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR, VT>,
        INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
-defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,
+defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR, VT>, INSN_MIPS4_32_NOT_32R6_64R6;
+defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR, VT>,
+       INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
+defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR, VT>,
+       INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
+
+defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64, VT>,
+       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
+defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64, VT>,
        INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
-defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>,
+defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64, VT>,
        INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
-defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,
+defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64, VT>,
+       INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
+}
+
+defm : MovzPats1_SuperClass<i32>;
+defm : MovzPats1_SuperClass<i64>;
+
+multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
+                     Instruction MOVZInst, Instruction XORiOp, ValueType VT> {
+def : MipsPat<
+    (select (VT (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
+    (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
+}
+
+multiclass MovzPats2_SuperClass<ValueType VT> {
+defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi, VT>, INSN_MIPS4_32_NOT_32R6_64R6;
+defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi, VT>,
        INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
-defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,
+defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64, VT>,
        INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
-defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>,
+defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64, VT>,
        INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
+}
 
-defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
+defm : MovzPats2_SuperClass<i32>;
+defm : MovzPats2_SuperClass<i64>;
 
-defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
-       GPR_64;
-defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
-       GPR_64;
-defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
-       GPR_64;
+multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
+                    Instruction XOROp, ValueType VT = i32> {
+  def : MipsPat<(select (VT (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
+                (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
+  def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
+                (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
+  def : MipsPat<(select (VT (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
+                (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
+}
 
-defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
-       INSN_MIPS4_32_NOT_32R6_64R6;
-defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
+defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
 defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
+defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
+       FGR_32;
+defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
+       FGR_64;
 
-defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>,
-       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
-defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
+defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR, i64>, INSN_MIPS4_32_NOT_32R6_64R6,
        GPR_64;
-defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
+defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR, i64>,
+       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
+defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR, i64>, INSN_MIPS4_32_NOT_32R6_64R6,
        GPR_64;
-
-defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
+defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR, i64>,
        INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
-defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
-       FGR_32;
-defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
-       FGR_32;
+defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR, i64>,
+       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64, FGR_64;
 
-defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
-       INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
-defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64, SLTiu64>,
-       INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
-defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
-       FGR_64;
-defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>,
-       INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
-defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
-       FGR_64;
-defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
-       FGR_64;
+defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64, i64>,
+       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
+defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64, i64>,
+       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
+defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64, i64>,
+       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
+defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64, i64>,
+       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64, FGR_64;
 
 // For targets that don't have conditional-move instructions
 // we have to match SELECT nodes with pseudo instructions.
 let usesCustomInserter = 1 in {
-  class Select_Pseudo<RegisterOperand RC> :
-    PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
-            [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,
+  class Select_Pseudo<RegisterOperand RC, RegisterOperand RO> :
+    PseudoSE<(outs RO:$dst), (ins RC:$cond, RO:$T, RO:$F),
+             [(set RO:$dst, (select RC:$cond, RO:$T, RO:$F))]>,
     ISA_MIPS1_NOT_4_32;
 
-  class SelectFP_Pseudo_T<RegisterOperand RC> :
-    PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
-             [(set RC:$dst, (MipsCMovFP_T RC:$T, GPR32Opnd:$cond, RC:$F))]>,
+  class SelectFP_Pseudo_T<RegisterOperand RO> :
+    PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$cond, RO:$T, RO:$F),
+             [(set RO:$dst, (MipsCMovFP_T RO:$T, GPR32Opnd:$cond, RO:$F))]>,
     ISA_MIPS1_NOT_4_32;
 
-  class SelectFP_Pseudo_F<RegisterOperand RC> :
-    PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
-             [(set RC:$dst, (MipsCMovFP_F RC:$T, GPR32Opnd:$cond, RC:$F))]>,
+  class SelectFP_Pseudo_F<RegisterOperand RO> :
+    PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$cond, RO:$T, RO:$F),
+             [(set RO:$dst, (MipsCMovFP_F RO:$T, GPR32Opnd:$cond, RO:$F))]>,
     ISA_MIPS1_NOT_4_32;
 }
 
-def PseudoSELECT_I : Select_Pseudo<GPR32Opnd>;
-def PseudoSELECT_I64 : Select_Pseudo<GPR64Opnd>;
-def PseudoSELECT_S : Select_Pseudo<FGR32Opnd>;
-def PseudoSELECT_D32 : Select_Pseudo<AFGR64Opnd>, FGR_32;
-def PseudoSELECT_D64 : Select_Pseudo<FGR64Opnd>, FGR_64;
+def PseudoSELECT_I : Select_Pseudo<GPR32Opnd, GPR32Opnd>;
+def PseudoSELECT_I64 : Select_Pseudo<GPR32Opnd, GPR64Opnd>;
+def PseudoSELECT_S : Select_Pseudo<GPR32Opnd, FGR32Opnd>;
+def PseudoSELECT_D32 : Select_Pseudo<GPR32Opnd, AFGR64Opnd>, FGR_32;
+def PseudoSELECT_D64 : Select_Pseudo<GPR32Opnd, FGR64Opnd>, FGR_64;
+
+def PseudoSELECT64_I : Select_Pseudo<GPR64Opnd, GPR32Opnd>, GPR_64;
+def PseudoSELECT64_I64 : Select_Pseudo<GPR64Opnd, GPR64Opnd>, GPR_64;
+def PseudoSELECT64_S : Select_Pseudo<GPR64Opnd, FGR32Opnd>, GPR_64;
+def PseudoSELECT64_D32 : Select_Pseudo<GPR64Opnd, AFGR64Opnd>, GPR_64, FGR_32;
+def PseudoSELECT64_D64 : Select_Pseudo<GPR64Opnd, FGR64Opnd>, GPR_64, FGR_64;
 
 def PseudoSELECTFP_T_I : SelectFP_Pseudo_T<GPR32Opnd>;
 def PseudoSELECTFP_T_I64 : SelectFP_Pseudo_T<GPR64Opnd>;
 def PseudoSELECTFP_T_S : SelectFP_Pseudo_T<FGR32Opnd>;
 def PseudoSELECTFP_T_D32 : SelectFP_Pseudo_T<AFGR64Opnd>, FGR_32;
 def PseudoSELECTFP_T_D64 : SelectFP_Pseudo_T<FGR64Opnd>, FGR_64;
 
 def PseudoSELECTFP_F_I : SelectFP_Pseudo_F<GPR32Opnd>;
 def PseudoSELECTFP_F_I64 : SelectFP_Pseudo_F<GPR64Opnd>;
 def PseudoSELECTFP_F_S : SelectFP_Pseudo_F<FGR32Opnd>;
 def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>, FGR_32;
 def PseudoSELECTFP_F_D64 : SelectFP_Pseudo_F<FGR64Opnd>, FGR_64;

lib/Target/Mips/MipsISelLowering.h

private:
     SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
     SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
     SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
     SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
     SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
                                  bool IsSRA) const;
     SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
     SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
+    SDValue lowerATOMIC_CMP_SWAP_WITH_SUCCESS(SDValue Op,
+                                              SelectionDAG &DAG) const;
 
     /// isEligibleForTailCallOptimization - Check whether the call is eligible
     /// for tail call optimization.
     virtual bool
     isEligibleForTailCallOptimization(const CCState &CCInfo,
                                       unsigned NextStackOffset,
                                       const MipsFunctionInfo &FI) const = 0;
 
private:
     MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
                     MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
                     bool Nand = false) const;
     MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
                                   MachineBasicBlock *BB, unsigned Size) const;
     MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
                                   MachineBasicBlock *BB, unsigned Size) const;
     MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
+
+    MachineBasicBlock *emitSEL64_S(MachineInstr *MI,
+                                   MachineBasicBlock *BB) const;
+
     MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI,
                                         MachineBasicBlock *BB, bool isFPCmp,
                                         unsigned Opc) const;
   };
 
   /// Create MipsTargetLowering objects.
   const MipsTargetLowering *
   createMips16TargetLowering(const MipsTargetMachine &TM,

lib/Target/Mips/MipsISelLowering.cpp

MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
   setTruncStoreAction(MVT::f64, MVT::f16, Expand);
 
   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
 
   // Used by legalize types to correctly generate the setcc result.
   // Without this, every float setcc comes with a AND/OR with the result,
   // we don't want this, since the fpcmp result goes to a flag register,
   // which is used implicitly by brcond and select operations.
-  AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
+  AddPromotedToType(ISD::SETCC, MVT::i1,
+                    ABI.AreGprs64bit() ? MVT::i64 : MVT::i32);
 
   // Mips Custom Operations
   setOperationAction(ISD::BR_JT,              MVT::Other, Custom);
   setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
   setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);
   setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
   setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
   setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
   setOperationAction(ISD::SELECT,             MVT::f32,   Custom);
MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
                                   const TargetLibraryInfo *libInfo) const {
   if (!funcInfo.MF->getTarget().Options.EnableFastISel)
     return TargetLowering::createFastISel(funcInfo, libInfo);
   return Mips::createFastISel(funcInfo, libInfo);
 }
 
 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
                                            EVT VT) const {
-  if (!VT.isVector())
-    return MVT::i32;
+  if (VT.isVector())
     return VT.changeVectorElementTypeToInteger();
+
+  return ABI.AreGprs64bit() ? MVT::i64 : MVT::i32;
 }
 
 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
                                     TargetLowering::DAGCombinerInfo &DCI,
                                     const MipsSubtarget &Subtarget) {
   if (DCI.isBeforeLegalizeOps())
     return SDValue();
 
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
   // If both operands are integer constants there's a possibility that we
   // can do some interesting optimizations.
   SDValue True = N->getOperand(1);
   ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
 
   if (!TrueC || !True.getValueType().isInteger())
     return SDValue();
 
-  // We'll also ignore MVT::i64 operands as this optimizations proves
-  // to be ineffective because of the required sign extensions as the result
-  // of a SETCC operator is always MVT::i32 for non-vector types.
-  if (True.getValueType() == MVT::i64)
-    return SDValue();
-
   int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
 
   // 1)  (a < x) ? y : y-1
   //  slti $reg1, a, x
   //  addiu $reg2, $reg1, y-1
-  if (Diff == 1)
-    return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
+  if (Diff == 1) {
+    if (SetCC.getValueType().getSizeInBits() >
+        False.getValueType().getSizeInBits())
+      SetCC = DAG.getNode(ISD::TRUNCATE, DL, False.getValueType(), SetCC);
+
+    SDValue Ret = DAG.getNode(ISD::ADD, DL, False.getValueType(), SetCC, False);
+    return Ret;
+  }
 
   // 2)  (a < x) ? y-1 : y
   //  slti $reg1, a, x
   //  xor $reg1, $reg1, 1
   //  addiu $reg2, $reg1, y-1
   if (Diff == -1) {
     ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
     SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
                          SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
+
+    if (SetCC.getValueType().getSizeInBits() >
+        True.getValueType().getSizeInBits())
+      SetCC = DAG.getNode(ISD::TRUNCATE, DL, True.getValueType(), SetCC);
+
     return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
   }
 
   // Couldn't optimize.
   return SDValue();
 }
 
 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
   case Mips::PseudoDUDIV:
   case Mips::DDIV:
   case Mips::DDIVU:
   case Mips::DMOD:
   case Mips::DMODU:
     return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true);
   case Mips::SEL_D:
     return emitSEL_D(MI, BB);
+  case Mips::SEL64_S:
+    return emitSEL64_S(MI, BB);
 
   case Mips::PseudoSELECT_I:
   case Mips::PseudoSELECT_I64:
   case Mips::PseudoSELECT_S:
   case Mips::PseudoSELECT_D32:
   case Mips::PseudoSELECT_D64:
-    return emitPseudoSELECT(MI, BB, false, Mips::BNE);
+  // 64-bit version
+  case Mips::PseudoSELECT64_I:
+  case Mips::PseudoSELECT64_I64:
+  case Mips::PseudoSELECT64_S:
+  case Mips::PseudoSELECT64_D32:
+  case Mips::PseudoSELECT64_D64:
+    return emitPseudoSELECT(MI, BB, false,
+                            Subtarget.isGP32bit() ? Mips::BNE : Mips::BNE64);
+
   case Mips::PseudoSELECTFP_F_I:
   case Mips::PseudoSELECTFP_F_I64:
   case Mips::PseudoSELECTFP_F_S:
   case Mips::PseudoSELECTFP_F_D32:
   case Mips::PseudoSELECTFP_F_D64:
     return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
+
   case Mips::PseudoSELECTFP_T_I:
   case Mips::PseudoSELECTFP_T_I64:
   case Mips::PseudoSELECTFP_T_S:
   case Mips::PseudoSELECTFP_T_D32:
   case Mips::PseudoSELECTFP_T_D64:
     return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
   }
 }
MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI,
 
   // We don't erase the original instruction, we just replace the condition
   // register with the 64-bit super-register.
   MI->getOperand(1).setReg(Fc2);
 
   return BB;
 }
 
+MachineBasicBlock *
+MipsTargetLowering::emitSEL64_S(MachineInstr *MI, MachineBasicBlock *BB) const {
+  MachineFunction *MF = BB->getParent();
+  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
+  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
+  MachineRegisterInfo &RegInfo = MF->getRegInfo();
+  DebugLoc DL = MI->getDebugLoc();
+  MachineBasicBlock::iterator II(MI);
+
+  unsigned Fc64 = MI->getOperand(1).getReg();
+
+  const auto &FGR32RegClass = TRI->getRegClass(Mips::FGR32RegClassID);
+  unsigned Fc32 = RegInfo.createVirtualRegister(FGR32RegClass);
+
+  BuildMI(*BB, II, DL, TII->get(Mips::COPY), Fc32)
+      .addReg(Fc64, 0, Mips::sub_lo);
+
+  // We don't erase the original instruction, we just replace the condition
+  // register with the 32-bit sub-register.
+  MI->getOperand(1).setReg(Fc32);
+
+  return BB;
+}
+
 //===----------------------------------------------------------------------===//
 //  Misc Lower Operation implementation
 //===----------------------------------------------------------------------===//
 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
   SDValue Chain = Op.getOperand(0);
   SDValue Table = Op.getOperand(1);
   SDValue Index = Op.getOperand(2);
   SDLoc DL(Op);

 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
   assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
   SDValue Cond = createFPCmp(DAG, Op);
 
   assert(Cond.getOpcode() == MipsISD::FPCmp &&
          "Floating point operand expected.");
 
   SDLoc DL(Op);
-  SDValue True  = DAG.getConstant(1, DL, MVT::i32);
-  SDValue False = DAG.getConstant(0, DL, MVT::i32);
+  EVT VT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
+                              Op.getValueType());
+  SDValue True = DAG.getConstant(1, DL, VT);
+  SDValue False = DAG.getConstant(0, DL, VT);
 
   return createCMovFP(DAG, Cond, True, False, DL);
 }
 
 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
                                                SelectionDAG &DAG) const {
   EVT Ty = Op.getValueType();
   GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
MipsTargetLowering::emitPseudoSELECT(MachineInstr *MI, MachineBasicBlock *BB,
 
   if (isFPCmp) {
     // bc1[tf] cc, sinkMBB
     BuildMI(BB, DL, TII->get(Opc))
       .addReg(MI->getOperand(1).getReg())
       .addMBB(sinkMBB);
   } else {
     // bne rs, $0, sinkMBB
     BuildMI(BB, DL, TII->get(Opc))
         .addReg(MI->getOperand(1).getReg())
-      .addReg(Mips::ZERO)
+        .addReg(ABI.GetZeroReg())
         .addMBB(sinkMBB);
   }
 
   //  copy0MBB:
   //   %FalseValue = ...
   //   # fallthrough to sinkMBB
   BB = copy0MBB;
 
   // Update machine-CFG edges

lib/Target/Mips/MipsInstrInfo.td

InstSE<(outs), (ins RO:$rs, opnd:$offset),
          FrmI, opstr> {
   let isBranch = 1;
   let isTerminator = 1;
   let hasDelaySlot = DelaySlot;
   let Defs = [AT];
 }
 
 // SetCC
-class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
-  InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
+class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RD,
+              RegisterOperand RO> :
+  InstSE<(outs RD:$rd), (ins RO:$rs, RO:$rt),
          !strconcat(opstr, "\t$rd, $rs, $rt"),
-         [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
+         [(set RD:$rd, (cond_op RO:$rs, RO:$rt))],
          II_SLT_SLTU, FrmR, opstr>;
 
 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
-              RegisterOperand RO>:
-  InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
+              RegisterOperand RD, RegisterOperand RO>:
+  InstSE<(outs RD:$rt), (ins RO:$rs, Od:$imm16),
          !strconcat(opstr, "\t$rt, $rs, $imm16"),
-         [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
+         [(set RD:$rt, (cond_op RO:$rs, imm_type:$imm16))],
          II_SLTI_SLTIU, FrmI, opstr>;
 
 // Jump
 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
              SDPatternOperator targetoperator, string bopstr> :
   InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
          [(operator targetoperator:$target)], II_J, FrmJ, bopstr> {
   let isTerminator=1;

 /// Arithmetic Instructions (ALU Immediate)
 let AdditionalPredicates = [NotInMicroMips] in {
 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16, GPR32Opnd,
                                            II_ADDIU, immSExt16, add>,
             ADDI_FM<0x9>, IsAsCheapAsAMove;
 }
 def ADDi  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
             ISA_MIPS1_NOT_32R6_64R6;
-def SLTi  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
-            SLTI_FM<0xa>;
-def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
-            SLTI_FM<0xb>;
+def SLTi  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd,
+            GPR32Opnd>, SLTI_FM<0xa>;
+def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd,
+            GPR32Opnd>, SLTI_FM<0xb>;
 let AdditionalPredicates = [NotInMicroMips] in {
 def ANDi  : MMRel, StdMMR6Rel,
             ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
             ADDI_FM<0xc>;
 }
 def ORi   : MMRel, StdMMR6Rel,
             ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
             ADDI_FM<0xd>;
 def XORi  : MMRel, StdMMR6Rel,
             ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
             ADDI_FM<0xe>;
 def LUi   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM;
 let AdditionalPredicates = [NotInMicroMips] in {
 /// Arithmetic Instructions (3-Operand, R-Type)
 def ADDu  : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
             ADD_FM<0, 0x21>;
 def SUBu  : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
             ADD_FM<0, 0x23>;
 }
 let Defs = [HI0, LO0] in
 def MUL   : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
             ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
 def ADD   : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
 def SUB   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
-def SLT   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
-def SLTu  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
+def SLT   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd, GPR32Opnd>, ADD_FM<0, 0x2a>;
+def SLTu  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd, GPR32Opnd>, ADD_FM<0, 0x2b>;
 let AdditionalPredicates = [NotInMicroMips] in {
 def AND   : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
             ADD_FM<0, 0x24>;
 def OR    : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
             ADD_FM<0, 0x25>;
 def XOR   : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
             ADD_FM<0, 0x26>;
 }

 def : MipsPat<(i32 (extloadi1  addr:$src)), (LBu addr:$src)>;
 def : MipsPat<(i32 (extloadi8  addr:$src)), (LBu addr:$src)>;
 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
 
 // peepholes
 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
 
 // brcond patterns
-multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
-                      Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
-                      Instruction SLTiuOp, Register ZEROReg> {
-def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
+multiclass BrcondPats1<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
+                       Register ZEROReg, ValueType VT> {
+def : MipsPat<(brcond (VT (setne RC:$lhs, 0)), bb:$dst),
               (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
-def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
+def : MipsPat<(brcond (VT (seteq RC:$lhs, 0)), bb:$dst),
               (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
-
-def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
-              (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
-def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
-              (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
-def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
-              (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
-def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
-              (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
-def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
-              (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
-def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
-              (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
-
-def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
-              (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
-def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
-              (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
-
 def : MipsPat<(brcond RC:$cond, bb:$dst),
               (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
 }
 
-defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
+multiclass BrcondPats2<RegisterClass RC, Instruction BEQOp, Register ZEROReg,
+                       Instruction SLTOp, Instruction SLTuOp,
+                       Instruction SLTiOp, Instruction SLTiuOp,
+                       ValueType VT> {
+def : MipsPat<(brcond (VT (setge RC:$lhs, RC:$rhs)), bb:$dst),
+              (BEQOp (SLTOp RC:$lhs, RC:$rhs), ZEROReg, bb:$dst)>;
+def : MipsPat<(brcond (VT (setuge RC:$lhs, RC:$rhs)), bb:$dst),
+              (BEQOp (SLTuOp RC:$lhs, RC:$rhs), ZEROReg, bb:$dst)>;
+def : MipsPat<(brcond (VT (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
+              (BEQOp (SLTiOp RC:$lhs, immSExt16:$rhs), ZEROReg, bb:$dst)>;
+def : MipsPat<(brcond (VT (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
+              (BEQOp (SLTiuOp RC:$lhs, immSExt16:$rhs), ZEROReg, bb:$dst)>;
+def : MipsPat<(brcond (VT (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
+              (BEQOp (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZEROReg, bb:$dst)>;
+def : MipsPat<(brcond (VT (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
+              (BEQOp (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZEROReg, bb:$dst)>;
+def : MipsPat<(brcond (VT (setle RC:$lhs, RC:$rhs)), bb:$dst),
+              (BEQOp (SLTOp RC:$rhs, RC:$lhs), ZEROReg, bb:$dst)>;
+def : MipsPat<(brcond (VT (setule RC:$lhs, RC:$rhs)), bb:$dst),
+              (BEQOp (SLTuOp RC:$rhs, RC:$lhs), ZEROReg, bb:$dst)>;
+}
+
+defm : BrcondPats1<GPR32, BEQ, BNE, ZERO, i32>;
+defm : BrcondPats2<GPR32, BEQ, ZERO, SLT, SLTu, SLTi, SLTiu, i32>;
 
 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
               (BLEZ i32:$lhs, bb:$dst)>;
 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
               (BGEZ i32:$lhs, bb:$dst)>;
 
 // setcc patterns
 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
                      Instruction SLTuOp, Register ZEROReg> {
   def : MipsPat<(seteq RC:$lhs, 0),
                 (SLTiuOp RC:$lhs, 1)>;
   def : MipsPat<(setne RC:$lhs, 0),
                 (SLTuOp ZEROReg, RC:$lhs)>;
   def : MipsPat<(seteq RC:$lhs, RC:$rhs),
                 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
   def : MipsPat<(setne RC:$lhs, RC:$rhs),
                 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
 }
 
-multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
+multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp,
+                     Instruction XORiOp> {
   def : MipsPat<(setle RC:$lhs, RC:$rhs),
-                (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
+                (XORiOp (SLTOp RC:$rhs, RC:$lhs), 1)>;
   def : MipsPat<(setule RC:$lhs, RC:$rhs),
-                (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
+                (XORiOp (SLTuOp RC:$rhs, RC:$lhs), 1)>;
 }
 
 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
   def : MipsPat<(setgt RC:$lhs, RC:$rhs),
                 (SLTOp RC:$rhs, RC:$lhs)>;
   def : MipsPat<(setugt RC:$lhs, RC:$rhs),
                 (SLTuOp RC:$rhs, RC:$lhs)>;
 }
 
-multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
+multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp,
+                     Instruction XORiOp> {
   def : MipsPat<(setge RC:$lhs, RC:$rhs),
-                (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
+                (XORiOp (SLTOp RC:$lhs, RC:$rhs), 1)>;
   def : MipsPat<(setuge RC:$lhs, RC:$rhs),
-                (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
+                (XORiOp (SLTuOp RC:$lhs, RC:$rhs), 1)>;
 }
 
 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
-                        Instruction SLTiuOp> {
+                        Instruction SLTiuOp, Instruction XORiOp> {
   def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
-                (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
+                (XORiOp (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
   def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
-                (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
+                (XORiOp (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
 }
 
 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
-defm : SetlePats<GPR32, SLT, SLTu>;
+defm : SetlePats<GPR32, SLT, SLTu, XORi>;
 defm : SetgtPats<GPR32, SLT, SLTu>;
-defm : SetgePats<GPR32, SLT, SLTu>;
-defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
+defm : SetgePats<GPR32, SLT, SLTu, XORi>;
+defm : SetgeImmPats<GPR32, SLTi, SLTiu, XORi>;
 
 // bswap pattern
 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
 
 // Load halfword/word patterns.
 let AddedComplexity = 40 in {
   def : LoadRegImmPat<LBu, i32, zextloadi8>;
   def : LoadRegImmPat<LH, i32, sextloadi16>;

lib/Target/Mips/MipsRegisterInfo.td

 // FP control registers.
 def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
           Unallocatable;
 
 // FP condition code registers.
 def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
           Unallocatable;
 
 // MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.
-// This class allows us to represent this in codegen patterns.
-def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>;
+// These classes allow us to represent this in codegen patterns.
+def FGRCC32 : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>;
+def FGRCC64 : RegisterClass<"Mips", [i64], 64, (sequence "D%u_64", 0, 31)>;
 
 def MSA128B: RegisterClass<"Mips", [v16i8], 128,
                            (sequence "W%u", 0, 31)>;
 def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
                            (sequence "W%u", 0, 31)>;
 def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128,
                            (sequence "W%u", 0, 31)>;
 def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128,

 def FGR64Opnd : RegisterOperand<FGR64> {
   let ParserMatchClass = FGR64AsmOperand;
 }
 
 def FGR32Opnd : RegisterOperand<FGR32> {
   let ParserMatchClass = FGR32AsmOperand;
 }
 
-def FGRCCOpnd : RegisterOperand<FGRCC> {
+def FGRCC32Opnd : RegisterOperand<FGRCC32> {
+  // The assembler doesn't use register classes so we can re-use
+  // FGR32AsmOperand.
+  let ParserMatchClass = FGR32AsmOperand;
+}
+
+def FGRCC64Opnd : RegisterOperand<FGRCC64> {
   // The assembler doesn't use register classes so we can re-use
   // FGR32AsmOperand.
   let ParserMatchClass = FGR32AsmOperand;
 }
 
 def FGRH32Opnd : RegisterOperand<FGRH32> {
   let ParserMatchClass = FGRH32AsmOperand;
 }

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

if (Subtarget->isGP64bit()) {
     SLTuOp = Mips::SLTu64;
     ADDuOp = Mips::DADDu;
   }
 
   SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
   SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
   EVT VT = LHS.getValueType();
 
-  SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);
-
-  if (Subtarget->isGP64bit()) {
-    // On 64-bit targets, sltu produces an i64 but our backend currently says
-    // that SLTu64 produces an i32. We need to fix this in the long run but for
-    // now, just make the DAG type-correct by asserting the upper bits are zero.
-    Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
-                                   CurDAG->getTargetConstant(0, DL, VT),
-                                   SDValue(Carry, 0),
-                                   CurDAG->getTargetConstant(Mips::sub_32, DL,
-                                                             VT));
-  }
-
   // Generate a second addition only if we know that RHS is not a
   // constant-zero node.
-  SDNode *AddCarry = Carry;
+  SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);
   ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
   if (!C || C->getZExtValue())
-    AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT, SDValue(Carry, 0), RHS);
+    Carry = CurDAG->getMachineNode(ADDuOp, DL, VT, SDValue(Carry, 0), RHS);
 
-  return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
-                              SDValue(AddCarry, 0));
+  return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, SDValue(Carry, 0));
 }
 
 /// Match frameindex
 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
                                               SDValue &Offset) const {
   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
     EVT ValTy = Addr.getValueType();
 

lib/Target/Mips/MipsSEISelLowering.cpp

SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
 
   if (!HasLo || !HasHi)
     return HasLo ? Lo : Hi;
 
   SDValue Vals[] = { Lo, Hi };
   return DAG.getMergeValues(Vals, DL);
 }
 
-
 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
   SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
                              DAG.getConstant(0, DL, MVT::i32));
   SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
                              DAG.getConstant(1, DL, MVT::i32));
   return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
 }
 

test/CodeGen/Mips/atomic.ll

 ; ALL:           srlv    $[[R17:[0-9]+]], $[[R14]], $[[R5]]
 
 ; NO-SEB-SEH:    sll     $[[R18:[0-9]+]], $[[R17]], 24
 ; NO-SEB-SEH:    sra     $[[R19:[0-9]+]], $[[R18]], 24
 
 ; HAS-SEB-SEH:   seb     $[[R19:[0-9]+]], $[[R17]]
 
 ; ALL:           xor     $[[R20:[0-9]+]], $[[R19]], $5
-; ALL:           sltiu   $2, $[[R20]], 1
+
+; MIPS32-ANY:    sltiu   $2, $[[R20]], 1
+
+; MIPS64-ANY:    sltiu   $[[R21:[0-9]+]], $[[R20]], 1
+; MIPS64-ANY:    sll     $2, $[[R21]], 0
 }
 
 ; Check one i16 so that we cover the seh sign extend
 @z = common global i16 0, align 1
 
 define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind {
 entry:
   %0 = atomicrmw add i16* @z, i16 %incr monotonic

test/CodeGen/Mips/blez_bgez.ll

-; RUN: llc -march=mipsel < %s | FileCheck %s
-; RUN: llc -march=mips64el < %s | FileCheck %s
+; RUN: llc -march=mipsel < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL
+; RUN: llc -march=mips64el < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=GP64
 
-; CHECK-LABEL: test_blez:
-; CHECK: blez ${{[0-9]+}}, $BB
+declare void @foo1()
 
 define void @test_blez(i32 %a) {
+; ALL-LABEL: test_blez:
+; ALL: blez ${{[0-9]+}}, $BB
 entry:
   %cmp = icmp sgt i32 %a, 0
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   tail call void @foo1()
   br label %if.end
 
 if.end:
   ret void
 }
 
-declare void @foo1()
-
-; CHECK-LABEL: test_bgez:
-; CHECK: bgez ${{[0-9]+}}, $BB
-
 define void @test_bgez(i32 %a) {
 entry:
+; ALL-LABEL: test_bgez:
+; ALL: bgez ${{[0-9]+}}, $BB
   %cmp = icmp slt i32 %a, 0
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   tail call void @foo1()
   br label %if.end
 
 if.end:
   ret void
 }
+
+define void @test_blez_64(i64 %a) {
+; GP64-LABEL: test_blez_64:
+; GP64: blez ${{[0-9]+}}, $BB
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  tail call void @foo1()
+  br label %if.end
+
+if.end:
+  ret void
+}
+
+define void @test_bgez_64(i64 %a) {
+entry:
+; ALL-LABEL: test_bgez_64:
+; ALL: bgez ${{[0-9]+}}, $BB
+  %cmp = icmp slt i64 %a, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  tail call void @foo1()
+  br label %if.end
+
+if.end:
+  ret void
+}

test/CodeGen/Mips/cmov.ll

-; RUN: llc -march=mips     -mcpu=mips32                 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
-; RUN: llc -march=mips     -mcpu=mips32 -regalloc=basic < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
-; RUN: llc -march=mips     -mcpu=mips32r2               < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
-; RUN: llc -march=mips     -mcpu=mips32r6               < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMP
-; RUN: llc -march=mips64el -mcpu=mips4                  < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
-; RUN: llc -march=mips64el -mcpu=mips64                 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
-; RUN: llc -march=mips64el -mcpu=mips64r6               < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMP
+; RUN: llc -march=mips -mcpu=mips32 < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
+; RUN: llc -march=mips -mcpu=mips32 -regalloc=basic < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
+; RUN: llc -march=mips -mcpu=mips32r2 < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
+; RUN: llc -march=mips -mcpu=mips32r6 < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=32-CMP
+; RUN: llc -march=mips64el -mcpu=mips4 < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -check-prefix=64
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -check-prefix=64
+; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=64-CMP -check-prefix=64
 
 @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
 @i3 = common global i32* null, align 4
 
 ; ALL-LABEL: cmov1:
 
 ; 32-CMOV-DAG:  lw $[[R0:[0-9]+]], %got(i3)
 ; 32-CMOV-DAG:  addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)

 ; 32-CMP:       or $[[CC:[0-9]+]], $[[CC3]], $[[CC2]]
 ; 32-CMP-DAG:   addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMP-DAG:   addiu $[[I4:[0-9]+]], $zero, 4
 ; 32-CMP-DAG:   seleqz $[[T0:[0-9]+]], $[[I4]], $[[CC]]
 ; 32-CMP-DAG:   selnez $[[T1:[0-9]+]], $[[I5]], $[[CC]]
 ; 32-CMP-DAG:   or $3, $[[T1]], $[[T0]]
 ; 32-CMP-DAG:   addiu $2, $zero, 0
 
-; 64-CMOV-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMOV-DAG:  addiu $[[I4:2]], $zero, 4
-; 64-CMOV-DAG:  slti $[[R0:[0-9]+]], $4, 32767
-; 64-CMOV-DAG:  movz $[[I4]], $[[I5]], $[[R0]]
-
-; 64-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMP-DAG:  addiu $[[I4:[0-9]+]], $zero, 4
-; 64-CMP-DAG:  slti $[[R0:[0-9]+]], $4, 32767
-; FIXME: We can do better than this by adding/subtracting the result of slti
-;        to/from one of the constants.
-; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I5]], $[[R0]]
-; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I4]], $[[R0]]
-; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
-
+; 64-DAG:  daddiu  $[[T0:[0-9]+]], $zero, 32766
+; 64-DAG:  slt     $[[T1:[0-9]+]], $[[T0]], $4
+; 64-DAG:  ori     $2, $[[T1]], 4
 define i64 @slti64_0(i64 %a) {
 entry:
   %cmp = icmp sgt i64 %a, 32766
   %conv = select i1 %cmp, i64 5, i64 4
   ret i64 %conv
 }
 
 ; ALL-LABEL: slti64_1:

 ; 32-CMP:       or $[[CC:[0-9]+]], $[[CC3]], $[[CC2]]
 ; 32-CMP-DAG:   addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMP-DAG:   addiu $[[I4:[0-9]+]], $zero, 4
 ; 32-CMP-DAG:   seleqz $[[T0:[0-9]+]], $[[I4]], $[[CC]]
 ; 32-CMP-DAG:   selnez $[[T1:[0-9]+]], $[[I5]], $[[CC]]
 ; 32-CMP-DAG:   or $3, $[[T1]], $[[T0]]
 ; 32-CMP-DAG:   addiu $2, $zero, 0
 
-; 64-CMOV-DAG: daddiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4
-; 64-CMOV-DAG: daddiu $[[R1:[0-9]+]], $zero, 32767
-; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4
-; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]]
-
-; 64-CMP-DAG:  daddiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMP-DAG:  daddiu $[[I4:2]], $zero, 4
-; 64-CMP-DAG:  daddiu $[[R1:[0-9]+]], $zero, 32767
-; 64-CMP-DAG:  slt $[[R0:[0-9]+]], $[[R1]], $4
-; FIXME: We can do better than this by using selccz to choose between -0 and -2
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I5]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I4]], $[[R0]]
-; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
-
+; 64-DAG:  daddiu $[[T0:[0-9]+]], $zero, 32767
+; 64-DAG:  slt $[[T1:[0-9]+]], $[[T0]], $4
+; 64-DAG:  ori $2, $[[T1]], 4
 define i64 @slti64_1(i64 %a) {
 entry:
   %cmp = icmp sgt i64 %a, 32767
   %conv = select i1 %cmp, i64 5, i64 4
   ret i64 %conv
 }
 
-; ALL-LABEL: slti64_2:
-
-; FIXME: The 32-bit versions of this test are too complicated to reasonably
-;        match at the moment. They do show some missing optimizations though
-;        such as:
-;           (movz $a, $b, (neg $c)) -> (movn $a, $b, $c)
+; ALL-LABEL: slti32_2:
 
-; 64-CMOV-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
-; 64-CMOV-DAG:  addiu $[[I4:2]], $zero, 4
-; 64-CMOV-DAG:  slti $[[R0:[0-9]+]], $4, -32768
-; 64-CMOV-DAG:  movz $[[I4]], $[[I3]], $[[R0]]
+; FIXME: Remove unecessary sign-extension.
+; 64-DAG:  slti    $[[T0:[0-9]+]], $4, -32768
+; 64-DAG:  sll     $[[T1:[0-9]+]], $[[T0]], 0
+; 64-DAG:  addiu   $2, $[[T1]], 3
+define i32 @slti32_2(i32 signext %a) {
+entry:
+  %cmp = icmp sgt i32 %a, -32769
+  %conv = select i1 %cmp, i32 3, i32 4
+  ret i32 %conv
+}
 
-; 64-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
-; 64-CMP-DAG:  addiu $[[I4:[0-9]+]], $zero, 4
-; 64-CMP-DAG:  slti $[[R0:[0-9]+]], $4, -32768
-; FIXME: We can do better than this by adding/subtracting the result of slti
-;        to/from one of the constants.
-; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I4]], $[[R0]]
-; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
+; ALL-LABEL: slti64_2:
 
+; 64-DAG:  slti    $[[T0:[0-9]+]], $4, -32768
+; 64-DAG:  daddiu  $2, $[[T0]], 3
 define i64 @slti64_2(i64 %a) {
 entry:
   %cmp = icmp sgt i64 %a, -32769
   %conv = select i1 %cmp, i64 3, i64 4
   ret i64 %conv
 }
 
-; ALL-LABEL: slti64_3:
+; ALL-LABEL: slti32_3:
 
-; FIXME: The 32-bit versions of this test are too complicated to reasonably
-;        match at the moment. They do show some missing optimizations though
-;        such as:
-;           (movz $a, $b, (neg $c)) -> (movn $a, $b, $c)
-
-; 64-CMOV-DAG: daddiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4
-; 64-CMOV-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766
-; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4
-; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]]
+; FIXME: Remove unecessary sign-extension.
+; 64-DAG: slt     $[[R0:[0-9]+]], ${{[0-9]+}}, $4
+; 64-DAG: sll     $[[R1:[0-9]+]], $[[R0]], 0
+; 64-DAG: ori     $2, $[[R1]], 4
+define i32 @slti32_3(i32 signext %a) {
+entry:
+  %cmp = icmp sgt i32 %a, -32770
+  %conv = select i1 %cmp, i32 5, i32 4
+  ret i32 %conv
+}
 
-; 64-CMP-DAG:  daddiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMP-DAG:  daddiu $[[I4:2]], $zero, 4
-; 64-CMP-DAG:  daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766
-; 64-CMP-DAG:  slt $[[R0:[0-9]+]], $[[R1]], $4
-; FIXME: We can do better than this by using selccz to choose between -0 and -2
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I5]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I4]], $[[R0]]
-; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
+; ALL-LABEL: slti64_3:
 
+; 64-DAG: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32766
+; 64-DAG: slt $[[R1:[0-9]+]], $[[R0]], $4
+; 64-DAG: ori $2, $[[R1]], 4
 define i64 @slti64_3(i64 %a) {
 entry:
   %cmp = icmp sgt i64 %a, -32770
   %conv = select i1 %cmp, i64 5, i64 4
   ret i64 %conv
 }
 
 ; sltiu instructions.

test/CodeGen/Mips/countleading.ll

 ; RUN: llc -march=mipsel -mcpu=mips32   < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s
 ; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s
 ; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R6    -check-prefix=MIPS32-GT-R1 %s
 ; RUN: llc -march=mips64el -mcpu=mips4    < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s
 ; RUN: llc -march=mips64el -mcpu=mips64   < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
-; R!N: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
+; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
 
 ; Prefixes:
 ;   ALL      - All
 ;   MIPS32-GT-R1 - MIPS64r1 and above (does not include MIPS64's)
 ;   MIPS64-GT-R1 - MIPS64r1 and above
 
 define i32 @ctlz_i32(i32 signext %X) nounwind readnone {
 entry:

test/CodeGen/Mips/fcmp.ll

 
 define i32 @oeq_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: oeq_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.eq.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
+; FIXME: The sign extension below is redundant.
 ; 64-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG:    andi $2, $[[T1]], 1
+; 64-CMP-DAG:    dmfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    sll $[[T2:[0-9]+]], $[[T1]], 0
+; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp oeq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ogt_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ogt_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ule.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ogt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @oge_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: oge_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ult.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp oge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @olt_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: olt_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.olt.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp olt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ole_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ole_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ole.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ole float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @one_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: one_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ueq.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp one float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ord_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ord_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.un.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp ord float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ueq_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ueq_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ueq.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ueq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ugt_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ugt_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ole.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ugt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @uge_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: uge_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.olt.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp uge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ult_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ult_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ult.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 
   %1 = fcmp ult float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ule_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ule_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ule.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ule float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @une_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: une_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.eq.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp une float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @uno_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: uno_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.un.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1

 
 define i32 @oeq_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: oeq_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.eq.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp oeq double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ogt_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ogt_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ule.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ogt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @oge_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: oge_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ult.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp oge double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @olt_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: olt_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.olt.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp olt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ole_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ole_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ole.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ole double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @one_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: one_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ueq.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp one double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ord_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ord_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.un.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp ord double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ueq_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ueq_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ueq.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ueq double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ugt_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ugt_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ole.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ugt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @uge_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: uge_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.olt.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp uge double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ult_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ult_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ult.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ult double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ule_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ule_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ule.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ule double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @une_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: une_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.eq.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp une double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @uno_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: uno_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.un.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1

test/CodeGen/Mips/llvm-ir/select-dbl.ll

 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
 
-define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
+define double @tst_select_i1_double(i1 %s, double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_double:
 
   ; M2:         andi    $[[T0:[0-9]+]], $4, 1
   ; M2:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
   ; M2:         nop
   ; M2:         ldc1    $f0, 16($sp)
   ; M2:         jr      $ra
   ; M2:         nop
   ; M2:         $[[BB0]]:
   ; M2:         mtc1    $7, $f0
   ; M2:         jr      $ra
   ; M2:         mtc1    $6, $f1
 
   ; CMOV-32:      mtc1    $7, $[[F0:f[0-9]+]]
   ; CMOV-32R1:    mtc1    $6, $f{{[0-9]+}}
   ; CMOV-32R2-R5: mthc1   $6, $[[F0]]
   ; CMOV-32:      andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV-32:      ldc1    $f0, 16($sp)
   ; CMOV-32:      movn.d  $f0, $[[F0]], $[[T0]]
 
   ; SEL-32:     mtc1    $7, $[[F0:f[0-9]+]]
   ; SEL-32:     mthc1   $6, $[[F0]]
+  ; SEL-32:     sll     $[[T0:[0-9]+]], $4, 31
+  ; SEL-32:     sra     $[[T1:[0-9]+]], $[[T0]], 31
   ; SEL-32:     ldc1    $[[F1:f[0-9]+]], 16($sp)
-  ; SEL-32:     mtc1    $4, $f0
+  ; SEL-32:     mtc1    $[[T1]], $f0
   ; SEL-32:     sel.d   $f0, $[[F1]], $[[F0]]
 
   ; M3:         andi    $[[T0:[0-9]+]], $4, 1
   ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
   ; M3:         nop
   ; M3:         mov.d   $f13, $f14
   ; M3:         $[[BB0]]:
   ; M3:         jr      $ra
   ; M3:         mov.d   $f0, $f13
 
   ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV-64:    movn.d  $f14, $f13, $[[T0]]
   ; CMOV-64:    mov.d   $f0, $f14
 
-  ; SEL-64:     mtc1    $4, $f0
+  ; SEL-64:     dsll    $[[T0:[0-9]+]], $4, 63
+  ; SEL-64:     dsra    $[[T1:[0-9]+]], $[[T0]], 63
+  ; SEL-64:     dmtc1   $[[T1]], $f0
   ; SEL-64:     sel.d   $f0, $f14, $f13
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
-define double @tst_select_i1_double_reordered(double %x, double %y,
-                                              i1 signext %s) {
+define double @tst_select_i1_double_reordered(double %x, double %y, i1 %s) {
 entry:
   ; ALL-LABEL: tst_select_i1_double_reordered:
 
   ; M2:         lw      $[[T0:[0-9]+]], 16($sp)
   ; M2:         andi    $[[T1:[0-9]+]], $[[T0]], 1
   ; M2:         bnez    $[[T1]], $[[BB0:BB[0-9_]+]]
   ; M2:         nop
   ; M2:         mov.d   $f12, $f14
entry:
   ; M3:         $[[BB0]]:
   ; M3:         jr      $ra
   ; M3:         mov.d   $f0, $f12
 
   ; CMOV-64:    andi    $[[T0:[0-9]+]], $6, 1
   ; CMOV-64:    movn.d  $f13, $f12, $[[T0]]
   ; CMOV-64:    mov.d   $f0, $f13
 
-  ; SEL-64:     mtc1    $6, $f0
+  ; SEL-64:     dsll    $[[T0:[0-9]+]], $6, 63
+  ; SEL-64:     dsra    $[[T1:[0-9]+]], $[[T0]], 63
+  ; SEL-64:     dmtc1   $[[T1]], $f0
   ; SEL-64:     sel.d   $f0, $f13, $f12
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_fcmp_olt_double(double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_olt_double:

test/CodeGen/Mips/llvm-ir/select-flt.ll

 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
 
-define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
+define float @tst_select_i1_float(i1 %s, float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_float:
 
   ; M2-M3:      andi    $[[T0:[0-9]+]], $4, 1
   ; M2-M3:      bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         jr      $ra
   ; M2:         mtc1    $6, $f0
   ; M3:         mov.s   $f13, $f14
   ; M2-M3:      $[[BB0]]:
   ; M2-M3:      jr      $ra
   ; M2:         mtc1    $5, $f0
   ; M3:         mov.s   $f0, $f13
 
   ; CMOV-32:    mtc1    $6, $f0
   ; CMOV-32:    mtc1    $5, $f1
   ; CMOV-32:    andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV-32:    movn.s  $f0, $f1, $[[T0]]
 
   ; SEL-32:     mtc1    $5, $[[F0:f[0-9]+]]
   ; SEL-32:     mtc1    $6, $[[F1:f[0-9]+]]
-  ; SEL-32:     mtc1    $4, $f0
+  ; SEL-32:     sll     $[[T0:[0-9]+]], $4, 31
+  ; SEL-32:     sra     $[[T1:[0-9]+]], $[[T0]], 31
+  ; SEL-32:     mtc1    $[[T1]], $f0
   ; SEL-32:     sel.s   $f0, $[[F1]], $[[F0]]
 
   ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV-64:    movn.s  $f14, $f13, $[[T0]]
   ; CMOV-64:    mov.s   $f0, $f14
 
-  ; SEL-64:     mtc1    $4, $f0
+  ; SEL-64:     dsll    $[[T0:[0-9]+]], $4, 63
+  ; SEL-64:     dsra    $[[T1:[0-9]+]], $[[T0]], 63
+  ; SEL-64:     dmtc1   $[[T1]], $f0
   ; SEL-64:     sel.s   $f0, $f14, $f13
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
-define float @tst_select_i1_float_reordered(float %x, float %y,
-                                            i1 signext %s) {
+define float @tst_select_i1_float_reordered(float %x, float %y, i1 %s) {
 entry:
   ; ALL-LABEL: tst_select_i1_float_reordered:
 
   ; M2-M3:      andi    $[[T0:[0-9]+]], $6, 1
   ; M2-M3:      bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         mov.s   $f12, $f14
   ; M3:         mov.s   $f12, $f13
   ; M2-M3:      $[[BB0]]:
   ; M2-M3:      jr      $ra
   ; M2-M3:      mov.s   $f0, $f12
 
   ; CMOV-32:    andi    $[[T0:[0-9]+]], $6, 1
   ; CMOV-32:    movn.s  $f14, $f12, $[[T0]]
   ; CMOV-32:    mov.s   $f0, $f14
 
-  ; SEL-32:     mtc1    $6, $f0
+  ; SEL-32:     sll     $[[T0:[0-9]+]], $6, 31
+  ; SEL-32:     sra     $[[T1:[0-9]+]], $[[T0]], 31
+  ; SEL-32:     mtc1    $[[T1]], $f0
   ; SEL-32:     sel.s   $f0, $f14, $f12
 
   ; CMOV-64:    andi    $[[T0:[0-9]+]], $6, 1
   ; CMOV-64:    movn.s  $f13, $f12, $[[T0]]
   ; CMOV-64:    mov.s   $f0, $f13
 
-  ; SEL-64:     mtc1    $6, $f0
+  ; SEL-64:     dsll    $[[T0:[0-9]+]], $6, 63
+  ; SEL-64:     dsra    $[[T1:[0-9]+]], $[[T0]], 63
+  ; SEL-64:     dmtc1   $[[T1]], $f0
   ; SEL-64:     sel.s   $f0, $f13, $f12
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
 define float @tst_select_fcmp_olt_float(float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_olt_float:

test/CodeGen/Mips/llvm-ir/select-int.ll

 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
 
-define signext i1 @tst_select_i1_i1(i1 signext %s,
-                                    i1 signext %x, i1 signext %y) {
+define signext i1 @tst_select_i1_i1(i1 %s, i1 signext %x, i1 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i1:
 
   ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
   ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
   ; M2-M3:  nop
   ; M2-M3:  move    $5, $6
   ; M2-M3:  $[[BB0]]:
   ; M2-M3:  jr      $ra
   ; M2-M3:  move    $2, $5
 
   ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV:   movn    $6, $5, $[[T0]]
   ; CMOV:   move    $2, $6
 
   ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
   ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
   ; SEL:    or      $2, $[[T2]], $[[T1]]
   %r = select i1 %s, i1 %x, i1 %y
   ret i1 %r
 }
 
-define signext i8 @tst_select_i1_i8(i1 signext %s,
-                                    i8 signext %x, i8 signext %y) {
+define signext i8 @tst_select_i1_i8(i1 %s, i8 signext %x, i8 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i8:
 
   ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
   ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
   ; M2-M3:  nop
   ; M2-M3:  move    $5, $6
   ; M2-M3:  $[[BB0]]:
   ; M2-M3:  jr      $ra
   ; M2-M3:  move    $2, $5
 
   ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV:   movn    $6, $5, $[[T0]]
   ; CMOV:   move    $2, $6
 
   ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
   ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
   ; SEL:    or      $2, $[[T2]], $[[T1]]
   %r = select i1 %s, i8 %x, i8 %y
   ret i8 %r
 }
 
-define signext i32 @tst_select_i1_i32(i1 signext %s,
-                                      i32 signext %x, i32 signext %y) {
+define signext i32 @tst_select_i1_i32(i1 %s, i32 signext %x, i32 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i32:
 
   ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
   ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
   ; M2-M3:  nop
   ; M2-M3:  move    $5, $6
   ; M2-M3:  $[[BB0]]:
   ; M2-M3:  jr      $ra
   ; M2-M3:  move    $2, $5
 
   ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV:   movn    $6, $5, $[[T0]]
   ; CMOV:   move    $2, $6
 
   ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
   ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
   ; SEL:    or      $2, $[[T2]], $[[T1]]
   %r = select i1 %s, i32 %x, i32 %y
   ret i32 %r
 }
 
-define signext i64 @tst_select_i1_i64(i1 signext %s,
-                                      i64 signext %x, i64 signext %y) {
+define signext i64 @tst_select_i1_i64(i1 %s, i64 signext %x, i64 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i64:
 
   ; M2:     andi    $[[T0:[0-9]+]], $4, 1
   ; M2:     bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
   ; M2:     nop
   ; M2:     lw      $[[T1:[0-9]+]], 16($sp)
   ; M2:     $[[BB0]]:
entry:
   ; M3:         jr      $ra
   ; M3:         move    $2, $5
 
   ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV-64:    movn    $6, $5, $[[T0]]
   ; CMOV-64:    move    $2, $6
 
   ; SEL-64:     andi    $[[T0:[0-9]+]], $4, 1
-  ; FIXME: This shift is redundant
-  ; SEL-64:     sll     $[[T0]], $[[T0]], 0
   ; SEL-64:     seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL-64:     selnez  $[[T0]], $5, $[[T0]]
   ; SEL-64:     or      $2, $[[T0]], $[[T1]]
   %r = select i1 %s, i64 %x, i64 %y
   ret i64 %r
 }

test/CodeGen/Mips/octeon.ll

 }
 
 define i64 @cmpeq(i64 %a, i64 %b) nounwind {
 entry:
 ; ALL-LABEL: cmpeq:
 ; OCTEON: jr     $ra
 ; OCTEON: seq    $2, $4, $5
 ; MIPS64: xor    $[[T0:[0-9]+]], $4, $5
-; MIPS64: sltiu  $[[T1:[0-9]+]], $[[T0]], 1
-; MIPS64: dsll   $[[T2:[0-9]+]], $[[T1]], 32
 ; MIPS64: jr     $ra
-; MIPS64: dsrl   $2, $[[T2]], 32
+; MIPS64: sltiu  $2, $[[T0]], 1
   %res = icmp eq i64 %a, %b
   %res2 = zext i1 %res to i64
   ret i64 %res2
 }
 
 define i64 @cmpeqi(i64 %a) nounwind {
 entry:
 ; ALL-LABEL: cmpeqi:
 ; OCTEON: jr     $ra
 ; OCTEON: seqi   $2, $4, 42
 ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42
 ; MIPS64: xor    $[[T1:[0-9]+]], $4, $[[T0]]
-; MIPS64: sltiu  $[[T2:[0-9]+]], $[[T1]], 1
-; MIPS64: dsll   $[[T3:[0-9]+]], $[[T2]], 32
 ; MIPS64: jr     $ra
-; MIPS64: dsrl   $2, $[[T3]], 32
+; MIPS64: sltiu  $2, $[[T1]], 1
   %res = icmp eq i64 %a, 42
   %res2 = zext i1 %res to i64
   ret i64 %res2
 }
 
 define i64 @cmpne(i64 %a, i64 %b) nounwind {
 entry:
 ; ALL-LABEL: cmpne:
 ; OCTEON: jr     $ra
 ; OCTEON: sne    $2, $4, $5
 ; MIPS64: xor    $[[T0:[0-9]+]], $4, $5
-; MIPS64: sltu   $[[T1:[0-9]+]], $zero, $[[T0]]
-; MIPS64: dsll   $[[T2:[0-9]+]], $[[T1]], 32
 ; MIPS64: jr     $ra
-; MIPS64: dsrl   $2, $[[T2]], 32
+; MIPS64: sltu   $2, $zero, $[[T0]]
   %res = icmp ne i64 %a, %b
   %res2 = zext i1 %res to i64
   ret i64 %res2
 }
 
 define i64 @cmpnei(i64 %a) nounwind {
 entry:
 ; ALL-LABEL: cmpnei:
 ; OCTEON: jr     $ra
 ; OCTEON: snei   $2, $4, 42
 ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42
 ; MIPS64: xor    $[[T1:[0-9]+]], $4, $[[T0]]
-; MIPS64: sltu   $[[T2:[0-9]+]], $zero, $[[T1]]
-; MIPS64: dsll   $[[T3:[0-9]+]], $[[T2]], 32
 ; MIPS64: jr     $ra
-; MIPS64: dsrl   $2, $[[T3]], 32
+; MIPS64: sltu   $2, $zero, $[[T1]]
   %res = icmp ne i64 %a, 42
   %res2 = zext i1 %res to i64
   ret i64 %res2
 }
 
 define i64 @bbit0(i64 %a) nounwind {
 entry:
 ; ALL-LABEL: bbit0: