[RegAllocFast] Clean-up. Remove redundant operations. NFC.

[skatkov]

llvm/lib/CodeGen/RegAllocFast.cpp

1305

EarlyClobber's sub regs will be handled here, so no need to do the same while we are processing EarlyClobbers at the end.

1354

We checked the condition here.

[arsenm]

llvm/lib/CodeGen/RegAllocFast.cpp

1207

This now may require new reallocation for each call

1357

This part LGTM

1409

This part LGTM

[arsenm]

Reverse ping

[MatzeB]

LGTM, though maybe re-consider the kill flag change unless you have a reason to add one...

llvm/lib/CodeGen/RegAllocFast.cpp

1357

We don't track liveness for reserved register (they're considered to be always alive). So I don't see what the point of adding a kill flag here is. I would expect it to not matter one way or another and not having a kill flag being less noise...

[MatzeB]

llvm/lib/CodeGen/RegAllocFast.cpp

1357

https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/CodeGen/TargetRegisterInfo.h#L520 for a comment on reserved regs.

[MatzeB]

llvm/lib/CodeGen/RegAllocFast.cpp

1207

I would expect more than 8 def operands to be very rare so I wouldn't really worry about reallocations... That said I also don't know why moving the SmallVector around helps anything...

[MatzeB]

llvm/lib/CodeGen/RegAllocFast.cpp

1357

And I just noticed the other comment, saying that we will never reach this point in the file for reserved regs. Makes sense!

[skatkov]

I'll try to look at it later this or may be earlier next week. I'm a bit detached from this topic and need some time to refresh.

[skatkov]

llvm/lib/CodeGen/RegAllocFast.cpp

1207

I agree, this is bad change. Originally I planned to add a support of statepoint instruction in the mode when it may have a lot of tied defs, And indeed this may require reallocation, so it is better to return this back.

[skatkov]

Update before landing

llvm/lib/CodeGen/RegAllocFast.cpp

if (HasDef) {
     if (HasVRegDef) {
       // Special handling for early clobbers, tied operands or subregister defs:
       // Compared to "normal" defs these:
       // - Must not use a register that is pre-assigned for a use operand.
       // - In order to solve tricky inline assembly constraints we change the
       //   heuristic to figure out a good operand order before doing
       //   assignments.
       if (NeedToAssignLiveThroughs) {
         DefOperandIndexes.clear();
         PhysRegUses.clear();
 
         // Track number of defs which may consume a register from the class.
         std::vector<unsigned> RegClassDefCounts(TRI->getNumRegClasses(), 0);
         assert(RegClassDefCounts[0] == 0);
 
         LLVM_DEBUG(dbgs() << "Need to assign livethroughs\n");
         for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
if (HasDef) {
     // defs first (we added them earlier in case of <def,read-undef>).
     for (signed I = MI.getNumOperands() - 1; I >= 0; --I) {
       MachineOperand &MO = MI.getOperand(I);
       if (!MO.isReg() || !MO.isDef())
         continue;
 
       // subreg defs don't free the full register. We left the subreg number
       // around as a marker in setPhysReg() to recognize this case here.
       if (MO.getSubReg() != 0) {
         MO.setSubReg(0);
         continue;
       }
 
       assert((!MO.isTied() || !isClobberedByRegMasks(MO.getReg())) &&
              "tied def assigned to clobbered register");
 
       // Do not free tied operands and early clobbers.
void RegAllocFast::allocateInstruction(MachineInstr &MI) {
   // Apply pre-assigned register uses to state.
   if (HasPhysRegUse) {
     for (MachineOperand &MO : MI.operands()) {
       if (!MO.isReg() || !MO.readsReg())
         continue;
       Register Reg = MO.getReg();
       if (!Reg.isPhysical())
         continue;
       if (MRI->isReserved(Reg))
         continue;
       bool displacedAny = usePhysReg(MI, Reg);
-      if (!displacedAny && !MRI->isReserved(Reg))
+      if (!displacedAny)
         MO.setIsKill(true);
     }
   }
 
   // Allocate virtreg uses and insert reloads as necessary.
   bool HasUndefUse = false;
   for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
     MachineOperand &MO = MI.getOperand(I);
if (HasUndefUse) {
     }
   }
 
   // Free early clobbers.
   if (HasEarlyClobber) {
     for (MachineOperand &MO : llvm::reverse(MI.operands())) {
       if (!MO.isReg() || !MO.isDef() || !MO.isEarlyClobber())
         continue;
-      // subreg defs don't free the full register. We left the subreg number
-      // around as a marker in setPhysReg() to recognize this case here.
-      if (MO.getSubReg() != 0) {
-        MO.setSubReg(0);
-        continue;
-      }
+      assert(!MO.getSubReg() && "should be already handled in def processing");
 
       Register Reg = MO.getReg();
       if (!Reg)
         continue;
       if (Reg.isVirtual()) {
         assert(!shouldAllocateRegister(Reg));
         continue;
       }