This is an archive of the discontinued LLVM Phabricator instance.

Differential D109183

[asan] Fixed link error by setting jump symbol to R_X86_64_PLT32.
ClosedPublic

Authored by kstoimenov on Sep 2 2021, 12:28 PM.

Details

Reviewers
vitalybuka
Commits
rGcf53c6c97106: [asan] Fixed link error by setting jump symbol to R_X86_64_PLT32.
Summary

Fixing this link error:
ld: error: relocation R_X86_64_PC32 cannot be used against symbol __asan_report_load...; recompile with -fPIC

Diff Detail

Event Timeline

kstoimenov created this revision.Sep 2 2021, 12:28 PM
Herald added subscribers: pengfei, hiraditya. · View Herald TranscriptSep 2 2021, 12:28 PM
kstoimenov requested review of this revision.Sep 2 2021, 12:28 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 2 2021, 12:28 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B122368: Diff 370363.Sep 2 2021, 12:59 PM
vitalybuka accepted this revision.Sep 2 2021, 1:08 PM

It should be visible in test? Can you please update one?

This revision is now accepted and ready to land.Sep 2 2021, 1:08 PM
kstoimenov updated this revision to Diff 370413.Sep 2 2021, 2:33 PM

Added tests.

kstoimenov updated this revision to Diff 370418.Sep 2 2021, 2:49 PM

Fixed a test.

This revision was landed with ongoing or failed builds.Sep 2 2021, 2:51 PM
Closed by commit rGcf53c6c97106: [asan] Fixed link error by setting jump symbol to R_X86_64_PLT32. (authored by kstoimenov). · Explain Why
This revision was automatically updated to reflect the committed changes.
kstoimenov added a commit: rGcf53c6c97106: [asan] Fixed link error by setting jump symbol to R_X86_64_PLT32..
Harbormaster completed remote builds in B122404: Diff 370418.Sep 2 2021, 3:29 PM

Revision Contents

PathSize
llvm/
lib/
Target/
X86/
3 lines
test/
CodeGen/
X86/
10 lines
10 lines

Diff 370419

llvm/lib/Target/X86/X86MCInstLower.cpp

Show First 20 Lines • Show All 1,520 Lines • ▼ Show 20 Linesvoid X86AsmPrinter::emitAsanReportError(Module &M, unsigned Reg,
MCSymbol *ReportError = OutContext.getOrCreateSymbol( MCSymbol *ReportError = OutContext.getOrCreateSymbol(
"__asan_report_" + Name + utostr(1ULL << AccessInfo.AccessSizeIndex)); "__asan_report_" + Name + utostr(1ULL << AccessInfo.AccessSizeIndex));
OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr) OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
.addReg(X86::RDI) .addReg(X86::RDI)
.addReg(X86::NoRegister + Reg), .addReg(X86::NoRegister + Reg),
STI); STI);
OutStreamer->emitInstruction( OutStreamer->emitInstruction(
MCInstBuilder(X86::JMP_1) MCInstBuilder(X86::JMP_1)
.addExpr(MCSymbolRefExpr::create(ReportError, OutContext)), .addExpr(MCSymbolRefExpr::create(ReportError, MCSymbolRefExpr::VK_PLT,
OutContext)),
STI); STI);
} }
void X86AsmPrinter::emitAsanMemaccessSymbols(Module &M) { void X86AsmPrinter::emitAsanMemaccessSymbols(Module &M) {
if (AsanMemaccessSymbols.empty()) if (AsanMemaccessSymbols.empty())
return; return;
const Triple &TT = TM.getTargetTriple(); const Triple &TT = TM.getTargetTriple();
▲ Show 20 Lines • Show All 1,337 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/asan-check-memaccess-add.ll

Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[EXTRA]]: ; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx ; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx ; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx ; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx ; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx ; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]] ; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi ; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store1 ; CHECK-NEXT: jmp __asan_report_store1@PLT
; CHECK: .type __asan_check_store2_rn[[RN2]],@function ; CHECK: .type __asan_check_store2_rn[[RN2]],@function
; CHECK-NEXT: .weak __asan_check_store2_rn[[RN2]] ; CHECK-NEXT: .weak __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: .hidden __asan_check_store2_rn[[RN2]] ; CHECK-NEXT: .hidden __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: __asan_check_store2_rn[[RN2]]: ; CHECK-NEXT: __asan_check_store2_rn[[RN2]]:
; CHECK-NEXT: movq [[REG:.*]], %r8 ; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8 ; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: movsbl 2147450880(%r8), %r8d ; CHECK-NEXT: movsbl 2147450880(%r8), %r8d
; CHECK-NEXT: testl %r8d, %r8d ; CHECK-NEXT: testl %r8d, %r8d
; CHECK-NEXT: jne [[EXTRA:.*]] ; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]: ; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]: ; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx ; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx ; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx ; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: addl $1, %ecx ; CHECK-NEXT: addl $1, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx ; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx ; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]] ; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi ; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store2 ; CHECK-NEXT: jmp __asan_report_store2@PLT
; CHECK: .type __asan_check_store4_rn[[RN4]],@function ; CHECK: .type __asan_check_store4_rn[[RN4]],@function
; CHECK-NEXT: .weak __asan_check_store4_rn[[RN4]] ; CHECK-NEXT: .weak __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: .hidden __asan_check_store4_rn[[RN4]] ; CHECK-NEXT: .hidden __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: __asan_check_store4_rn[[RN4]]: ; CHECK-NEXT: __asan_check_store4_rn[[RN4]]:
; CHECK-NEXT: movq [[REG:.*]], %r8 ; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8 ; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: movsbl 2147450880(%r8), %r8d ; CHECK-NEXT: movsbl 2147450880(%r8), %r8d
; CHECK-NEXT: testl %r8d, %r8d ; CHECK-NEXT: testl %r8d, %r8d
; CHECK-NEXT: jne [[EXTRA:.*]] ; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]: ; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]: ; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx ; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx ; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx ; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: addl $3, %ecx ; CHECK-NEXT: addl $3, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx ; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx ; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]] ; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi ; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store4 ; CHECK-NEXT: jmp __asan_report_store4@PLT
; CHECK: .type __asan_check_store8_rn[[RN8]],@function ; CHECK: .type __asan_check_store8_rn[[RN8]],@function
; CHECK-NEXT: .weak __asan_check_store8_rn[[RN8]] ; CHECK-NEXT: .weak __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: .hidden __asan_check_store8_rn[[RN8]] ; CHECK-NEXT: .hidden __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: __asan_check_store8_rn[[RN8]]: ; CHECK-NEXT: __asan_check_store8_rn[[RN8]]:
; CHECK-NEXT: movq [[REG:.*]], %r8 ; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8 ; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: cmpb $0, 2147450880(%r8) ; CHECK-NEXT: cmpb $0, 2147450880(%r8)
; CHECK-NEXT: jne [[FAIL:.*]] ; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]: ; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]: ; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi ; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store8 ; CHECK-NEXT: jmp __asan_report_store8@PLT
; CHECK: .type __asan_check_store16_rn[[RN16]],@function ; CHECK: .type __asan_check_store16_rn[[RN16]],@function
; CHECK-NEXT: .weak __asan_check_store16_rn[[RN16]] ; CHECK-NEXT: .weak __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: .hidden __asan_check_store16_rn[[RN16]] ; CHECK-NEXT: .hidden __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: __asan_check_store16_rn[[RN16]]: ; CHECK-NEXT: __asan_check_store16_rn[[RN16]]:
; CHECK-NEXT: movq [[REG:.*]], %r8 ; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8 ; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: cmpw $0, 2147450880(%r8) ; CHECK-NEXT: cmpw $0, 2147450880(%r8)
; CHECK-NEXT: jne [[FAIL:.*]] ; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]: ; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]: ; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi ; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store16 ; CHECK-NEXT: jmp __asan_report_store16@PLT
declare void @llvm.asan.check.memaccess(i8*, i32 immarg) declare void @llvm.asan.check.memaccess(i8*, i32 immarg)

llvm/test/CodeGen/X86/asan-check-memaccess-or.ll

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[EXTRA]]: ; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx ; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx ; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx ; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx ; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx ; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]] ; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi ; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store1 ; CHECK-NEXT: jmp __asan_report_store1@PLT
; CHECK: .type __asan_check_store2_rn[[RN2]],@function ; CHECK: .type __asan_check_store2_rn[[RN2]],@function
; CHECK-NEXT: .weak __asan_check_store2_rn[[RN2]] ; CHECK-NEXT: .weak __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: .hidden __asan_check_store2_rn[[RN2]] ; CHECK-NEXT: .hidden __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: __asan_check_store2_rn[[RN2]]: ; CHECK-NEXT: __asan_check_store2_rn[[RN2]]:
; CHECK-NEXT: movq [[REG:.*]], %r8 ; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8 ; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8 ; CHECK-NEXT: orq $17592186044416, %r8
; CHECK-NEXT: movb (%r8), %r8b ; CHECK-NEXT: movb (%r8), %r8b
; CHECK-NEXT: testb %r8b, %r8b ; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: jne [[EXTRA:.*]] ; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]: ; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]: ; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx ; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx ; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx ; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: addl $1, %ecx ; CHECK-NEXT: addl $1, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx ; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx ; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]] ; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi ; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store2 ; CHECK-NEXT: jmp __asan_report_store2@PLT
; CHECK: .type __asan_check_store4_rn[[RN4]],@function ; CHECK: .type __asan_check_store4_rn[[RN4]],@function
; CHECK-NEXT: .weak __asan_check_store4_rn[[RN4]] ; CHECK-NEXT: .weak __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: .hidden __asan_check_store4_rn[[RN4]] ; CHECK-NEXT: .hidden __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: __asan_check_store4_rn[[RN4]]: ; CHECK-NEXT: __asan_check_store4_rn[[RN4]]:
; CHECK-NEXT: movq [[REG:.*]], %r8 ; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8 ; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8 ; CHECK-NEXT: orq $17592186044416, %r8
; CHECK-NEXT: movb (%r8), %r8b ; CHECK-NEXT: movb (%r8), %r8b
; CHECK-NEXT: testb %r8b, %r8b ; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: jne [[EXTRA:.*]] ; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]: ; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]: ; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: pushq %rcx ; CHECK-NEXT: pushq %rcx
; CHECK-NEXT: movq [[REG]], %rcx ; CHECK-NEXT: movq [[REG]], %rcx
; CHECK-NEXT: andl $7, %ecx ; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: addl $3, %ecx ; CHECK-NEXT: addl $3, %ecx
; CHECK-NEXT: cmpl %r8d, %ecx ; CHECK-NEXT: cmpl %r8d, %ecx
; CHECK-NEXT: popq %rcx ; CHECK-NEXT: popq %rcx
; CHECK-NEXT: jl [[RET]] ; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi ; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store4 ; CHECK-NEXT: jmp __asan_report_store4@PLT
; CHECK: .type __asan_check_store8_rn[[RN8]],@function ; CHECK: .type __asan_check_store8_rn[[RN8]],@function
; CHECK-NEXT: .weak __asan_check_store8_rn[[RN8]] ; CHECK-NEXT: .weak __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: .hidden __asan_check_store8_rn[[RN8]] ; CHECK-NEXT: .hidden __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: __asan_check_store8_rn[[RN8]]: ; CHECK-NEXT: __asan_check_store8_rn[[RN8]]:
; CHECK-NEXT: movq [[REG:.*]], %r8 ; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8 ; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8{{.*}} ; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
; CHECK-NEXT: cmpb $0, (%r8) ; CHECK-NEXT: cmpb $0, (%r8)
; CHECK-NEXT: jne [[FAIL:.*]] ; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]: ; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]: ; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi ; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store8 ; CHECK-NEXT: jmp __asan_report_store8@PLT
; CHECK: .type __asan_check_store16_rn[[RN16]],@function ; CHECK: .type __asan_check_store16_rn[[RN16]],@function
; CHECK-NEXT: .weak __asan_check_store16_rn[[RN16]] ; CHECK-NEXT: .weak __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: .hidden __asan_check_store16_rn[[RN16]] ; CHECK-NEXT: .hidden __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: __asan_check_store16_rn[[RN16]]: ; CHECK-NEXT: __asan_check_store16_rn[[RN16]]:
; CHECK-NEXT: movq [[REG:.*]], %r8 ; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8 ; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8{{.*}} ; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
; CHECK-NEXT: cmpw $0, (%r8) ; CHECK-NEXT: cmpw $0, (%r8)
; CHECK-NEXT: jne [[FAIL:.*]] ; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]: ; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]: ; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi ; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store16 ; CHECK-NEXT: jmp __asan_report_store16@PLT
declare void @llvm.asan.check.memaccess(i8*, i32 immarg) declare void @llvm.asan.check.memaccess(i8*, i32 immarg)