[hexagon] Add system register, transfer support

[bcain]

Summary

This commit adds the system reg/regpair definitions and the corresponding register transfer instructions.

[sidneym]

LGTM

[bcain]

@kparzysz any concerns?

[bcain]

Updated to remove discrepancies with PRM.

[bcain]

Updated to address further PRM mismatches.

[bcain]

Previous upload was a stale patch, sorry!

Updating w/more corrections to reflect PRM.

[kparzysz]

LGTM. Thanks!

llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp

static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
                                              const void *Decoder);
 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
                                                const void *Decoder);
 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                  uint64_t Address,
                                                  const void *Decoder);
+static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder);
 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
                                                const void *Decoder);
 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
                                                  uint64_t Address,
                                                  const void *Decoder);
 static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
                                                    uint64_t Address,
                                                    const void *Decoder);
+static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
+                                                 uint64_t Address,
+                                                 const void *Decoder);
+
 
 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
                                        uint64_t Address, const void *Decoder);
 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
                                     uint64_t /*Address*/, const void *Decoder);
 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
                                     const void *Decoder);
 #include "HexagonDepDecoders.inc"
 #include "HexagonGenDisassemblerTables.inc"
if (Bits == 0)
     Bits = 15;
   uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
   uint32_t Extended = FullValue + Address;
   if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4))
     HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
   return MCDisassembler::Success;
 }
 
+static const uint16_t SysRegDecoderTable[] = {
+    Hexagon::SGP0,       Hexagon::SGP1,      Hexagon::STID,
+    Hexagon::ELR,        Hexagon::BADVA0,    Hexagon::BADVA1,
+    Hexagon::SSR,        Hexagon::CCR,       Hexagon::HTID,
+    Hexagon::BADVA,      Hexagon::IMASK,     Hexagon::S11,
+    Hexagon::S12,        Hexagon::S13,       Hexagon::S14,
+    Hexagon::S15,        Hexagon::EVB,       Hexagon::MODECTL,
+    Hexagon::SYSCFG,     Hexagon::S19,       Hexagon::S20,
+    Hexagon::VID,        Hexagon::S22,       Hexagon::S23,
+    Hexagon::S24,        Hexagon::S25,       Hexagon::S26,
+    Hexagon::CFGBASE,    Hexagon::DIAG,      Hexagon::REV,
+    Hexagon::PCYCLELO,   Hexagon::PCYCLEHI,  Hexagon::ISDBST,
+    Hexagon::ISDBCFG0,   Hexagon::ISDBCFG1,  Hexagon::S35,
+    Hexagon::BRKPTPC0,   Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1,
+    Hexagon::BRKPTCFG1,  Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT,
+    Hexagon::ISDBEN,     Hexagon::ISDBGPR,   Hexagon::S44,
+    Hexagon::S45,        Hexagon::S46,       Hexagon::S47,
+    Hexagon::PMUCNT0,    Hexagon::PMUCNT1,   Hexagon::PMUCNT2,
+    Hexagon::PMUCNT3,    Hexagon::PMUEVTCFG, Hexagon::PMUCFG,
+    Hexagon::S54,        Hexagon::S55,       Hexagon::S56,
+    Hexagon::S57,        Hexagon::S58,       Hexagon::S59,
+    Hexagon::S60,        Hexagon::S61,       Hexagon::S62,
+    Hexagon::S63,        Hexagon::S64,       Hexagon::S65,
+    Hexagon::S66,        Hexagon::S67,       Hexagon::S68,
+    Hexagon::S69,        Hexagon::S70,       Hexagon::S71,
+    Hexagon::S72,        Hexagon::S73,       Hexagon::S74,
+    Hexagon::S75,        Hexagon::S76,       Hexagon::S77,
+    Hexagon::S78,        Hexagon::S79,       Hexagon::S80,
+};
+
+static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
+                                               uint64_t /*Address*/,
+                                               const void *Decoder) {
+  if (RegNo >= sizeof(SysRegDecoderTable) / sizeof(SysRegDecoderTable[0]))
+    return MCDisassembler::Fail;
+
+  if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister)
+    return MCDisassembler::Fail;
+
+  unsigned Register = SysRegDecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Register));
+  return MCDisassembler::Success;
+}
+
+static const uint16_t SysReg64DecoderTable[] = {
+    Hexagon::SGP1_0, Hexagon::S3_2,   Hexagon::S5_4,   Hexagon::S7_6,
+    Hexagon::S9_8,   Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14,
+    Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22,
+    Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30,
+    Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,
+    Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,
+    Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,
+    Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,
+    Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,
+    Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
+};
+
+static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
+                                                 uint64_t /*Address*/,
+                                                 const void *Decoder) {
+  RegNo = RegNo >> 1;
+  if (RegNo >= sizeof(SysReg64DecoderTable) / sizeof(SysReg64DecoderTable[0]))
+    return MCDisassembler::Fail;
+
+  if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister)
+    return MCDisassembler::Fail;
+
+  unsigned Register = SysReg64DecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Register));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                  uint64_t /*Address*/,
                                                  const void *Decoder) {
   using namespace Hexagon;
 
   static const MCPhysReg GuestRegDecoderTable[] = {
     /*  0 */ GELR,      GSR,        GOSP,       G3,
     /*  4 */ G4,        G5,         G6,         G7,

llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td

 class Enc_7b7ba8 : OpcodeHexagon {
   bits <2> Qu4;
   let Inst{9-8} = Qu4{1-0};
   bits <5> Rt32;
   let Inst{20-16} = Rt32{4-0};
   bits <5> Vd32;
   let Inst{4-0} = Vd32{4-0};
 }
+class Enc_7d1542 : OpcodeHexagon {
+  bits <7> Ss128;
+  let Inst{22-16} = Ss128{6-0};
+  bits <5> Rd32;
+  let Inst{4-0} = Rd32{4-0};
+}
 class Enc_7e5a82 : OpcodeHexagon {
   bits <5> Ii;
   let Inst{12-8} = Ii{4-0};
   bits <5> Rss32;
   let Inst{20-16} = Rss32{4-0};
   bits <5> Rdd32;
   let Inst{4-0} = Rdd32{4-0};
 }
class Enc_8e583a : OpcodeHexagon {
   let Inst{7-1} = Ii{8-2};
   bits <4> Rs16;
   let Inst{19-16} = Rs16{3-0};
   bits <5> n1;
   let Inst{28-28} = n1{4-4};
   let Inst{25-23} = n1{3-1};
   let Inst{13-13} = n1{0-0};
 }
+class Enc_8f7633 : OpcodeHexagon {
+  bits <5> Rs32;
+  let Inst{20-16} = Rs32{4-0};
+  bits <7> Sd128;
+  let Inst{6-0} = Sd128{6-0};
+}
 class Enc_90cd8b : OpcodeHexagon {
   bits <5> Rss32;
   let Inst{20-16} = Rss32{4-0};
   bits <5> Rd32;
   let Inst{4-0} = Rd32{4-0};
 }
 class Enc_91b9fe : OpcodeHexagon {
   bits <5> Ii;
class Enc_a6853f : OpcodeHexagon {
   let Inst{13-13} = n1{0-0};
 }
 class Enc_a6ce9c : OpcodeHexagon {
   bits <6> Ii;
   let Inst{3-0} = Ii{5-2};
   bits <4> Rs16;
   let Inst{7-4} = Rs16{3-0};
 }
+class Enc_a705fc : OpcodeHexagon {
+  bits <5> Rss32;
+  let Inst{20-16} = Rss32{4-0};
+  bits <7> Sdd128;
+  let Inst{6-0} = Sdd128{6-0};
+}
 class Enc_a7341a : OpcodeHexagon {
   bits <5> Vu32;
   let Inst{12-8} = Vu32{4-0};
   bits <5> Vv32;
   let Inst{20-16} = Vv32{4-0};
   bits <5> Vx32;
   let Inst{4-0} = Vx32{4-0};
 }

 class Enc_e26546 : OpcodeHexagon {
   bits <5> Ii;
   let Inst{6-3} = Ii{4-1};
   bits <3> Nt8;
   let Inst{10-8} = Nt8{2-0};
   bits <5> Rx32;
   let Inst{20-16} = Rx32{4-0};
 }
+class Enc_e32517 : OpcodeHexagon {
+  bits <7> Sss128;
+  let Inst{22-16} = Sss128{6-0};
+  bits <5> Rdd32;
+  let Inst{4-0} = Rdd32{4-0};
+}
 class Enc_e38e1f : OpcodeHexagon {
   bits <8> Ii;
   let Inst{12-5} = Ii{7-0};
   bits <2> Pu4;
   let Inst{22-21} = Pu4{1-0};
   bits <5> Rs32;
   let Inst{20-16} = Rs32{4-0};
   bits <5> Rd32;

llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td

 (outs),
 (ins),
 "syncht",
 tc_77f94a5e, TypeST>, Enc_e3b0c4 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-16} = 0b1010100001000000;
 let isSolo = 1;
 }
+def Y2_tfrscrr : HInst<
+(outs IntRegs:$Rd32),
+(ins SysRegs:$Ss128),
+"$Rd32 = $Ss128",
+tc_fae9dfa5, TypeCR>, Enc_7d1542 {
+let Inst{13-5} = 0b000000000;
+let Inst{31-23} = 0b011011101;
+let hasNewValue = 1;
+let opNewValue = 0;
+}
+def Y2_tfrsrcr : HInst<
+(outs SysRegs:$Sd128),
+(ins IntRegs:$Rs32),
+"$Sd128 = $Rs32",
+tc_6ae3426b, TypeCR>, Enc_8f7633 {
+let Inst{13-7} = 0b0000000;
+let Inst{31-21} = 0b01100111000;
+let hasNewValue = 1;
+let opNewValue = 0;
+}
 def Y2_wait : HInst<
 (outs),
 (ins IntRegs:$Rs32),
 "wait($Rs32)",
 tc_2c3e17fc, TypeCR>, Enc_ecbcc8, Requires<[HasV65]> {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-21} = 0b01100100010;
 let isSolo = 1;
 }
 def Y4_l2fetch : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32),
 "l2fetch($Rs32,$Rt32)",
 tc_a3070909, TypeST>, Enc_ca3887 {
 let Inst{7-0} = 0b00000000;
 let Inst{13-13} = 0b0;
 let Inst{31-21} = 0b10100110000;
 let isSoloAX = 1;
 let hasSideEffects = 1;
 let mayStore = 1;
 }
+def Y4_tfrscpp : HInst<
+(outs DoubleRegs:$Rdd32),
+(ins SysRegs64:$Sss128),
+"$Rdd32 = $Sss128",
+tc_fae9dfa5, TypeCR>, Enc_e32517 {
+let Inst{13-5} = 0b000000000;
+let Inst{31-23} = 0b011011110;
+}
+def Y4_tfrspcp : HInst<
+(outs SysRegs64:$Sdd128),
+(ins DoubleRegs:$Rss32),
+"$Sdd128 = $Rss32",
+tc_6ae3426b, TypeCR>, Enc_a705fc {
+let Inst{13-7} = 0b0000000;
+let Inst{31-21} = 0b01101101000;
+let hasNewValue = 1;
+let opNewValue = 0;
+}
 def Y4_trace : HInst<
 (outs),
 (ins IntRegs:$Rs32),
 "trace($Rs32)",
 tc_d7718fbe, TypeCR>, Enc_ecbcc8 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-21} = 0b01100010010;
 let isSoloAX = 1;

llvm/lib/Target/Hexagon/HexagonRegisterInfo.td

let Namespace = "Hexagon" in {
 
   class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs,
                          list<string> alt = []> :
         RegisterWithSubRegs<n, subregs> {
     let AltNames = alt;
     let HWEncoding{4-0} = num;
   }
 
+  class HexagonSys<bits<7> num, string n, list<string> alt = [],
+                   list<Register> alias = []> : Register<n, alt> {
+    let Aliases = alias;
+    let HWEncoding{6-0} = num;
+  }
+
+  class HexagonDoubleSys<bits<7> num, string n, list<Register> subregs,
+                         list<string> alt = []> :
+        RegisterWithSubRegs<n, subregs> {
+    let AltNames = alt;
+    let HWEncoding{6-0} = num;
+  }
+
   // Registers are identified with 5-bit ID numbers.
   // Ri - 32-bit integer registers.
   class Ri<bits<5> num, string n, list<string> alt = []> :
         HexagonReg<num, n, alt>;
 
   // Rp - false/pseudo registers.  These registers are used
   // to provide a distinct set of aliases for both styles of vector
   // register pairs without encountering subregister indexing constraints.
let Namespace = "Hexagon" in {
 
   // Rcc - 64-bit control registers.
   class Rcc<bits<5> num, string n, list<Register> subregs,
             list<string> alt = []> :
         HexagonDoubleReg<num, n, subregs, alt> {
     let SubRegs = subregs;
   }
 
+  // Rs - system registers
+  class Rs<bits<7> num, string n,
+           list<string> alt = [], list<Register> alias = []> :
+        HexagonSys<num, n, alt, alias>;
+
+  // Rss - 64-bit system registers.
+  class Rss<bits<7> num, string n, list<Register> subregs,
+            list<string> alt = []> :
+        HexagonDoubleSys<num, n, subregs, alt> {
+    let SubRegs = subregs;
+  }
+
   // Mx - address modifier registers
   class Mx<bits<1> num, string n> : Register<n, []> {
     let HWEncoding{0} = num;
   }
 
   // Rg - Guest/Hypervisor registers
   class Rg<bits<5> num, string n,
            list<string> alt = [], list<Register> alias = []> :
let Namespace = "Hexagon" in {
   }
 
   // Vector Predicate registers.
   def Q0 : Rq<0, "q0">, DwarfRegNum<[131]>;
   def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>;
   def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>;
   def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>;
 
+  // System registers.
+  def SGP0     :  Rs<0,  "sgp0",       ["s0"]>,  DwarfRegNum<[144]>;
+  def SGP1     :  Rs<1,  "sgp1",       ["s1"]>,  DwarfRegNum<[145]>;
+  def STID     :  Rs<2,  "stid",       ["s2"]>,  DwarfRegNum<[146]>;
+  def ELR      :  Rs<3,  "elr",        ["s3"]>,  DwarfRegNum<[147]>;
+  def BADVA0   :  Rs<4,  "badva0",     ["s4"]>,  DwarfRegNum<[148]>;
+  def BADVA1   :  Rs<5,  "badva1",     ["s5"]>,  DwarfRegNum<[149]>;
+  def SSR      :  Rs<6,  "ssr",        ["s6"]>,  DwarfRegNum<[150]>;
+  def CCR      :  Rs<7,  "ccr",        ["s7"]>,  DwarfRegNum<[151]>;
+  def HTID     :  Rs<8,  "htid",       ["s8"]>,  DwarfRegNum<[152]>;
+  def BADVA    :  Rs<9,  "badva",      ["s9"]>,  DwarfRegNum<[153]>;
+  def IMASK    :  Rs<10, "imask",      ["s10"]>, DwarfRegNum<[154]>;
+  def S11      :  Rs<11, "s11">,                 DwarfRegNum<[155]>;
+  def S12      :  Rs<12, "s12">,                 DwarfRegNum<[156]>;
+  def S13      :  Rs<13, "s13">,                 DwarfRegNum<[157]>;
+  def S14      :  Rs<14, "s14">,                 DwarfRegNum<[158]>;
+  def S15      :  Rs<15, "s15">,                 DwarfRegNum<[159]>;
+  def EVB      :  Rs<16, "evb",        ["s16"]>, DwarfRegNum<[160]>;
+  def MODECTL  :  Rs<17, "modectl",    ["s17"]>, DwarfRegNum<[161]>;
+  def SYSCFG   :  Rs<18, "syscfg",     ["s18"]>, DwarfRegNum<[162]>;
+  def S19      :  Rs<19, "s19",        ["s19"]>, DwarfRegNum<[163]>;
+  def S20      :  Rs<20, "s20",        ["s20"]>, DwarfRegNum<[164]>;
+  def VID      :  Rs<21, "vid",        ["s21"]>, DwarfRegNum<[165]>;
+  def S22      :  Rs<22, "s22",        ["s22"]>, DwarfRegNum<[166]>;
+  def S23      :  Rs<23, "s23">,                 DwarfRegNum<[167]>;
+  def S24      :  Rs<24, "s24">,                 DwarfRegNum<[168]>;
+  def S25      :  Rs<25, "s25">,                 DwarfRegNum<[169]>;
+  def S26      :  Rs<26, "s26">,                 DwarfRegNum<[170]>;
+  def CFGBASE  :  Rs<27, "cfgbase",    ["s27"]>, DwarfRegNum<[171]>;
+  def DIAG     :  Rs<28, "diag",       ["s28"]>, DwarfRegNum<[172]>;
+  def REV      :  Rs<29, "rev",        ["s29"]>, DwarfRegNum<[173]>;
+  def PCYCLELO :  Rs<30, "pcyclelo",   ["s30"]>, DwarfRegNum<[174]>;
+  def PCYCLEHI :  Rs<31, "pcyclehi",   ["s31"]>, DwarfRegNum<[175]>;
+  def ISDBST   :  Rs<32, "isdbst",     ["s32"]>, DwarfRegNum<[176]>;
+  def ISDBCFG0 :  Rs<33, "isdbcfg0",   ["s33"]>, DwarfRegNum<[177]>;
+  def ISDBCFG1 :  Rs<34, "isdbcfg1",   ["s34"]>, DwarfRegNum<[178]>;
+  def S35      :  Rs<35, "s35">,                 DwarfRegNum<[179]>;
+  def BRKPTPC0 :  Rs<36, "brkptpc0",   ["s36"]>, DwarfRegNum<[180]>;
+  def BRKPTCFG0:  Rs<37, "brkptcfg0",  ["s37"]>, DwarfRegNum<[181]>;
+  def BRKPTPC1 :  Rs<38, "brkptpc1",   ["s38"]>, DwarfRegNum<[182]>;
+  def BRKPTCFG1:  Rs<39, "brkptcfg1",  ["s39"]>, DwarfRegNum<[183]>;
+  def ISDBMBXIN:  Rs<40, "isdbmbxin",  ["s40"]>, DwarfRegNum<[184]>;
+  def ISDBMBXOUT: Rs<41, "isdbmbxout", ["s41"]>, DwarfRegNum<[185]>;
+  def ISDBEN:     Rs<42, "isdben",     ["s42"]>, DwarfRegNum<[186]>;
+  def ISDBGPR:    Rs<43, "isdbgpr",    ["s43"]>, DwarfRegNum<[187]>;
+  def S44:        Rs<44, "s44">,                 DwarfRegNum<[188]>;
+  def S45:        Rs<45, "s45">,                 DwarfRegNum<[189]>;
+  def S46:        Rs<46, "s46">,                 DwarfRegNum<[190]>;
+  def S47:        Rs<47, "s47">,                 DwarfRegNum<[191]>;
+  def PMUCNT0:    Rs<48, "pmucnt0",    ["s48"]>, DwarfRegNum<[192]>;
+  def PMUCNT1:    Rs<49, "pmucnt1",    ["s49"]>, DwarfRegNum<[193]>;
+  def PMUCNT2:    Rs<50, "pmucnt2",    ["s50"]>, DwarfRegNum<[194]>;
+  def PMUCNT3:    Rs<51, "pmucnt3",    ["s51"]>, DwarfRegNum<[195]>;
+  def PMUEVTCFG:  Rs<52, "pmuevtcfg",  ["s52"]>, DwarfRegNum<[196]>;
+  def PMUCFG:     Rs<53, "pmucfg",     ["s53"]>, DwarfRegNum<[197]>;
+  def S54:        Rs<54, "s54">,                 DwarfRegNum<[198]>;
+  def S55:        Rs<55, "s55">,                 DwarfRegNum<[199]>;
+  def S56:        Rs<56, "s56">,                 DwarfRegNum<[200]>;
+  def S57:        Rs<57, "s57">,                 DwarfRegNum<[201]>;
+  def S58:        Rs<58, "s58">,                 DwarfRegNum<[202]>;
+  def S59:        Rs<59, "s59">,                 DwarfRegNum<[203]>;
+  def S60:        Rs<60, "s60">,                 DwarfRegNum<[204]>;
+  def S61:        Rs<61, "s61">,                 DwarfRegNum<[205]>;
+  def S62:        Rs<62, "s62">,                 DwarfRegNum<[206]>;
+  def S63:        Rs<63, "s63">,                 DwarfRegNum<[207]>;
+  def S64:        Rs<64, "s64">,                 DwarfRegNum<[208]>;
+  def S65:        Rs<65, "s65">,                 DwarfRegNum<[209]>;
+  def S66:        Rs<66, "s66">,                 DwarfRegNum<[210]>;
+  def S67:        Rs<67, "s67">,                 DwarfRegNum<[211]>;
+  def S68:        Rs<68, "s68">,                 DwarfRegNum<[212]>;
+  def S69:        Rs<69, "s69">,                 DwarfRegNum<[213]>;
+  def S70:        Rs<70, "s70">,                 DwarfRegNum<[214]>;
+  def S71:        Rs<71, "s71">,                 DwarfRegNum<[215]>;
+  def S72:        Rs<72, "s72">,                 DwarfRegNum<[216]>;
+  def S73:        Rs<73, "s73">,                 DwarfRegNum<[217]>;
+  def S74:        Rs<74, "s74">,                 DwarfRegNum<[218]>;
+  def S75:        Rs<75, "s75">,                 DwarfRegNum<[219]>;
+  def S76:        Rs<76, "s76">,                 DwarfRegNum<[220]>;
+  def S77:        Rs<77, "s77">,                 DwarfRegNum<[221]>;
+  def S78:        Rs<78, "s78">,                 DwarfRegNum<[222]>;
+  def S79:        Rs<79, "s79">,                 DwarfRegNum<[223]>;
+  def S80:        Rs<80, "s80">,                 DwarfRegNum<[224]>;
+
+  // System Register Pair
+  let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
+    def SGP1_0 : Rss<0,  "s1:0",  [SGP0, SGP1], ["sgp1:0"]>, DwarfRegNum<[144]>;
+    def S3_2   : Rss<2,  "s3:2",  [STID, ELR]>,              DwarfRegNum<[146]>;
+    def S5_4   : Rss<4,  "s5:4",  [BADVA0, BADVA1], ["badva1:0"]>,
+                                                             DwarfRegNum<[148]>;
+    def S7_6   : Rss<6,  "s7:6",  [SSR, CCR], ["ccr:ssr"]>,  DwarfRegNum<[150]>;
+    def S9_8   : Rss<8,  "s9:8",  [HTID, BADVA]>,            DwarfRegNum<[152]>;
+    def S11_10 : Rss<10, "s11:10", [IMASK, S11]>,            DwarfRegNum<[154]>;
+    def S13_12 : Rss<12, "s13:12", [S12, S13]>,              DwarfRegNum<[156]>;
+    def S15_14 : Rss<14, "s15:14", [S14, S15]>,              DwarfRegNum<[158]>;
+    def S17_16 : Rss<16, "s17:16", [EVB, MODECTL]>,          DwarfRegNum<[160]>;
+    def S19_18 : Rss<18, "s19:18", [SYSCFG, S19]>,           DwarfRegNum<[162]>;
+    def S21_20 : Rss<20, "s21:20", [S20, VID]>,              DwarfRegNum<[164]>;
+    def S23_22 : Rss<22, "s23:22", [S22, S23]>,              DwarfRegNum<[166]>;
+    def S25_24 : Rss<24, "s25:24", [S24, S25]>,              DwarfRegNum<[168]>;
+    def S27_26 : Rss<26, "s27:26", [S26, CFGBASE]>,          DwarfRegNum<[170]>;
+    def S29_28 : Rss<28, "s29:28", [DIAG, REV]>,             DwarfRegNum<[172]>;
+    def S31_30 : Rss<30, "s31:30", [PCYCLELO, PCYCLEHI], ["pcycle"]>,    DwarfRegNum<[174]>;
+    def S33_32 : Rss<32, "s33:32", [ISDBST, ISDBCFG0]>,      DwarfRegNum<[176]>;
+    def S35_34 : Rss<34, "s35:34", [ISDBCFG1, S35]>,    DwarfRegNum<[178]>;
+    def S37_36 : Rss<36, "s37:36", [BRKPTPC0, BRKPTCFG0]>,   DwarfRegNum<[180]>;
+    def S39_38 : Rss<38, "s39:38", [BRKPTPC1, BRKPTCFG1]>,   DwarfRegNum<[182]>;
+    def S41_40 : Rss<40, "s41:40", [ISDBMBXIN, ISDBMBXOUT]>, DwarfRegNum<[184]>;
+    def S43_42 : Rss<42, "s43:42", [ISDBEN, ISDBGPR]>,       DwarfRegNum<[186]>;
+    def S45_44 : Rss<44, "s45:44", [S44, S45]>,              DwarfRegNum<[188]>;
+    def S47_46 : Rss<46, "s47:46", [S46, S47]>,              DwarfRegNum<[190]>;
+    def S49_48 : Rss<48, "s49:48", [PMUCNT0, PMUCNT1]>,      DwarfRegNum<[192]>;
+    def S51_50 : Rss<50, "s51:50", [PMUCNT2, PMUCNT3]>,      DwarfRegNum<[194]>;
+    def S53_52 : Rss<52, "s53:52", [PMUEVTCFG, PMUCFG]>,     DwarfRegNum<[196]>;
+    def S55_54 : Rss<54, "s55:54", [S54, S55]>,              DwarfRegNum<[198]>;
+    def S57_56 : Rss<56, "s57:56", [S56, S57]>,              DwarfRegNum<[200]>;
+    def S59_58 : Rss<58, "s59:58", [S58, S59]>,              DwarfRegNum<[202]>;
+    def S61_60 : Rss<60, "s61:60", [S60, S61]>,              DwarfRegNum<[204]>;
+    def S63_62 : Rss<62, "s63:62", [S62, S63]>,              DwarfRegNum<[206]>;
+    def S65_64 : Rss<64, "s65:64", [S64, S65]>,              DwarfRegNum<[208]>;
+    def S67_66 : Rss<66, "s67:66", [S66, S67]>,              DwarfRegNum<[210]>;
+    def S69_68 : Rss<68, "s69:68", [S68, S69]>,              DwarfRegNum<[212]>;
+    def S71_70 : Rss<70, "s71:70", [S70, S71]>,              DwarfRegNum<[214]>;
+    def S73_72 : Rss<72, "s73:72", [S72, S73]>,              DwarfRegNum<[216]>;
+    def S75_74 : Rss<74, "s75:74", [S74, S75]>,              DwarfRegNum<[218]>;
+    def S77_76 : Rss<76, "s77:76", [S77, S76]>,              DwarfRegNum<[219]>;
+    def S79_78 : Rss<78, "s79:78", [S79, S78]>,              DwarfRegNum<[220]>;
+  }
+
   // Guest Registers
   def GELR:      Rg<0,  "gelr", ["g0"]>,       DwarfRegNum<[220]>;
   def GSR:       Rg<1,  "gsr", ["g1"]>,        DwarfRegNum<[221]>;
   def GOSP:      Rg<2,  "gosp", ["g2"]>,       DwarfRegNum<[222]>;
   def G3:        Rg<3,  "gbadva", ["g3"]>,     DwarfRegNum<[223]>;
   def G4:        Rg<4,  "g4">,                 DwarfRegNum<[224]>;
   def G5:        Rg<5,  "g5">,                 DwarfRegNum<[225]>;
   def G6:        Rg<6,  "g6">,                 DwarfRegNum<[226]>;

 def GuestRegs64 : RegisterClass<"Hexagon", [i64], 64,
   (add G1_0, G3_2,
        G5_4, G7_6, G9_8, G11_10, G13_12, G15_14,
        G17_16, G19_18,
        G21_20, G23_22,
        G25_24, G27_26, G29_28,
        G31_30)>;
 
+let Size = 32, isAllocatable = 0 in
+def SysRegs : RegisterClass<"Hexagon", [i32], 32,
+  (add SGP0, SGP1, STID, ELR, BADVA0, BADVA1,
+       SSR, CCR, HTID, BADVA, IMASK,
+       S11, S12, S13, S14, S15,
+       S19, S23, S25,
+       EVB, MODECTL, SYSCFG, S20, VID, S22, S24,
+       S26, CFGBASE, DIAG, REV, PCYCLEHI,
+       PCYCLELO, ISDBST, ISDBCFG0, ISDBCFG1, S35,
+       BRKPTPC0, BRKPTCFG0, BRKPTPC1, BRKPTCFG1,
+       ISDBMBXIN, ISDBMBXOUT, ISDBEN, ISDBGPR,
+       S44, S45, S46, S47,
+       PMUCNT0, PMUCNT1, PMUCNT2, PMUCNT3,
+       PMUEVTCFG, PMUCFG, S54, S55, S56, S57,
+       S58, S59, S60, S61, S62, S63, S64, S65, S66, S67,
+       S68, S69, S70, S71, S72, S73, S74, S75, S76, S77,
+       S78, S79, S80
+       )>;
+
+let Size = 64, isAllocatable = 0 in
+def SysRegs64 : RegisterClass<"Hexagon", [i64], 64,
+  (add SGP1_0,
+       S3_2, S5_4, S7_6, S9_8,
+       S11_10, S13_12, S15_14,
+       S17_16, S19_18, S21_20,
+       S23_22, S25_24,
+       S27_26, S29_28, S31_30, S33_32, S35_34,
+       S37_36, S39_38, S41_40, S43_42, S45_44,
+       S47_46, S49_48, S51_50, S53_52,
+       S55_54, S57_56, S59_58,
+       S61_60, S63_62, S65_64, S67_66, S69_68,
+       S71_70, S73_72, S75_74, S77_76, S79_78
+       )>;
+
 // These registers are new for v62 and onward.
 // The function RegisterMatchesArch() uses this list for validation.
 let isAllocatable = 0 in
 def V62Regs : RegisterClass<"Hexagon", [i32], 32,
   (add FRAMELIMIT, FRAMEKEY,   C17_16, PKTCOUNTLO, PKTCOUNTHI, PKTCOUNT,
        UTIMERLO,   UTIMERHI,   UTIMER)>;
 
 // These registers are new for v65 and onward.
 let Size = 32, isAllocatable = 0 in
 def V65Regs : RegisterClass<"Hexagon", [i32], 32, (add VTMP)>;
 
 
 def HexagonCSR
   : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23,
                          R24, R25, R26, R27)>;

llvm/test/MC/Hexagon/sysregs.s

+# RUN: llvm-mc -arch=hexagon -filetype=asm %s | FileCheck %s
+#
+
+         r1:0=s75:74
+# CHECK: r1:0 = s75:74
+         r1:0=s73:72
+# CHECK: r1:0 = s73:72
+         r1:0=s71:70
+# CHECK: r1:0 = s71:70
+         r1:0=s69:68
+# CHECK: r1:0 = s69:68
+         r1:0=s67:66
+# CHECK: r1:0 = s67:66
+         r1:0=s65:64
+# CHECK: r1:0 = s65:64
+         r1:0=s63:62
+# CHECK: r1:0 = s63:62
+         r1:0=s61:60
+# CHECK: r1:0 = s61:60
+         r1:0=s53:52
+# CHECK: r1:0 = s53:52
+         r1:0=s51:50
+# CHECK: r1:0 = s51:50
+         r1:0=s49:48
+# CHECK: r1:0 = s49:48
+         r1:0=s47:46
+# CHECK: r1:0 = s47:46
+         r1:0=s45:44
+# CHECK: r1:0 = s45:44
+         r1:0=s43:42
+# CHECK: r1:0 = s43:42
+         r1:0=s41:40
+# CHECK: r1:0 = s41:40
+         r1:0=s39:38
+# CHECK: r1:0 = s39:38
+         r1:0=s37:36
+# CHECK: r1:0 = s37:36
+         r1:0=s31:30
+# CHECK: r1:0 = s31:30
+         r1:0=c1:0
+# CHECK: r1:0 = c1:0
+         r1:0=s35:34
+# CHECK: r1:0 = s35:34
+         r1:0=s33:32
+# CHECK: r1:0 = s33:32
+         r1:0=s31:30
+# CHECK: r1:0 = s31:30
+         r1:0=s29:28
+# CHECK: r1:0 = s29:28
+         r1:0=s27:26
+# CHECK: r1:0 = s27:26
+         r1:0=s21:20
+# CHECK: r1:0 = s21:20
+         r1:0=s19:18
+# CHECK: r1:0 = s19:18
+         r1:0=s17:16
+# CHECK: r1:0 = s17:16
+         r1:0=s9:8
+# CHECK: r1:0 = s9:8
+         r1:0=s7:6
+# CHECK: r1:0 = s7:6
+         r1:0=s5:4
+# CHECK: r1:0 = s5:4
+         r1:0=s3:2
+# CHECK: r1:0 = s3:2
+         r1=s54
+# CHECK: r1 = s54
+         r0=s59
+# CHECK: r0 = s59
+         r0=s44
+# CHECK: r0 = s44
+         r0=s45
+# CHECK: r0 = s45
+         r0=s46
+# CHECK: r0 = s46
+         r0=s47
+# CHECK: r0 = s47
+
+         r0=s56
+# CHECK: r0 = s56
+
+         r1:0=pcycle
+# CHECK: r1:0 = s31:30

llvm/test/MC/Hexagon/sysregs2.s

+# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+#
+
+            sgp1:0=r1:0
+# CHECK:  { s1:0 = r1:0 }
+           s3:2=r7:6
+# CHECK: { s3:2 = r7:6 }
+           badva1:0=r11:10
+# CHECK: { s5:4 = r11:10 }
+           s7:6=r13:12
+# CHECK: { s7:6 = r13:12 }
+           r1:0=s9:8
+# CHECK: { r1:0 = s9:8 }
+           r1:0=s17:16
+# CHECK: { r1:0 = s17:16 }
+           r3:2=s21:20
+# CHECK: { r3:2 = s21:20 }
+           r3:2=s27:26
+# CHECK: { r3:2 = s27:26 }
+           r29:28=s29:28
+# CHECK: { r29:28 = s29:28 }
+           s31:30=r17:16
+# CHECK: { s31:30 = r17:16 }
+           s37:36=r1:0
+# CHECK: { s37:36 = r1:0 }
+           s39:38=r1:0
+# CHECK: { s39:38 = r1:0 }
+           r1:0 =s41:40
+# CHECK: { r1:0 = s41:40 }
+           s43:42=r7:6
+# CHECK: { s43:42 = r7:6 }
+           s45:44=r9:8
+# CHECK: { s45:44 = r9:8 }
+           s47:46=r17:16
+# CHECK: { s47:46 = r17:16 }
+           s49:48=r19:18
+# CHECK: { s49:48 = r19:18 }
+           s51:50=r27:26
+# CHECK: { s51:50 = r27:26 }
+           s53:52=r23:22
+# CHECK: { s53:52 = r23:22 }
+           s61:60=r21:20
+# CHECK: { s61:60 = r21:20 }
+           s63:62=r5:4
+# CHECK: { s63:62 = r5:4 }
+
+# The following were added for Bug 13858
+
+           r10=sgp0
+# CHECK: { r10 = sgp0 }
+           r10=sgp1
+# CHECK: { r10 = sgp1 }
+           r10=stid
+# CHECK: { r10 = stid }
+           r10=elr
+# CHECK: { r10 = elr }
+           r10=badva0
+# CHECK: { r10 = badva0 }
+           r10=badva1
+# CHECK: { r10 = badva1 }
+           r10=ssr
+# CHECK: { r10 = ssr }
+           r10=ccr
+# CHECK: { r10 = ccr }
+           r10=htid
+# CHECK: { r10 = htid }
+           r10=badva
+# CHECK: { r10 = badva }
+           r10=imask
+# CHECK: { r10 = imask }
+           r10=s11
+# CHECK: { r10 = s11 }
+           r10=evb
+# CHECK: { r10 = evb }
+           r10=modectl
+# CHECK: { r10 = modectl }
+           r10=syscfg
+# CHECK: { r10 = syscfg }
+           r10=s20
+# CHECK: { r10 = s20 }
+           r10=vid
+# CHECK: { r10 = vid }
+           r10=s22
+# CHECK: { r10 = s22 }
+           r10=cfgbase
+# CHECK: { r10 = cfgbase }
+           r10=diag
+# CHECK: { r10 = diag }
+           r10=rev
+# CHECK: { r10 = rev }
+           r10=pcyclelo
+# CHECK: { r10 = pcyclelo }
+           r10=pcyclehi
+# CHECK: { r10 = pcyclehi }
+           r10=isdbst
+# CHECK: { r10 = isdbst }
+           r10=isdbcfg0
+# CHECK: { r10 = isdbcfg0 }
+           r10=isdbcfg1
+# CHECK: { r10 = isdbcfg1 }
+           r10=s35
+# CHECK: { r10 = s35 }
+           r10=brkptpc0
+# CHECK: { r10 = brkptpc0 }
+           r10=brkptcfg0
+# CHECK: { r10 = brkptcfg0 }
+           r10=brkptpc1
+# CHECK: { r10 = brkptpc1 }
+           r10=brkptcfg1
+# CHECK: { r10 = brkptcfg1 }
+           r10=isdbmbxin
+# CHECK: { r10 = isdbmbxin }
+           r10=isdbmbxout
+# CHECK: { r10 = isdbmbxout }
+           r10=isdben
+# CHECK: { r10 = isdben }
+           r10=isdbgpr
+# CHECK: { r10 = isdbgpr }
+           r10=s44
+# CHECK: { r10 = s44 }
+           r10=s45
+# CHECK: { r10 = s45 }
+           r10=s46
+# CHECK: { r10 = s46 }
+           r10=s47
+# CHECK: { r10 = s47 }
+           r10=pmucnt0
+# CHECK: { r10 = pmucnt0 }
+           r10=pmucnt1
+# CHECK: { r10 = pmucnt1 }
+           r10=pmucnt2
+# CHECK: { r10 = pmucnt2 }
+           r10=pmucnt3
+# CHECK: { r10 = pmucnt3 }
+           r10=pmuevtcfg
+# CHECK: { r10 = pmuevtcfg }
+           r10=s54
+# CHECK: { r10 = s54 }
+           r10=s60
+# CHECK: { r10 = s60 }
+           r10=s61
+# CHECK: { r10 = s61 }
+           r10=s62
+# CHECK: { r10 = s62 }
+           r10=s63
+# CHECK: { r10 = s63 }
+           r10=s70
+# CHECK: { r10 = s70 }
+           r10=s71
+# CHECK: { r10 = s71 }
+           r10=s72
+# CHECK: { r10 = s72 }
+           r10=s73
+# CHECK: { r10 = s73 }
+           r10=s74
+# CHECK: { r10 = s74 }
+           r10=s75
+# CHECK: { r10 = s75 }
+           r10=s76
+# CHECK: { r10 = s76 }
+           r10=s77
+# CHECK: { r10 = s77 }
+           r10=s78
+# CHECK: { r10 = s78 }
+           r10=s79
+# CHECK: { r10 = s79 }
+           r10=s80
+# CHECK: { r10 = s80 }

llvm/test/MC/Hexagon/sysregs3.s

+# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+#
+
+# Verify exceptions to the grouping rules for some registers.
+
+  { r6=ssr; r0=memw(r0) }
+# CHECK: { r6 = ssr
+  { r7:6=ccr:ssr; r1:0=memd(r0) }
+# CHECK: { r7:6 = s7:6
+  { ssr=r6; r0=memw(r0) }
+# CHECK: { ssr = r6
+  { s7:6=r7:6; r1:0=memd(r0) }
+# CHECK: { s7:6 = r7:6