[asan] Fixed a runtime crash.

[kstoimenov]

Summary

Looks like the NoRegister has some effect on the final code that is generated. My guess is that some optimization kicks in at the end?

When I use -S to dump the assembly I get the correct version with 'shrq $3, %r8':

movq    %r9, %r8
shrq    $3, %r8
movsbl  2147450880(%r8), %r8d

But, when I disassemble the final binary I get RAX in stead of R8:

mov    %r9,%r8
shr    $0x3,%rax
movsbl 0x7fff8000(%r8),%r8d

[vitalybuka]

Can you add a test?

[kstoimenov]

So the test will compile to an executable, so it will have to be a cpp file with a main. Then it will run 'objdump --disassemble=__asan_check_load4_rn53' and check that the machine code is properly generated. Where would be a good place to put this kind of test? The llvm/test/CodeGen/X86 location doesn't seem to be a good place as it has only .ll files in it.

[vitalybuka]

In D108745#2967460, @kstoimenov wrote:

So the test will compile to an executable, so it will have to be a cpp file with a main. Then it will run 'objdump --disassemble=__asan_check_load4_rn53' and check that the machine code is properly generated. Where would be a good place to put this kind of test? The llvm/test/CodeGen/X86 location doesn't seem to be a good place as it has only .ll files in it.

No. I am asking about extending tests of original patch.
Something must be different. Maybe one of obj files contains code with different reg then the rest and linker just picked not the one you are expected.
Maybe flags used to compile that object file was somehow special.

Would be nice to find-out why. I am not comfortable (as with the same place in the original patch as well) with having code which makes a difference, but invisible to tests.

[vitalybuka]

It would be nice if you find how you compiler that obj, but LGTM as is

llvm/lib/Target/X86/X86MCInstLower.cpp

getAddressSanitizerParams(
       Triple(M.getTargetTriple()), M.getDataLayout().getPointerSizeInBits(),
       AccessInfo.CompileKernel, &ShadowBase, &MappingScale, &OrShadowOffset);
 
   OutStreamer->emitInstruction(
       MCInstBuilder(X86::MOV64rr).addReg(X86::R8).addReg(X86::NoRegister + Reg),
       STI);
   OutStreamer->emitInstruction(MCInstBuilder(X86::SHR64ri)
                                    .addReg(X86::R8)
-                                   .addReg(X86::NoRegister)
+                                   .addReg(X86::R8)
                                    .addImm(MappingScale),
                                STI);
   if (OrShadowOffset) {
     OutStreamer->emitInstruction(MCInstBuilder(X86::OR64ri32)
-                                     .addReg(X86::NoRegister)
+                                     .addReg(X86::R8)
                                      .addReg(X86::R8)
                                      .addImm(ShadowBase),
                                  STI);
     OutStreamer->emitInstruction(MCInstBuilder(X86::MOV8rm)
                                      .addReg(X86::R8B)
                                      .addReg(X86::R8)
                                      .addImm(1)
                                      .addReg(X86::NoRegister)