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Differential D108566

[AArch64][GlobalISel] Add regbankselect support for G_LLROUND
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Authored by paquette on Aug 23 2021, 9:58 AM.

Details

Reviewers
aemerson
jroelofs
Commits
rGa2c8e1765808: [AArch64][GlobalISel] Add regbankselect support for G_LLROUND
Summary

Same as G_LROUND: destination should always be a GPR, source should always be a FPR.

Diff Detail

Event Timeline

paquette created this revision.Aug 23 2021, 9:58 AM
Herald added subscribers: hiraditya, kristof.beyls, rovka. · View Herald TranscriptAug 23 2021, 9:58 AM
paquette requested review of this revision.Aug 23 2021, 9:58 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 23 2021, 9:58 AM
jroelofs accepted this revision.Aug 23 2021, 10:18 AM
This revision is now accepted and ready to land.Aug 23 2021, 10:18 AM
This revision was landed with ongoing or failed builds.Aug 23 2021, 10:34 AM
Closed by commit rGa2c8e1765808: [AArch64][GlobalISel] Add regbankselect support for G_LLROUND (authored by paquette). · Explain Why
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rGa2c8e1765808: [AArch64][GlobalISel] Add regbankselect support for G_LLROUND.
Harbormaster completed remote builds in B120813: Diff 368135.Aug 23 2021, 11:03 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
GISel/
4 lines
test/
CodeGen/
AArch64/
GlobalISel/
65 lines

Diff 368140

llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

Show First 20 Lines • Show All 526 Lines • ▼ Show 20 Linesbool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
const MachineRegisterInfo &MRI, const MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI, const TargetRegisterInfo &TRI,
unsigned Depth) const { unsigned Depth) const {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case TargetOpcode::G_FPTOSI: case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI: case TargetOpcode::G_FPTOUI:
case TargetOpcode::G_FCMP: case TargetOpcode::G_FCMP:
case TargetOpcode::G_LROUND: case TargetOpcode::G_LROUND:
case TargetOpcode::G_LLROUND:
return true; return true;
default: default:
break; break;
} }
return hasFPConstraints(MI, MRI, TRI, Depth); return hasFPConstraints(MI, MRI, TRI, Depth);
} }
bool AArch64RegisterBankInfo::onlyDefinesFP(const MachineInstr &MI, bool AArch64RegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,
▲ Show 20 Lines • Show All 412 Lines • ▼ Show 20 Lines if (!isFPIntrinsic(ID))
break; break;
for (const auto &Op : MI.explicit_operands()) { for (const auto &Op : MI.explicit_operands()) {
if (Op.isReg()) if (Op.isReg())
OpRegBankIdx[Idx] = PMI_FirstFPR; OpRegBankIdx[Idx] = PMI_FirstFPR;
++Idx; ++Idx;
} }
break; break;
} }
case TargetOpcode::G_LROUND: { case TargetOpcode::G_LROUND:
case TargetOpcode::G_LLROUND: {
// Source is always floating point and destination is always integer. // Source is always floating point and destination is always integer.
OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR}; OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
break; break;
} }
} }
// Finally construct the computed mapping. // Finally construct the computed mapping.
SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands); SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
Show All 13 Lines

llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
...
---
name: no_cross_bank_copies_needed
legalized: true
regBankSelected: false
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: no_cross_bank_copies_needed
; CHECK: liveins: $d0
; CHECK: %fpr:fpr(s64) = COPY $d0
; CHECK: %llround:gpr(s64) = G_LLROUND %fpr(s64)
; CHECK: $d0 = COPY %llround(s64)
; CHECK: RET_ReallyLR implicit $s0
%fpr:_(s64) = COPY $d0
%llround:_(s64) = G_LLROUND %fpr
$d0 = COPY %llround:_(s64)
RET_ReallyLR implicit $s0
...
---
name: source_needs_copy
legalized: true
regBankSelected: false
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: source_needs_copy
; CHECK: liveins: $x0
; CHECK: %gpr:gpr(s64) = COPY $x0
; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
; CHECK: %llround:gpr(s64) = G_LLROUND [[COPY]](s64)
; CHECK: $d0 = COPY %llround(s64)
; CHECK: RET_ReallyLR implicit $s0
%gpr:_(s64) = COPY $x0
%llround:_(s64) = G_LLROUND %gpr
$d0 = COPY %llround:_(s64)
RET_ReallyLR implicit $s0
...
---
name: load_gets_fpr
legalized: true
regBankSelected: false
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: load_gets_fpr
; CHECK: liveins: $x0
; CHECK: %ptr:gpr(p0) = COPY $x0
; CHECK: %load:fpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
; CHECK: %llround:gpr(s64) = G_LLROUND %load(s32)
; CHECK: $d0 = COPY %llround(s64)
; CHECK: RET_ReallyLR implicit $s0
%ptr:_(p0) = COPY $x0
%load:_(s32) = G_LOAD %ptr(p0) :: (load (s32))
%llround:_(s64) = G_LLROUND %load
$d0 = COPY %llround:_(s64)
RET_ReallyLR implicit $s0
...