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Differential D108036

AMDGPU: Respect compute ABI attributes with unknown OS
ClosedPublic

Authored by arsenm on Aug 13 2021, 7:13 AM.

Details

Reviewers
rampitec
foad
mareko
Summary

Unfortunately Mesa is still using amdgcn-- as the triple for OpenGL,
so we still have the awkward unknown OS case to deal with. Previously
if the HSA ABI intrinsics appeared, we we would not add the ABI
registers to the function. We would emit an error later, but we still
need to produce some compile result. Start adding the registers to any
compute function, regardless of the OS. This keeps the internal state
more consistent, and will help avoid numerous test crashes in a future
patch which starts assuming the ABI inputs are present on functions by
default.

Diff Detail

Unit TestsFailed

TimeTest
730 msx64 debian > Clang.Index::annotate-comments.cpp
540 msx64 debian > Clang.Index::comment-c-decls.c
540 msx64 debian > Clang.Index::comment-cplus-decls.cpp
780 msx64 debian > Clang.Index::comment-to-html-xml-conversion.cpp
560 msx64 debian > Clang.Index::format-comment-cdecls.c
View Full Test Results (20 Failed)

Event Timeline

arsenm created this revision.Aug 13 2021, 7:13 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 6 others. · View Herald TranscriptAug 13 2021, 7:13 AM
arsenm requested review of this revision.Aug 13 2021, 7:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 13 2021, 7:13 AM
Herald added a subscriber: wdng. · View Herald Transcript
Harbormaster completed remote builds in B119443: Diff 366274.Aug 13 2021, 7:46 AM
rampitec accepted this revision.Aug 13 2021, 9:54 AM
This revision is now accepted and ready to land.Aug 13 2021, 9:54 AM
arsenm closed this revision.Aug 13 2021, 5:56 PM

5beb9a0e6aec4a4901229377d8cb9e6115956446

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
16 lines
test/
CodeGen/
AMDGPU/
18 lines

Diff 366274

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Lines if (!ST.flatScratchIsArchitected()) {
if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 && if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
(CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS)) (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
ArgInfo.PrivateSegmentWaveByteOffset = ArgInfo.PrivateSegmentWaveByteOffset =
ArgDescriptor::createRegister(AMDGPU::SGPR5); ArgDescriptor::createRegister(AMDGPU::SGPR5);
} }
} }
bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F); bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
if (isAmdHsaOrMesa) { if (isAmdHsaOrMesa && !ST.enableFlatScratch())
if (!ST.enableFlatScratch())
PrivateSegmentBuffer = true; PrivateSegmentBuffer = true;
else if (ST.isMesaGfxShader(F))
ImplicitBufferPtr = true;
if (UseFixedABI || F.hasFnAttribute("amdgpu-kernarg-segment-ptr"))
KernargSegmentPtr = true;
if (!AMDGPU::isGraphics(CC)) {
if (UseFixedABI) { if (UseFixedABI) {
DispatchPtr = true; DispatchPtr = true;
QueuePtr = true; QueuePtr = true;
// FIXME: We don't need this? // FIXME: We don't need this?
DispatchID = true; DispatchID = true;
} else { } else {
if (F.hasFnAttribute("amdgpu-dispatch-ptr")) if (F.hasFnAttribute("amdgpu-dispatch-ptr"))
DispatchPtr = true; DispatchPtr = true;
if (F.hasFnAttribute("amdgpu-queue-ptr")) if (F.hasFnAttribute("amdgpu-queue-ptr"))
QueuePtr = true; QueuePtr = true;
if (F.hasFnAttribute("amdgpu-dispatch-id")) if (F.hasFnAttribute("amdgpu-dispatch-id"))
DispatchID = true; DispatchID = true;
} }
} else if (ST.isMesaGfxShader(F)) {
ImplicitBufferPtr = true;
} }
if (UseFixedABI || F.hasFnAttribute("amdgpu-kernarg-segment-ptr"))
KernargSegmentPtr = true;
// TODO: This could be refined a lot. The attribute is a poor way of // TODO: This could be refined a lot. The attribute is a poor way of
// detecting calls or stack objects that may require it before argument // detecting calls or stack objects that may require it before argument
// lowering. // lowering.
if (ST.hasFlatAddressSpace() && isEntryFunction() && if (ST.hasFlatAddressSpace() && isEntryFunction() &&
(isAmdHsaOrMesa || ST.enableFlatScratch()) && (isAmdHsaOrMesa || ST.enableFlatScratch()) &&
(HasCalls || HasStackObjects || ST.enableFlatScratch()) && (HasCalls || HasStackObjects || ST.enableFlatScratch()) &&
!ST.flatScratchIsArchitected()) { !ST.flatScratchIsArchitected()) {
FlatScratchInit = true; FlatScratchInit = true;
▲ Show 20 Lines • Show All 464 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/trap-abis.ll

Show All 12 Lines
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-trap-handler --amdhsa-code-object-version=4 -verify-machineinstrs < %s | FileCheck --check-prefix=HSA-NOTRAP-GFX900-V4 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-trap-handler --amdhsa-code-object-version=4 -verify-machineinstrs < %s | FileCheck --check-prefix=HSA-NOTRAP-GFX900-V4 %s
declare void @llvm.trap() #0 declare void @llvm.trap() #0
declare void @llvm.debugtrap() #1 declare void @llvm.debugtrap() #1
define amdgpu_kernel void @trap(i32 addrspace(1)* nocapture readonly %arg0) { define amdgpu_kernel void @trap(i32 addrspace(1)* nocapture readonly %arg0) {
; NOHSA-TRAP-GFX900-V2-LABEL: trap: ; NOHSA-TRAP-GFX900-V2-LABEL: trap:
; NOHSA-TRAP-GFX900-V2: ; %bb.0: ; NOHSA-TRAP-GFX900-V2: ; %bb.0:
; NOHSA-TRAP-GFX900-V2-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; NOHSA-TRAP-GFX900-V2-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v0, 0 ; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v0, 0
; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v1, 1 ; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v1, 1
; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt lgkmcnt(0) ; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt lgkmcnt(0)
; NOHSA-TRAP-GFX900-V2-NEXT: global_store_dword v0, v1, s[0:1] ; NOHSA-TRAP-GFX900-V2-NEXT: global_store_dword v0, v1, s[0:1]
; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V2-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V2-NEXT: s_endpgm
; ;
; NOHSA-TRAP-GFX900-V3-LABEL: trap: ; NOHSA-TRAP-GFX900-V3-LABEL: trap:
; NOHSA-TRAP-GFX900-V3: ; %bb.0: ; NOHSA-TRAP-GFX900-V3: ; %bb.0:
; NOHSA-TRAP-GFX900-V3-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; NOHSA-TRAP-GFX900-V3-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v0, 0 ; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v0, 0
; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v1, 1 ; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v1, 1
; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt lgkmcnt(0) ; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt lgkmcnt(0)
; NOHSA-TRAP-GFX900-V3-NEXT: global_store_dword v0, v1, s[0:1] ; NOHSA-TRAP-GFX900-V3-NEXT: global_store_dword v0, v1, s[0:1]
; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V3-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V3-NEXT: s_endpgm
; ;
; NOHSA-TRAP-GFX900-V4-LABEL: trap: ; NOHSA-TRAP-GFX900-V4-LABEL: trap:
; NOHSA-TRAP-GFX900-V4: ; %bb.0: ; NOHSA-TRAP-GFX900-V4: ; %bb.0:
; NOHSA-TRAP-GFX900-V4-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; NOHSA-TRAP-GFX900-V4-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v0, 0 ; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v0, 0
; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v1, 1 ; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v1, 1
; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt lgkmcnt(0) ; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt lgkmcnt(0)
; NOHSA-TRAP-GFX900-V4-NEXT: global_store_dword v0, v1, s[0:1] ; NOHSA-TRAP-GFX900-V4-NEXT: global_store_dword v0, v1, s[0:1]
; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V4-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V4-NEXT: s_endpgm
; ;
; HSA-TRAP-GFX803-V2-LABEL: trap: ; HSA-TRAP-GFX803-V2-LABEL: trap:
▲ Show 20 Lines • Show All 302 Lines • ▼ Show 20 Lines; HSA-NOTRAP-GFX900-V4-NEXT: s_endpgm
unreachable unreachable
store volatile i32 2, i32 addrspace(1)* %arg0 store volatile i32 2, i32 addrspace(1)* %arg0
ret void ret void
} }
define amdgpu_kernel void @non_entry_trap(i32 addrspace(1)* nocapture readonly %arg0) local_unnamed_addr { define amdgpu_kernel void @non_entry_trap(i32 addrspace(1)* nocapture readonly %arg0) local_unnamed_addr {
; NOHSA-TRAP-GFX900-V2-LABEL: non_entry_trap: ; NOHSA-TRAP-GFX900-V2-LABEL: non_entry_trap:
; NOHSA-TRAP-GFX900-V2: ; %bb.0: ; %entry ; NOHSA-TRAP-GFX900-V2: ; %bb.0: ; %entry
; NOHSA-TRAP-GFX900-V2-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; NOHSA-TRAP-GFX900-V2-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v0, 0 ; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v0, 0
; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt lgkmcnt(0) ; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt lgkmcnt(0)
; NOHSA-TRAP-GFX900-V2-NEXT: global_load_dword v1, v0, s[0:1] glc ; NOHSA-TRAP-GFX900-V2-NEXT: global_load_dword v1, v0, s[0:1] glc
; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V2-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1 ; NOHSA-TRAP-GFX900-V2-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1
; NOHSA-TRAP-GFX900-V2-NEXT: s_and_b64 vcc, exec, vcc ; NOHSA-TRAP-GFX900-V2-NEXT: s_and_b64 vcc, exec, vcc
; NOHSA-TRAP-GFX900-V2-NEXT: s_cbranch_vccz BB1_2 ; NOHSA-TRAP-GFX900-V2-NEXT: s_cbranch_vccz BB1_2
; NOHSA-TRAP-GFX900-V2-NEXT: ; %bb.1: ; %ret ; NOHSA-TRAP-GFX900-V2-NEXT: ; %bb.1: ; %ret
; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v1, 3 ; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v1, 3
; NOHSA-TRAP-GFX900-V2-NEXT: global_store_dword v0, v1, s[0:1] ; NOHSA-TRAP-GFX900-V2-NEXT: global_store_dword v0, v1, s[0:1]
; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V2-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V2-NEXT: s_endpgm
; NOHSA-TRAP-GFX900-V2-NEXT: BB1_2: ; %trap ; NOHSA-TRAP-GFX900-V2-NEXT: BB1_2: ; %trap
; NOHSA-TRAP-GFX900-V2-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V2-NEXT: s_endpgm
; ;
; NOHSA-TRAP-GFX900-V3-LABEL: non_entry_trap: ; NOHSA-TRAP-GFX900-V3-LABEL: non_entry_trap:
; NOHSA-TRAP-GFX900-V3: ; %bb.0: ; %entry ; NOHSA-TRAP-GFX900-V3: ; %bb.0: ; %entry
; NOHSA-TRAP-GFX900-V3-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; NOHSA-TRAP-GFX900-V3-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v0, 0 ; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v0, 0
; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt lgkmcnt(0) ; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt lgkmcnt(0)
; NOHSA-TRAP-GFX900-V3-NEXT: global_load_dword v1, v0, s[0:1] glc ; NOHSA-TRAP-GFX900-V3-NEXT: global_load_dword v1, v0, s[0:1] glc
; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V3-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1 ; NOHSA-TRAP-GFX900-V3-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1
; NOHSA-TRAP-GFX900-V3-NEXT: s_and_b64 vcc, exec, vcc ; NOHSA-TRAP-GFX900-V3-NEXT: s_and_b64 vcc, exec, vcc
; NOHSA-TRAP-GFX900-V3-NEXT: s_cbranch_vccz BB1_2 ; NOHSA-TRAP-GFX900-V3-NEXT: s_cbranch_vccz BB1_2
; NOHSA-TRAP-GFX900-V3-NEXT: ; %bb.1: ; %ret ; NOHSA-TRAP-GFX900-V3-NEXT: ; %bb.1: ; %ret
; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v1, 3 ; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v1, 3
; NOHSA-TRAP-GFX900-V3-NEXT: global_store_dword v0, v1, s[0:1] ; NOHSA-TRAP-GFX900-V3-NEXT: global_store_dword v0, v1, s[0:1]
; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V3-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V3-NEXT: s_endpgm
; NOHSA-TRAP-GFX900-V3-NEXT: BB1_2: ; %trap ; NOHSA-TRAP-GFX900-V3-NEXT: BB1_2: ; %trap
; NOHSA-TRAP-GFX900-V3-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V3-NEXT: s_endpgm
; ;
; NOHSA-TRAP-GFX900-V4-LABEL: non_entry_trap: ; NOHSA-TRAP-GFX900-V4-LABEL: non_entry_trap:
; NOHSA-TRAP-GFX900-V4: ; %bb.0: ; %entry ; NOHSA-TRAP-GFX900-V4: ; %bb.0: ; %entry
; NOHSA-TRAP-GFX900-V4-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; NOHSA-TRAP-GFX900-V4-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v0, 0 ; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v0, 0
; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt lgkmcnt(0) ; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt lgkmcnt(0)
; NOHSA-TRAP-GFX900-V4-NEXT: global_load_dword v1, v0, s[0:1] glc ; NOHSA-TRAP-GFX900-V4-NEXT: global_load_dword v1, v0, s[0:1] glc
; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V4-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1 ; NOHSA-TRAP-GFX900-V4-NEXT: v_cmp_eq_u32_e32 vcc, -1, v1
; NOHSA-TRAP-GFX900-V4-NEXT: s_and_b64 vcc, exec, vcc ; NOHSA-TRAP-GFX900-V4-NEXT: s_and_b64 vcc, exec, vcc
; NOHSA-TRAP-GFX900-V4-NEXT: s_cbranch_vccz BB1_2 ; NOHSA-TRAP-GFX900-V4-NEXT: s_cbranch_vccz BB1_2
; NOHSA-TRAP-GFX900-V4-NEXT: ; %bb.1: ; %ret ; NOHSA-TRAP-GFX900-V4-NEXT: ; %bb.1: ; %ret
▲ Show 20 Lines • Show All 395 Lines • ▼ Show 20 Lines
ret: ret:
store volatile i32 3, i32 addrspace(1)* %arg0 store volatile i32 3, i32 addrspace(1)* %arg0
ret void ret void
} }
define amdgpu_kernel void @debugtrap(i32 addrspace(1)* nocapture readonly %arg0) { define amdgpu_kernel void @debugtrap(i32 addrspace(1)* nocapture readonly %arg0) {
; NOHSA-TRAP-GFX900-V2-LABEL: debugtrap: ; NOHSA-TRAP-GFX900-V2-LABEL: debugtrap:
; NOHSA-TRAP-GFX900-V2: ; %bb.0: ; NOHSA-TRAP-GFX900-V2: ; %bb.0:
; NOHSA-TRAP-GFX900-V2-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; NOHSA-TRAP-GFX900-V2-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v0, 0 ; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v0, 0
; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v1, 1 ; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v1, 1
; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v2, 2 ; NOHSA-TRAP-GFX900-V2-NEXT: v_mov_b32_e32 v2, 2
; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt lgkmcnt(0) ; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt lgkmcnt(0)
; NOHSA-TRAP-GFX900-V2-NEXT: global_store_dword v0, v1, s[0:1] ; NOHSA-TRAP-GFX900-V2-NEXT: global_store_dword v0, v1, s[0:1]
; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V2-NEXT: global_store_dword v0, v2, s[0:1] ; NOHSA-TRAP-GFX900-V2-NEXT: global_store_dword v0, v2, s[0:1]
; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V2-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V2-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V2-NEXT: s_endpgm
; ;
; NOHSA-TRAP-GFX900-V3-LABEL: debugtrap: ; NOHSA-TRAP-GFX900-V3-LABEL: debugtrap:
; NOHSA-TRAP-GFX900-V3: ; %bb.0: ; NOHSA-TRAP-GFX900-V3: ; %bb.0:
; NOHSA-TRAP-GFX900-V3-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; NOHSA-TRAP-GFX900-V3-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v0, 0 ; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v0, 0
; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v1, 1 ; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v1, 1
; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v2, 2 ; NOHSA-TRAP-GFX900-V3-NEXT: v_mov_b32_e32 v2, 2
; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt lgkmcnt(0) ; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt lgkmcnt(0)
; NOHSA-TRAP-GFX900-V3-NEXT: global_store_dword v0, v1, s[0:1] ; NOHSA-TRAP-GFX900-V3-NEXT: global_store_dword v0, v1, s[0:1]
; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V3-NEXT: global_store_dword v0, v2, s[0:1] ; NOHSA-TRAP-GFX900-V3-NEXT: global_store_dword v0, v2, s[0:1]
; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V3-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V3-NEXT: s_endpgm ; NOHSA-TRAP-GFX900-V3-NEXT: s_endpgm
; ;
; NOHSA-TRAP-GFX900-V4-LABEL: debugtrap: ; NOHSA-TRAP-GFX900-V4-LABEL: debugtrap:
; NOHSA-TRAP-GFX900-V4: ; %bb.0: ; NOHSA-TRAP-GFX900-V4: ; %bb.0:
; NOHSA-TRAP-GFX900-V4-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; NOHSA-TRAP-GFX900-V4-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v0, 0 ; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v0, 0
; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v1, 1 ; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v1, 1
; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v2, 2 ; NOHSA-TRAP-GFX900-V4-NEXT: v_mov_b32_e32 v2, 2
; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt lgkmcnt(0) ; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt lgkmcnt(0)
; NOHSA-TRAP-GFX900-V4-NEXT: global_store_dword v0, v1, s[0:1] ; NOHSA-TRAP-GFX900-V4-NEXT: global_store_dword v0, v1, s[0:1]
; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0)
; NOHSA-TRAP-GFX900-V4-NEXT: global_store_dword v0, v2, s[0:1] ; NOHSA-TRAP-GFX900-V4-NEXT: global_store_dword v0, v2, s[0:1]
; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0) ; NOHSA-TRAP-GFX900-V4-NEXT: s_waitcnt vmcnt(0)
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