This is an archive of the discontinued LLVM Phabricator instance.

Note: I don't mean this patch for submission (yet), it's rather meant as a question: (line 977) why should the def be a physical register mean the instruction isn't trivially rematerializable?

(ran tests, everything passes)

Thanks!

Harbormaster completed remote builds in B118930: Diff 365530.Aug 10 2021, 11:09 AM

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llvm/

lib/

CodeGen/

TargetInstrInfo.cpp

2 lines

Diff 365530

llvm/lib/CodeGen/TargetInstrInfo.cpp

Show First 20 Lines • Show All 951 Lines • ▼ Show 20 Lines	if (MI.isInlineAsm())
return false;		return false;

// Avoid instructions which load from potentially varying memory.		// Avoid instructions which load from potentially varying memory.
if (MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA))		if (MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA))
return false;		return false;

// If any of the registers accessed are non-constant, conservatively assume		// If any of the registers accessed are non-constant, conservatively assume
// the instruction is not rematerializable.		// the instruction is not rematerializable.
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {		for (unsigned i = 1, e = MI.getNumOperands(); i != e; ++i) {
		Lint: Pre-merge checks Inline Actions clang-tidy: warning: invalid case style for variable 'i' [readability-identifier-naming] not useful clang-tidy: warning: invalid case style for variable 'e' [readability-identifier-naming] not useful Lint: Pre-merge checks: clang-tidy: warning: invalid case style for variable 'i' [readability-identifier-naming]…
const MachineOperand &MO = MI.getOperand(i);		const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg()) continue;		if (!MO.isReg()) continue;
Register Reg = MO.getReg();		Register Reg = MO.getReg();
if (Reg == 0)		if (Reg == 0)
continue;		continue;

// Check for a well-behaved physical register.		// Check for a well-behaved physical register.
if (Register::isPhysicalRegister(Reg)) {		if (Register::isPhysicalRegister(Reg)) {
▲ Show 20 Lines • Show All 435 Lines • Show Last 20 Lines

This is an archive of the discontinued LLVM Phabricator instance.

[WIP] Ignore def operand when determining whether an instruction is remat.Needs ReviewPublic

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Diff 365530

llvm/lib/CodeGen/TargetInstrInfo.cpp

[WIP] Ignore def operand when determining whether an instruction is remat.
Needs ReviewPublic