[AArch64][GlobalISel] Make G_PTRTOINT only legal for s64 + p0

[paquette]

Summary

A few issues:

1. There was no legalizer test for G_PTRTOINT
2. Same clamping issue as in many other opcodes
3. AArch64 pointers can only be 64b, so in reality we always have to trunc or extend with any size other than p0 anyway.

This seems to actually produce more correct selection for narrow types as well.

[aemerson]

I think the clamping behavior should only allow s64 result types, since AArch64 pointers can only be 64b.

[paquette]

Always clamp to s64

[aemerson]

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptrtoint.mir

27

I expected these to change?

[paquette]

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptrtoint.mir

27

The existing legality behaviour says it's okay:

.legalForCartesianProduct({s1, s8, s16, s32, s64}, {p0})

Should we just drop everything except for s64 entirely?

[aemerson]

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptrtoint.mir

27

Yes I think so.

[paquette]

Only allow s64.

I think that, running through to selection, this actually fixes a couple bugs too. (ptrtoint_s16_p0 and ptrtoint_s8_p0 were using sub_32???)

[aemerson]

LGTM.

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
   getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
 
   if (TM.getCodeModel() == CodeModel::Small)
     getActionDefinitionsBuilder(G_GLOBAL_VALUE).custom();
   else
     getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0});
 
   getActionDefinitionsBuilder(G_PTRTOINT)
-      .legalForCartesianProduct({s8, s16, s32, s64}, {p0})
-      .legalFor({{v2s64, v2p0}})
-      .maxScalar(0, s64)
-      .widenScalarToNextPow2(0, /*Min*/ 8);
+      .legalFor({{s64, p0}, {v2s64, v2p0}})
+      .widenScalarToNextPow2(0, 64)
+      .clampScalar(0, s64, s64);
 
   getActionDefinitionsBuilder(G_INTTOPTR)
       .unsupportedIf([&](const LegalityQuery &Query) {
         return Query.Types[0].getSizeInBits() != Query.Types[1].getSizeInBits();
       })
       .legalFor({{p0, s64}, {v2p0, v2s64}});
 
   // Casts for 32 and 64-bit width type are just copies.

llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -O0 -mtriple=aarch64-apple-ios -verify-machineinstrs -global-isel -stop-after=legalizer %s -o - | FileCheck %s
 
 @_ZTIi = external global i8*
 
 declare i32 @foo(i32)
 declare i32 @__gxx_personality_v0(...)
 declare i32 @llvm.eh.typeid.for(i8*)
 declare void @_Unwind_Resume(i8*)
 
-; CHECK: name: bar
-; CHECK: body:
-; CHECK-NEXT:   bb.1 (%ir-block.0):
-; CHECK:     successors: %{{bb.[0-9]+.*}}%[[LP:bb.[0-9]+]]
-
-; CHECK:   [[LP]].{{[a-z]+}} (landing-pad):
-; CHECK:     EH_LABEL
-
-; CHECK:     [[PTR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK:     [[SEL_PTR:%[0-9]+]]:_(p0) = COPY $x1
-; CHECK:     [[SEL_PTR_INT:%[0-9]+]]:_(s32) = G_PTRTOINT [[SEL_PTR]](p0)
-; CHECK:     G_STORE [[PTR]](p0), %0(p0) :: (store (p0) into %ir.exn.slot)
-; CHECK:     G_STORE [[SEL_PTR_INT]](s32), %1(p0) :: (store (s32) into %ir.ehselector.slot)
-
 define void @bar() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+  ; CHECK-LABEL: name: bar
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+  ; CHECK-NEXT:   [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.exn.slot
+  ; CHECK-NEXT:   [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.ehselector.slot
+  ; CHECK-NEXT:   EH_LABEL <mcsymbol >
+  ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   $w0 = COPY [[C]](s32)
+  ; CHECK-NEXT:   BL @foo, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
+  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   EH_LABEL <mcsymbol >
+  ; CHECK-NEXT:   G_BR %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.cleanup (landing-pad):
+  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
+  ; CHECK-NEXT:   liveins: $x0, $x1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   EH_LABEL <mcsymbol >
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+  ; CHECK-NEXT:   [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+  ; CHECK-NEXT:   G_STORE [[COPY]](p0), [[FRAME_INDEX]](p0) :: (store (p0) into %ir.exn.slot)
+  ; CHECK-NEXT:   G_STORE [[TRUNC]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.ehselector.slot)
+  ; CHECK-NEXT:   G_BR %bb.4
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.continue:
+  ; CHECK-NEXT:   RET_ReallyLR
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4.eh.resume:
+  ; CHECK-NEXT:   [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (p0) from %ir.exn.slot)
+  ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   $x0 = COPY [[LOAD]](p0)
+  ; CHECK-NEXT:   BL @_Unwind_Resume, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
+  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
   %exn.slot = alloca i8*
   %ehselector.slot = alloca i32
   %1 = invoke i32 @foo(i32 42) to label %continue unwind label %cleanup
 
 cleanup:
   %2 = landingpad { i8*, i32 } cleanup
   %3 = extractvalue { i8*, i32 } %2, 0
   store i8* %3, i8** %exn.slot, align 8

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptrtoint.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
 
 ...
 ---
+name: p0_s64
+body: |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: p0_s64
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+    ; CHECK-NEXT: %int:_(s64) = G_PTRTOINT %ptr(p0)
+    ; CHECK-NEXT: $x0 = COPY %int(s64)
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
+    %ptr:_(p0) = COPY $x0
+    %int:_(s64) = G_PTRTOINT %ptr
+    $x0 = COPY %int
+    RET_ReallyLR implicit $x0
+...
+---
+name: p0_s32
+body: |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: p0_s32
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT %ptr(p0)
+    ; CHECK-NEXT: %int:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+    ; CHECK-NEXT: $w0 = COPY %int(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %ptr:_(p0) = COPY $x0
+    %int:_(s32) = G_PTRTOINT %ptr
+    $w0 = COPY %int
+    RET_ReallyLR implicit $w0
+...
+---
+name: p0_s16
+body: |
+  bb.0:
+    liveins: $x0, $h0
+    ; CHECK-LABEL: name: p0_s16
+    ; CHECK: liveins: $x0, $h0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT %ptr(p0)
+    ; CHECK-NEXT: %int:_(s16) = G_TRUNC [[PTRTOINT]](s64)
+    ; CHECK-NEXT: $h0 = COPY %int(s16)
+    ; CHECK-NEXT: RET_ReallyLR implicit $h0
+    %ptr:_(p0) = COPY $x0
+    %int:_(s16) = G_PTRTOINT %ptr
+    $h0 = COPY %int
+    RET_ReallyLR implicit $h0
+...
+---
+name: p0_s8
+body: |
+  bb.0:
+    liveins: $x0, $b0
+    ; CHECK-LABEL: name: p0_s8
+    ; CHECK: liveins: $x0, $b0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT %ptr(p0)
+    ; CHECK-NEXT: %int:_(s8) = G_TRUNC [[PTRTOINT]](s64)
+    ; CHECK-NEXT: $b0 = COPY %int(s8)
+    ; CHECK-NEXT: RET_ReallyLR implicit $b0
+    %ptr:_(p0) = COPY $x0
+    %int:_(s8) = G_PTRTOINT %ptr
+    $b0 = COPY %int
+    RET_ReallyLR implicit $b0
+...
+---
+name: p0_s1
+body: |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: p0_s1
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT %ptr(p0)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+    ; CHECK-NEXT: %ext:_(s32) = G_AND [[TRUNC]], [[C]]
+    ; CHECK-NEXT: $w0 = COPY %ext(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %ptr:_(p0) = COPY $x0
+    %int:_(s1) = G_PTRTOINT %ptr
+    %ext:_(s32) = G_ZEXT %int
+    $w0 = COPY %ext
+    RET_ReallyLR implicit $w0
+...
+---
+name: p0_s128
+body: |
+  bb.0:
+    liveins: $x0, $q0
+    ; CHECK-LABEL: name: p0_s128
+    ; CHECK: liveins: $x0, $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT %ptr(p0)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: %int:_(s128) = G_MERGE_VALUES [[PTRTOINT]](s64), [[C]](s64)
+    ; CHECK-NEXT: $q0 = COPY %int(s128)
+    ; CHECK-NEXT: RET_ReallyLR implicit $q0
+    %ptr:_(p0) = COPY $x0
+    %int:_(s128) = G_PTRTOINT %ptr
+    $q0 = COPY %int
+    RET_ReallyLR implicit $q0
+...
+---
+name: p0_s88
+body: |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: p0_s88
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT %ptr(p0)
+    ; CHECK-NEXT: %trunc:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+    ; CHECK-NEXT: $w0 = COPY %trunc(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %ptr:_(p0) = COPY $x0
+    %int:_(s88) = G_PTRTOINT %ptr
+    %trunc:_(s32) = G_TRUNC %int
+    $w0 = COPY %trunc
+    RET_ReallyLR implicit $w0
+
+...
+---
 name:            v2s64_v2p0_legal
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $q0
 
     ; CHECK-LABEL: name: v2s64_v2p0_legal
     ; CHECK: liveins: $q0
-    ; CHECK: %ptr:_(<2 x p0>) = COPY $q0
-    ; CHECK: %int:_(<2 x s64>) = G_PTRTOINT %ptr(<2 x p0>)
-    ; CHECK: $q0 = COPY %int(<2 x s64>)
-    ; CHECK: RET_ReallyLR implicit $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %ptr:_(<2 x p0>) = COPY $q0
+    ; CHECK-NEXT: %int:_(<2 x s64>) = G_PTRTOINT %ptr(<2 x p0>)
+    ; CHECK-NEXT: $q0 = COPY %int(<2 x s64>)
+    ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %ptr:_(<2 x p0>) = COPY $q0
     %int:_(<2 x s64>) = G_PTRTOINT %ptr(<2 x p0>)
     $q0 = COPY %int(<2 x s64>)
     RET_ReallyLR implicit $q0
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
   define void @inttoptr_p0_s64() { ret void }
   define void @ptrtoint_s64_p0() { ret void }
   define void @ptrtoint_s32_p0() { ret void }
   define void @ptrtoint_s16_p0() { ret void }
   define void @ptrtoint_s8_p0() { ret void }
+  define void @ptrtoint_s1_p0() { ret void }
   define void @inttoptr_v2p0_v2s64() { ret void }
   define void @ptrtoint_v2s64_v2p0() { ret void }
 ...
 
 ---
 name:            inttoptr_p0_s64
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 body:             |
   bb.0:
     liveins: $x0
     ; CHECK-LABEL: name: inttoptr_p0_s64
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
     ; CHECK-NEXT: $x0 = COPY [[COPY]]
     %0(s64) = COPY $x0
     %1(p0) = G_INTTOPTR %0
     $x0 = COPY %1(p0)
 ...
 
 ---
 name:            ptrtoint_s64_p0
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 body:             |
   bb.0:
     liveins: $x0
     ; CHECK-LABEL: name: ptrtoint_s64_p0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
     ; CHECK-NEXT: $x0 = COPY [[COPY]]
     %0(p0) = COPY $x0
     %1(s64) = G_PTRTOINT %0
     $x0 = COPY %1(s64)
 ...
 
 ---
 name:            ptrtoint_s32_p0
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 body:             |
   bb.0:
     liveins: $x0
     ; CHECK-LABEL: name: ptrtoint_s32_p0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
-    ; CHECK-NEXT: $w0 = COPY [[COPY1]]
-    %0(p0) = COPY $x0
-    %1(s32) = G_PTRTOINT %0
-    $w0 = COPY %1(s32)
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %ptr:gpr64 = COPY $x0
+    ; CHECK-NEXT: %ptr2int:gpr64common = COPY %ptr
+    ; CHECK-NEXT: %int:gpr32sp = COPY %ptr2int.sub_32
+    ; CHECK-NEXT: $w0 = COPY %int
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %ptr:gpr(p0) = COPY $x0
+    %ptr2int:gpr(s64) = G_PTRTOINT %ptr(p0)
+    %int:gpr(s32) = G_TRUNC %ptr2int(s64)
+    $w0 = COPY %int(s32)
+    RET_ReallyLR implicit $w0
 ...
 
 ---
 name:            ptrtoint_s16_p0
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 body:             |
   bb.0:
     liveins: $x0
     ; CHECK-LABEL: name: ptrtoint_s16_p0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
-    ; CHECK-NEXT: $w0 = COPY [[COPY2]]
-    %0(p0) = COPY $x0
-    %1(s16) = G_PTRTOINT %0
-    %2:gpr(s32) = G_ANYEXT %1
-    $w0 = COPY %2(s32)
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %ptr:gpr64 = COPY $x0
+    ; CHECK-NEXT: %int:gpr32 = COPY %ptr.sub_32
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY %int
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
+    ; CHECK-NEXT: $h0 = COPY [[COPY1]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $h0
+    %ptr:gpr(p0) = COPY $x0
+    %ptr2int:gpr(s64) = G_PTRTOINT %ptr(p0)
+    %int:gpr(s16) = G_TRUNC %ptr2int(s64)
+    $h0 = COPY %int(s16)
+    RET_ReallyLR implicit $h0
 ...
 
 ---
 name:            ptrtoint_s8_p0
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 body:             |
   bb.0:
     liveins: $x0
     ; CHECK-LABEL: name: ptrtoint_s8_p0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
-    ; CHECK-NEXT: $w0 = COPY [[COPY2]]
-    %0(p0) = COPY $x0
-    %1(s8) = G_PTRTOINT %0
-    %2:gpr(s32) = G_ANYEXT %1
-    $w0 = COPY %2(s32)
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %ptr:gpr64 = COPY $x0
+    ; CHECK-NEXT: %int:gpr32 = COPY %ptr.sub_32
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY %int
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr8 = COPY [[COPY]].bsub
+    ; CHECK-NEXT: $b0 = COPY [[COPY1]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $b0
+    %ptr:gpr(p0) = COPY $x0
+    %ptr2int:gpr(s64) = G_PTRTOINT %ptr(p0)
+    %int:gpr(s8) = G_TRUNC %ptr2int(s64)
+    $b0 = COPY %int(s8)
+    RET_ReallyLR implicit $b0
+
 ...
+---
+name:            ptrtoint_s1_p0
+legalized:       true
+regBankSelected: true
 
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+body:             |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: ptrtoint_s1_p0
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %ptr:gpr64 = COPY $x0
+    ; CHECK-NEXT: %ptr2int:gpr64common = COPY %ptr
+    ; CHECK-NEXT: %trunc:gpr32common = COPY %ptr2int.sub_32
+    ; CHECK-NEXT: %ext:gpr32sp = ANDWri %trunc, 0
+    ; CHECK-NEXT: $w0 = COPY %ext
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %ptr:gpr(p0) = COPY $x0
+    %ptr2int:gpr(s64) = G_PTRTOINT %ptr(p0)
+    %one:gpr(s32) = G_CONSTANT i32 1
+    %trunc:gpr(s32) = G_TRUNC %ptr2int(s64)
+    %ext:gpr(s32) = G_AND %trunc, %one
+    $w0 = COPY %ext(s32)
+    RET_ReallyLR implicit $w0
+...
 ---
 name:            inttoptr_v2p0_v2s64
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $q0, $x0