AArch64: support @llvm.va_copy in GISel

[t.p.northover]

Summary

It's essentially just a memcpy of some platform-depenent constant number of bytes. This puts the code in the Legalizer so that the (potentially fairly large) memory operations can be split up properly.

[paquette]

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

959

slightly more succinct

966

SDAG sets Align to be the pointer size here. Should we do that too?

[t.p.northover]

Adopted suggested changes. The align one didn't actually change the MIR output unfortunately so I don't tihnk it's really testable.

[paquette]

LGTM

[t.p.northover]

Thanks, committed as 5ad086089962.

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

966

Oh yes, well spotted!

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

bool AArch64LegalizerInfo::legalizeSmallCMGlobalValue(
 
   MIRBuilder.buildInstr(AArch64::G_ADD_LOW, {DstReg}, {ADRP})
       .addGlobalAddress(GV, Offset,
                         OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
   MI.eraseFromParent();
   return true;
 }
 
+static unsigned findIntrinsicID(MachineInstr &I) {
+  auto IntrinOp = find_if(I.operands(), [&](const MachineOperand &Op) {
+    return Op.isIntrinsicID();
+  });
+  if (IntrinOp == I.operands_end())
+    return 0;
+  return IntrinOp->getIntrinsicID();
+}
+
 bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
                                              MachineInstr &MI) const {
+  switch (findIntrinsicID(MI)) {
+  case Intrinsic::vacopy: {
+    unsigned PtrSize = ST->isTargetILP32() ? 4 : 8;
+    unsigned VaListSize =
+      (ST->isTargetDarwin() || ST->isTargetWindows())
+          ? PtrSize
+          : ST->isTargetILP32() ? 20 : 32;
+
+    MachineFunction &MF = *MI.getMF();
+    auto Val = MF.getRegInfo().createGenericVirtualRegister(
+        LLT::scalar(VaListSize * 8));
+    MachineIRBuilder MIB(MI);
+    MIB.buildLoad(Val, MI.getOperand(2),
+                  *MF.getMachineMemOperand(MachinePointerInfo(),
+                                           MachineMemOperand::MOLoad,
+                                           VaListSize, Align(PtrSize)));
+    MIB.buildStore(Val, MI.getOperand(1),
+                   *MF.getMachineMemOperand(MachinePointerInfo(),
+                                            MachineMemOperand::MOStore,
+                                            VaListSize, Align(PtrSize)));
+    MI.eraseFromParent();
+    return true;
+  }
+  }
+
   return true;
 }
 
 bool AArch64LegalizerInfo::legalizeShlAshrLshr(
     MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder,
     GISelChangeObserver &Observer) const {
   assert(MI.getOpcode() == TargetOpcode::G_ASHR ||
          MI.getOpcode() == TargetOpcode::G_LSHR ||

llvm/test/CodeGen/AArch64/GlobalISel/legalize-vacopy.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=arm64-apple-ios -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-DARWIN
+# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-LINUX
+
+---
+name:            test_vaarg
+body: |
+  bb.0:
+        liveins: $x0, $x1
+
+    ; CHECK-DARWIN-LABEL: name: test_vaarg
+    ; CHECK-DARWIN: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+    ; CHECK-DARWIN: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+    ; CHECK-DARWIN: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY1]](p0) :: (load (s64))
+    ; CHECK-DARWIN: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store (s64))
+    ; CHECK-DARWIN: RET_ReallyLR
+    ; CHECK-LINUX-LABEL: name: test_vaarg
+    ; CHECK-LINUX: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+    ; CHECK-LINUX: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+    ; CHECK-LINUX: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY1]](p0) :: (load (s64))
+    ; CHECK-LINUX: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK-LINUX: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C]](s64)
+    ; CHECK-LINUX: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from unknown-address + 8)
+    ; CHECK-LINUX: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+    ; CHECK-LINUX: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64)
+    ; CHECK-LINUX: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p0) :: (load (s64) from unknown-address + 16)
+    ; CHECK-LINUX: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
+    ; CHECK-LINUX: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C2]](s64)
+    ; CHECK-LINUX: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p0) :: (load (s64) from unknown-address + 24)
+    ; CHECK-LINUX: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store (s64))
+    ; CHECK-LINUX: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+    ; CHECK-LINUX: G_STORE [[LOAD1]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 8)
+    ; CHECK-LINUX: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
+    ; CHECK-LINUX: G_STORE [[LOAD2]](s64), [[PTR_ADD4]](p0) :: (store (s64) into unknown-address + 16)
+    ; CHECK-LINUX: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
+    ; CHECK-LINUX: G_STORE [[LOAD3]](s64), [[PTR_ADD5]](p0) :: (store (s64) into unknown-address + 24)
+    ; CHECK-LINUX: RET_ReallyLR
+        %0:_(p0) = COPY $x0
+        %1:_(p0) = COPY $x1
+        G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), %0(p0), %1
+        RET_ReallyLR
+...