[Lanai] implement wide immediate support

[q3k]

Summary

This fixes LanaiTTIImpl::getIntImmCost to return valid costs for i128
(and wider) values. Previously any immediate wider than
64 bits would cause Lanai llc to crash.

A regression test is also added that exercises this functionality.

[q3k]

Attempting to stack changes.

[jpienaar]

llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h

63

Wouldn't this say that returning > 64 is cheaper than returning 32 bits?

[q3k]

llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h

63

As far as I understand, this affects only constant hoisting, and returning TCC_Free means “don't hoist this constant”, which is the default behavior unless implemented otherwise anyway. IIUC, this means worst case we're leaving possible optimizations for i128+ on the table but aren't making things worse for narrower types. There is also precedent to returning _Free when deilng with wide immediates in SystemZTTIImpl::getIntImmCost, which is in fact where I've lifted this from. :) Same for X86TTIImpl::getIntImmCost.

However, I can instead attempt to properly implement the cost here. As far as I understand, we want to return the cost of materializing loading the constant as an immediate, a.k.a. the number of instructions it takes to load a given constant into registers. For anything wider than 32 bit we could implement the line 71-74 calculation in a loop for each 32-bit chunk of the immediate. This is what RISC-V and AArch64 do.

Alternatively we could simplify it to (BitSize >> 3) * TTC_Basic (8 for i128, 16 for i256...), reflecting the worst case mov+or materialization for each 32 bits, ignoring the no-low-bits set optimization from lines 72-73. This is in line with 4 * TTC_Basic currently returned for i64.

WDYT?

[jpienaar]

llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h

63

That makes sense, OK, lets keep it as is. And can refine if needed.

[q3k]

Thanks! I'll also need someone to submit/commit/land this for me. Is this something you can do, @jpienaar? Or should I be asking someone else?

[q3k]

Friendly ping, need someone to actually submit this now... :) @jpienaar? @MaskRay?

llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h

TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth) {
     if (TyWidth == 32)
       return TTI::PSK_FastHardware;
     return TTI::PSK_Software;
   }
 
   InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
                                 TTI::TargetCostKind CostKind) {
     assert(Ty->isIntegerTy());
+    unsigned BitSize = Ty->getPrimitiveSizeInBits();
+    // There is no cost model for constants with a bit size of 0. Return
+    // TCC_Free here, so that constant hoisting will ignore this constant.
+    if (BitSize == 0)
+      return TTI::TCC_Free;
+    // No cost model for operations on integers larger than 64 bit implemented
+    // yet.
+    if (BitSize > 64)
+      return TTI::TCC_Free;
+
     if (Imm == 0)
       return TTI::TCC_Free;
     if (isInt<16>(Imm.getSExtValue()))
       return TTI::TCC_Basic;
     if (isInt<21>(Imm.getZExtValue()))
       return TTI::TCC_Basic;
     if (isInt<32>(Imm.getSExtValue())) {
       if ((Imm.getSExtValue() & 0xFFFF) == 0)

llvm/test/CodeGen/Lanai/lowering-128.ll

 ; RUN: llc -march=lanai < %s | FileCheck %s
 
 ; Tests that lowering wide registers (128 bits or more) works on Lanai.
 ; The emitted assembly is not checked, we just do a smoketest.
 
 target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
 target triple = "lanai"
 
 ; CHECK-LABEL: add128:
 define i128 @add128(i128 %x, i128 %y) {
   %a = add i128 %x, %y
   ret i128 %a
 }
+
+; CHECK-LABEL: immshift128:
+define i128 @immshift128(i1 %sel) unnamed_addr {
+  %a = add i128 0, 340282366920938463463374007431768209319
+  %b = add i128 0, 340282366920938463463374607431768209320
+  %c = select i1 %sel, i128 %a, i128 %b
+  %d = shl i128 %a, 10
+  ret i128 %d
+}