[PowerPC] Fix return type of XL compat CAS

[lkail]

Summary

__compare_and_swap* should return i32 rather than i1.

[jsji]

LGTM. Thanks!

clang/lib/CodeGen/CGBuiltin.cpp

case PPC::BI__builtin_ppc_compare_and_swaplp: {
     // https://www.ibm.com/docs/en/xl-c-and-cpp-aix/16.1?topic=functions-compare-swap-compare-swaplp
     // > In either case, the contents of the memory location specified by addr
     // > are copied into the memory location specified by old_val_addr.
     // But it hasn't specified storing to OldValAddr is atomic or not and
     // which order to use. Now following XL's codegen, treat it as a normal
     // store.
     Value *LoadedVal = Pair.first.getScalarVal();
     Builder.CreateStore(LoadedVal, OldValAddr);
-    return Pair.second;
+    return Builder.CreateZExt(Pair.second, Builder.getInt32Ty());
   }
   case PPC::BI__builtin_ppc_fetch_and_add:
   case PPC::BI__builtin_ppc_fetch_and_addlp: {
     return MakeBinaryAtomicValue(*this, AtomicRMWInst::Add, E,
                                  llvm::AtomicOrdering::Monotonic);
   }
   case PPC::BI__builtin_ppc_fetch_and_and:
   case PPC::BI__builtin_ppc_fetch_and_andlp: {

clang/test/CodeGen/builtins-ppc-xlcompat-cas.c

 // CHECK-NEXT:    store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
 // CHECK-NEXT:    store i32 [[C:%.*]], i32* [[C_ADDR]], align 4
 // CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4
 // CHECK-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
 // CHECK-NEXT:    [[TMP2:%.*]] = cmpxchg weak volatile i32* [[A_ADDR]], i32 [[TMP1]], i32 [[TMP0]] monotonic monotonic, align 4
 // CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
 // CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
 // CHECK-NEXT:    store i32 [[TMP3]], i32* [[B_ADDR]], align 4
-// CHECK-NEXT:    ret void
+// CHECK-NEXT:    [[TMP5:%.*]] = zext i1 [[TMP4]] to i32
+// CHECK-NEXT:    ret i32 [[TMP5]]
 //
-void test_builtin_ppc_compare_and_swap(int a, int b, int c) {
-  __compare_and_swap(&a, &b, c);
+int test_builtin_ppc_compare_and_swap(int a, int b, int c) {
+  return __compare_and_swap(&a, &b, c);
 }
 
 
 // CHECK-LABEL: @test_builtin_ppc_compare_and_swaplp(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
 // CHECK-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 8
 // CHECK-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
 // CHECK-NEXT:    store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
 // CHECK-NEXT:    store i64 [[C:%.*]], i64* [[C_ADDR]], align 8
 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, i64* [[C_ADDR]], align 8
 // CHECK-NEXT:    [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
 // CHECK-NEXT:    [[TMP2:%.*]] = cmpxchg weak volatile i64* [[A_ADDR]], i64 [[TMP1]], i64 [[TMP0]] monotonic monotonic, align 8
 // CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0
 // CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1
 // CHECK-NEXT:    store i64 [[TMP3]], i64* [[B_ADDR]], align 8
-// CHECK-NEXT:    ret void
+// CHECK-NEXT:    [[TMP5:%.*]] = zext i1 [[TMP4]] to i32
+// CHECK-NEXT:    ret i32 [[TMP5]]
 //
-void test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
-  __compare_and_swaplp(&a, &b, c);
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c);
 }