Add disassembly for the conditioned RSUB immediate instruction for the ARC backend

[thomasjohns]

Summary

This adds an entry for a conditioned RSUB with a register-register-u6 pattern (e.g. rsub.ne %r0, %r0, 31) in ARCInstrInfo.td and ARCInstrFormats.td and demonstrates the ability to decode this instruction from an object file.

For example, when disassembling the object file derived from compiling:

int f(int x) {
  return __builtin_clz(x);
}

we used to have:

00000000 <f>:
       0: 2f 28 13 80   <unknown>
       4: ca 20 21 08   mov.eq  %r0, 32
       8: e0 7f         j_s.d   [%blink]
       a: ce 20 e2 07   <unknown>

but now we have:

00000000 <f>:
       0: 2f 28 13 80   <unknown>
       4: ca 20 21 08   mov.eq  %r0, 32
       8: e0 7f         j_s.d   [%blink]
       a: ce 20 e2 07   rsub.ne %r0, %r0, 31

This also adds two test cases for the disassembly of MOVcc_ru6 which where accidently dropped from a previous revision: https://reviews.llvm.org/D105560.

[marksl]

llvm/lib/Target/ARC/ARCInstrInfo.td

164

This form Refs=[STATUS32]

169

This form Defs=[STATUS32] and Refs=[STATUS32]

[thomasjohns]

llvm/lib/Target/ARC/ARCInstrInfo.td

169

Hi Mark, I'm not sure what Refs is referring to. Is there something that should be changed here?

[marksl]

llvm/lib/Target/ARC/ARCInstrInfo.td

169

Sorry, should be Uses=[STATUS32]

[thomasjohns]

Annotate that _cc_f_rru6 uses STATUS32 flag.