Add disassembly for the conditioned move immediate instruction for the ARC backend

[thomasjohns]

Summary

This adds and entry for MOVcc_ru6 (e.g. mov.eq %r0, 32) in ARCInstrInfo.td, its associated dependencies, and the ability to decode this instruction from an object file.

For example, when disassembling the object file derived from compiling:

int f(int x) {
  return __builtin_clz(x);
}

we used to have:

00000000 <f>:
       0: 2f 28 13 80   <unknown>
       4: ca 20 21 08   <unknown>
       8: e0 7f         j_s.d   [%blink]
       a: ce 20 e2 07   <unknown>

but now we have:

00000000 <f>:
       0: 2f 28 13 80   <unknown>
       4: ca 20 21 08   mov.eq  %r0, 32
       8: e0 7f         j_s.d   [%blink]
       a: ce 20 e2 07   <unknown>

[marksl]

Could you fix the issues reported by clang-tidy?

[gyiu]

Do we also need a LIT testcase for this under llvm/test/CodeGen/ARC?

[thomasjohns]

In D105560#2862649, @marksl wrote:

Could you fix the issues reported by clang-tidy?

Absolutely. Working on this now.

[thomasjohns]

In D105560#2862905, @gyiu wrote:

Do we also need a LIT testcase for this under llvm/test/CodeGen/ARC?

This change is only aiming to get the disassembly working (and thus the llvm/test/MC/Disassembler/ARC case). Our plan is to get the code-gen side of the CLZ intrinsic working in a follow up patch, and then we'll add the codegen LIT testcase there. Does this sound okay?

[gyiu]

In D105560#2862938, @thomasjohns wrote:

In D105560#2862905, @gyiu wrote:

Do we also need a LIT testcase for this under llvm/test/CodeGen/ARC?

This change is only aiming to get the disassembly working (and thus the llvm/test/MC/Disassembler/ARC case). Our plan is to get the code-gen side of the CLZ intrinsic working in a follow up patch, and then we'll add the codegen LIT testcase there. Does this sound okay?

Sounds good to me.

[thomasjohns]

Fix the straightforward clang-tidy lints.

[marksl]

Your change looks good to me

[thomasjohns]

llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp

110

The recommendation for this lint is to move to decodeCCRU6Instruction. However, most backends seem to follow the Decode* naming convention and we do too for other Decode methods.

Changing all our methods to decode* is one option (PowerPC does this), though it will increase the diff size by a fair amount.

Another option is to add // NOLINTNEXTLINE(readability-identifier-naming) comments which the AMDGPU backend does.

I feel like other backends might have either ignored this or have submitted code before the clang-tidy pre-merge check was around.

[thomasjohns]

llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp

14

For these, I need to do some research for how to workaround. With the way the buildkite bot checks this, it doesn't seem to pick up our compile_commands.json correctly or something like that.

llvm/lib/Target/ARC/ARCInstrFormats.td

class F32_SOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
   let Inst{23-22} = 0b00;
   let Inst{21-16} = 0b101111;
   let Inst{15} = F;
   let Inst{14-12} = B{5-3};
   let Inst{11-6} = C;
   let Inst{5-0} = subop;
 }
 
+// Single Operand Immediate Instructions.
+// 1-register, unsigned 6-bit immediate Single Operand instruction.
+// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
+// |B[2-0]  | 1| 1|            subop| F|B[5-3]  |U6           |1|cc       |
+class F32_SOP_CC_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
+                     string asmstr, list<dag> pattern> :
+  InstARC<4, outs, ins, asmstr, pattern> {
+
+  bits<5> cc;
+  bits<6> U6;
+  bits<6> B;
+
+  let Inst{31-27} = major;
+  let Inst{26-24} = B{2-0};
+  let Inst{23-22} = 0b11;
+  let Inst{21-16} = subop;
+  let Inst{15} = F;
+  let Inst{14-12} = B{5-3};
+  let Inst{11-6} = U6;
+  let Inst{5} = 1;
+  let Inst{4-0} = cc;
+
+  let DecoderMethod = "DecodeCCRU6Instruction";
+}
+
 // Dual Operand Instructions.  Inst[21-16] specifies the specific operation
 // for this format.
 
 // 3-register Dual Operand instruction.
 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
 // |B[2-0]  | 0| 0|            subop| F|B[5-3]  |C            |A          |
 class F32_DOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
                  string asmstr, list<dag> pattern> :

llvm/lib/Target/ARC/ARCInstrInfo.td

 //===- ARCInstrInfo.td - Target Description for ARC --------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the ARC instructions in TableGen format.
 //
 //===----------------------------------------------------------------------===//
 
 include "ARCInstrFormats.td"
 
+//===----------------------------------------------------------------------===//
+// Operand Pattern Stuff.
+//===----------------------------------------------------------------------===//
+
+// Operand for printing out a condition code.
+let PrintMethod = "printCCOperand" in
+  def CCOp : PredicateOperand<i32, (ops i32imm), (ops)>;
+
+// The "u6" operand of a RRU6-type instruction
+let PrintMethod = "printU6" in {
+  def u6 : Operand<i32>, ImmLeaf<i32, [{
+    return isUInt<6>(Imm);
+  }]>;
+  def wide_u6 : Operand<i64>, ImmLeaf<i64, [{
+    return isUInt<6>(Imm);
+  }]>;
+}
+
 // ---------------------------------------------------------------------------
 // Selection DAG Nodes.
 // ---------------------------------------------------------------------------
 
 // Selection DAG types.
 def SDT_ARCcmptst : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
 def SDT_ARCcmov : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>]>;
 def SDT_ARCmov : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>]>;

 
 def MOV_ru6 : F32_DOP_RU6<0b00100, 0b001010, 0,
                           (outs GPR32:$B), (ins immU6:$U6),
                           "mov\t$B, $U6", []>;
 
 def cmov : PatFrag<(ops node:$op1, node:$op2, node:$cc),
                    (ARCcmov $op1, $op2, $cc)>;
 let Uses = [STATUS32] in {
   def MOVcc : F32_DOP_CC_RR<0b00100, 0b001010, 0,
                  (outs GPR32:$B),
                  (ins GPR32:$C, GPR32:$fval, cmovpred:$cc),
                  !strconcat("mov.", "$cc\t$B, $C"),
                  [(set GPR32:$B, (cmov i32:$C, i32:$fval, cmovpred:$cc))]> {
     let Constraints = "$B = $fval";
   }
+
+  def MOVcc_ru6 : F32_SOP_CC_RU6<0b00100, 0b001010, 0,
+                 (outs GPR32:$b), (ins u6:$c, CCOp:$cc, GPR32:$b2),
+                 "mov.$cc\t$b, $c", []> {
+    let isAsCheapAsAMove=0;
+    let isPredicable=1;
+    let isReMaterializable=0;
+    let Constraints="$b2 = $b";
   }
+}
+
 def : Pat<(ARCGAWrapper tglobaladdr:$addr),
            (MOV_rlimm tglobaladdr:$addr)>;
 
 def : Pat<(ARCGAWrapper tjumptable:$addr),
            (MOV_rlimm tjumptable:$addr)>;
 
 
 // ---------------------------------------------------------------------------

llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp

 //===- ARCDisassembler.cpp - Disassembler for ARC ---------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file is part of the ARC Disassembler.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "ARC.h"
 #include "ARCRegisterInfo.h"
 #include "MCTargetDesc/ARCMCTargetDesc.h"
 #include "TargetInfo/ARCTargetInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
 #include "llvm/MC/MCFixedLenDisassembler.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrInfo.h"
static DecodeStatus DecodeLdLImmInstruction(MCInst &, uint64_t, uint64_t,
                                             const void *);
 
 static DecodeStatus DecodeStLImmInstruction(MCInst &, uint64_t, uint64_t,
                                             const void *);
 
 static DecodeStatus DecodeLdRLImmInstruction(MCInst &, uint64_t, uint64_t,
                                              const void *);
 
+static DecodeStatus DecodeCCRU6Instruction(MCInst &, uint64_t, uint64_t,
+                                           const void *);
+
 static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t, uint64_t,
                                               const void *);
 
 static const uint16_t GPR32DecoderTable[] = {
     ARC::R0,  ARC::R1,    ARC::R2,  ARC::R3,   ARC::R4,  ARC::R5,  ARC::R6,
     ARC::R7,  ARC::R8,    ARC::R9,  ARC::R10,  ARC::R11, ARC::R12, ARC::R13,
     ARC::R14, ARC::R15,   ARC::R16, ARC::R17,  ARC::R18, ARC::R19, ARC::R20,
     ARC::R21, ARC::R22,   ARC::R23, ARC::R24,  ARC::R25, ARC::GP,  ARC::FP,
static DecodeStatus DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address,
   unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9;
   DecodeGPR32RegisterClass(Inst, R, Address, Dec);
   Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S9)));
   return MCDisassembler::Success;
 }
 
 static bool DecodeSymbolicOperand(MCInst &Inst, uint64_t Address,
                                   uint64_t Value, const void *Decoder) {
-  static const uint64_t atLeast = 2;
+  static const uint64_t AtLeast = 2;
   // TODO: Try to force emitter to use MCDisassembler* instead of void*.
   auto Disassembler = static_cast<const MCDisassembler *>(Decoder);
   return (nullptr != Disassembler &&
           Disassembler->tryAddingSymbolicOperand(Inst, Value, Address, true, 0,
-                                                 atLeast));
+                                                 AtLeast));
 }
 
 static void DecodeSymbolicOperandOff(MCInst &Inst, uint64_t Address,
                                      uint64_t Offset, const void *Decoder) {
-  uint64_t nextAddress = Address + Offset;
+  uint64_t NextAddress = Address + Offset;
 
-  if (!DecodeSymbolicOperand(Inst, Address, nextAddress, Decoder))
+  if (!DecodeSymbolicOperand(Inst, Address, NextAddress, Decoder))
     Inst.addOperand(MCOperand::createImm(Offset));
 }
 
 template <unsigned B>
 static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS,
                                         uint64_t Address, const void *Decoder) {
 
   static_assert(B > 0, "field is empty");
static DecodeStatus DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn,
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t Insn,
                                               uint64_t Address,
                                               const void *Decoder) {
   LLVM_DEBUG(dbgs() << "Decoding MOV_S h-register\n");
   using Field = decltype(Insn);
-  Field h = fieldFromInstruction(Insn, 5, 3) |
+  Field H = fieldFromInstruction(Insn, 5, 3) |
             (fieldFromInstruction(Insn, 0, 2) << 3);
-  Field g = fieldFromInstruction(Insn, 8, 3) |
+  Field G = fieldFromInstruction(Insn, 8, 3) |
             (fieldFromInstruction(Insn, 3, 2) << 3);
 
   auto DecodeRegisterOrImm = [&Inst, Address, Decoder](Field RegNum,
                                                        Field Value) {
     if (30 == RegNum) {
       Inst.addOperand(MCOperand::createImm(Value));
       return MCDisassembler::Success;
     }
 
     return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder);
   };
 
-  if (MCDisassembler::Success != DecodeRegisterOrImm(g, 0))
+  if (MCDisassembler::Success != DecodeRegisterOrImm(G, 0))
     return MCDisassembler::Fail;
 
-  return DecodeRegisterOrImm(h, Insn >> 16u);
+  return DecodeRegisterOrImm(H, Insn >> 16u);
+}
+
+static DecodeStatus DecodeCCRU6Instruction(MCInst &Inst, uint64_t Insn,
+                                           uint64_t Address,
+                                           const void *Decoder) {
+  unsigned DstB;
+  LLVM_DEBUG(dbgs() << "Decoding CCRU6 instruction:\n");
+  DstB = decodeBField(Insn);
+  DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
+  using Field = decltype(Insn);
+  Field U6Field = fieldFromInstruction(Insn, 6, 11);
+  Inst.addOperand(MCOperand::createImm(U6Field));
+  Field CCField = fieldFromInstruction(Insn, 0, 4);
+  Inst.addOperand(MCOperand::createImm(CCField));
+  return MCDisassembler::Success;
 }
 
 DecodeStatus ARCDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
                                              ArrayRef<uint8_t> Bytes,
                                              uint64_t Address,
                                              raw_ostream &cStream) const {
   MCDisassembler::DecodeStatus Result;
   if (Bytes.size() < 2) {

llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h

public:
   // Autogenerated by tblgen.
   std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
   void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
   static const char *getRegisterName(unsigned RegNo);
 
   void printRegName(raw_ostream &OS, unsigned RegNo) const override;
   void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
                  const MCSubtargetInfo &STI, raw_ostream &O) override;
+  void printCCOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+  void printU6(const MCInst *MI, int OpNum, raw_ostream &O);
 
 private:
   void printMemOperandRI(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printOperand(const MCInst *MI, uint64_t /*Address*/, unsigned OpNum,
                     raw_ostream &O) {
     printOperand(MI, OpNum, O);
   }
   void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printBRCCPredicateOperand(const MCInst *MI, unsigned OpNum,
                                  raw_ostream &O);
+  void printU6ShiftedBy(unsigned ShiftBy, const MCInst *MI, int OpNum,
+                        raw_ostream &O);
 };
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H

llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp

 }
 
 void ARCInstPrinter::printBRCCPredicateOperand(const MCInst *MI, unsigned OpNum,
                                                raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNum);
   assert(Op.isImm() && "Predicate operand is immediate.");
   O << ARCBRCondCodeToString((ARCCC::BRCondCode)Op.getImm());
 }
+
+void ARCInstPrinter::printCCOperand(const MCInst *MI, int OpNum,
+                                    raw_ostream &O) {
+  O << ARCCondCodeToString((ARCCC::CondCode)MI->getOperand(OpNum).getImm());
+}
+
+void ARCInstPrinter::printU6ShiftedBy(unsigned ShiftBy, const MCInst *MI,
+                                      int OpNum, raw_ostream &O) {
+  const MCOperand &MO = MI->getOperand(OpNum);
+  if (MO.isImm()) {
+    unsigned Value = MO.getImm();
+    unsigned Value2 = Value >> ShiftBy;
+    if (Value2 > 0x3F || (Value2 << ShiftBy != Value)) {
+      errs() << "!!! Instruction has out-of-range U6 immediate operand:\n"
+             << "    Opcode is " << MI->getOpcode() << "; operand value is "
+             << Value;
+      if (ShiftBy)
+        errs() << " scaled by " << (1 << ShiftBy) << "\n";
+      assert(false && "instruction has wrong format");
+    }
+  }
+  printOperand(MI, OpNum, O);
+}
+
+void ARCInstPrinter::printU6(const MCInst *MI, int OpNum, raw_ostream &O) {
+  printU6ShiftedBy(0, MI, OpNum, O);
+}