Add disassembly for the conditioned RSUB immediate instruction for the ARC backend

[thomasjohns]

Summary

This adds an entry for a conditioned RSUB with a register-register-u6 pattern (e.g. rsub.ne %r0, %r0, 31) in ARCInstrInfo.td and ARCInstrFormats.td and demonstrates the ability to decode this instruction from an object file.

For example, when disassembling the object file derived from compiling:

int f(int x) {
  return __builtin_clz(x);
}

we used to have:

00000000 <f>:
       0: 2f 28 13 80   <unknown>
       4: ca 20 21 08   mov.eq  %r0, 32
       8: e0 7f         j_s.d   [%blink]
       a: ce 20 e2 07   <unknown>

but now we have:

00000000 <f>:
       0: 2f 28 13 80   <unknown>
       4: ca 20 21 08   mov.eq  %r0, 32
       8: e0 7f         j_s.d   [%blink]
       a: ce 20 e2 07   rsub.ne %r0, %r0, 31

This also adds two test cases for the disassembly of MOVcc_ru6 which where accidently dropped from a previous revision: https://reviews.llvm.org/D105560.

[marksl]

llvm/lib/Target/ARC/ARCInstrInfo.td

164

This form Refs=[STATUS32]

169

This form Defs=[STATUS32] and Refs=[STATUS32]

[thomasjohns]

llvm/lib/Target/ARC/ARCInstrInfo.td

169

Hi Mark, I'm not sure what Refs is referring to. Is there something that should be changed here?

[marksl]

llvm/lib/Target/ARC/ARCInstrInfo.td

169

Sorry, should be Uses=[STATUS32]

[thomasjohns]

Annotate that _cc_f_rru6 uses STATUS32 flag.

llvm/lib/Target/ARC/ARCInstrFormats.td

class F32_SOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
   let Inst{21-16} = 0b101111;
   let Inst{15} = F;
   let Inst{14-12} = B{5-3};
   let Inst{11-6} = C;
   let Inst{5-0} = subop;
 }
 
 // Single Operand Immediate Instructions.
-// 1-register, unsigned 6-bit immediate Single Operand instruction.
+// 1-register, unsigned 6-bit immediate Single Operand instruction with
+// condition code.
 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
 // |B[2-0]  | 1| 1|            subop| F|B[5-3]  |U6           |1|cc       |
 class F32_SOP_CC_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
                      string asmstr, list<dag> pattern> :
   InstARC<4, outs, ins, asmstr, pattern> {
 
   bits<5> cc;
   bits<6> U6;
class F32_DOP_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
   let Inst{23-22} = 0b01;
   let Inst{21-16} = subop;
   let Inst{15} = F;
   let Inst{14-12} = B{5-3};
   let Inst{11-6} = U6;
   let Inst{5-0} = A;
 }
 
+// 2-register, unsigned 6-bit immediate Dual Operand instruction with
+// condition code. This instruction uses B as the first 2 operands
+// (i.e, add.cc B, B, u6).
+// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
+// |B[2-0]  | 1| 1|            subop| F|B[5-3]  |U6           |1|cc       |
+class F32_DOP_CC_RRU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
+                      string asmstr, list<dag> pattern> :
+  InstARC<4, outs, ins, asmstr, pattern> {
+  bits<5> cc;
+  bits<6> U6;
+  bits<6> B;
+  bits<6> A;
+
+  let Inst{31-27} = major;
+  let Inst{26-24} = B{2-0};
+  let Inst{23-22} = 0b11;
+  let Inst{21-16} = subop;
+  let Inst{15} = F;
+  let Inst{14-12} = B{5-3};
+  let Inst{11-6} = U6;
+  let Inst{5} = 1;
+  let Inst{4-0} = cc;
+}
+
 // 2-register, signed 12-bit immediate Dual Operand instruction.
 // This instruction uses B as the first 2 operands (i.e., add B, B, -128).
 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
 // |B[2-0]  | 1| 0|            subop| F|B[5-3]  |S12[5-0]     |S12[11-6]  |
 class F32_DOP_RS12<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
                    string asmstr, list<dag> pattern> :
   InstARC<4, outs, ins, asmstr, pattern> {
   bits<6> B;

llvm/lib/Target/ARC/ARCInstrInfo.td

def _rru6 : F32_DOP_RU6<major, mincode, 0, (outs GPR32:$A),
                           !strconcat(opasm, "\t$A, $B, $U6"),
                           []>;
   def _f_rru6 : F32_DOP_RU6<major, mincode, 1, (outs GPR32:$A),
                             (ins GPR32:$B, immU6:$U6),
                             !strconcat(opasm, ".f\t$A, $B, $U6"),
                             []>
   { let Defs = [STATUS32]; }
 
+  def _cc_rru6 : F32_DOP_CC_RRU6<major, mincode, 0, (outs GPR32:$A),
+                                 (ins immU6:$U6, ccond:$cc, GPR32:$B),
+                                 !strconcat(opasm, ".$cc\t$A, $B, $U6"),
+                                 []> {
+                                   let Uses = [STATUS32];
+                                   let Constraints = "$A = $B";
+                                 }
+
+  def _cc_f_rru6 : F32_DOP_CC_RRU6<major, mincode, 1, (outs GPR32:$A),
+                                   (ins immU6:$U6, ccond:$cc, GPR32:$B),
+                                   !strconcat(opasm, ".$cc.f\t$A, $B, $U6"),
+                                   []> {
+                                     let Defs = [STATUS32];
+                                     let Uses = [STATUS32];
+                                     let Constraints = "$A = $B";
+                                   }
+
   // 2 register with 32-bit immediate variant.
   def _rrlimm : F32_DOP_RLIMM<major, mincode, 0,
                               (outs GPR32:$A),
                               (ins GPR32:$B, i32imm:$LImm),
                               !strconcat(opasm, "\t$A, $B, $LImm"),
                               []>;
   def _f_rrlimm : F32_DOP_RLIMM<major, mincode, 1,
                                 (outs GPR32:$A),

 // ---------------------------------------------------------------------------
 
 // Definitions for 3 operand binary instructions.
 defm ADD : ArcBinaryGEN4Inst<0b000000, "add",1>;
 defm SUB : ArcBinaryGEN4Inst<0b000010, "sub">;
 defm SUB1 : ArcBinaryGEN4Inst<0b010111, "sub1">;
 defm SUB2 : ArcBinaryGEN4Inst<0b011000, "sub2">;
 defm SUB3 : ArcBinaryGEN4Inst<0b011001, "sub3">;
+defm RSUB : ArcBinaryGEN4Inst<0b001110, "rsub">;
 defm OR  : ArcBinaryGEN4Inst<0b000101, "or",1>;
 defm AND : ArcBinaryGEN4Inst<0b000100, "and",1>;
 defm XOR : ArcBinaryGEN4Inst<0b000111, "xor",1>;
 defm MAX : ArcBinaryGEN4Inst<0b001000, "max",1>;
 defm MIN : ArcBinaryGEN4Inst<0b001001, "min",1>;
 defm ASL : ArcBinaryEXT5Inst<0b000000, "asl">;
 defm LSR : ArcBinaryEXT5Inst<0b000001, "lsr">;
 defm ASR : ArcBinaryEXT5Inst<0b000010, "asr">;

llvm/test/MC/Disassembler/ARC/alu.txt

 # CHECK: sub2 %r3, %fp, 17
 0x58 0x23 0x43 0x34
 
 # CHECK: sub3 %fp, %fp, -1
 0x99 0x23 0xff 0x3f
 
 # CHECK: sub3.f %fp, %fp, -1
 0x99 0x23 0xff 0xbf
+
+# CHECK: rsub.eq %r0, %r0, 30
+0xce 0x20 0xa1 0x07
+
+# CHECK: rsub.ne %r0, %r0, 31
+0xce 0x20 0xe2 0x07
+
+# CHECK: rsub.ne.f %r0, %r0, 31
+0xce 0x20 0xe2 0x87

llvm/test/MC/Disassembler/ARC/misc.txt

 0xca 0x22 0x81 0x01
 
 # CHECK: mov %r13, %r2
 0x0a 0x25 0x80 0x10
 
 # CHECK: mov %r1, 20
 0x4a 0x21 0x00 0x05
 
+# CHECK: mov.eq %r0, 32
+0xca 0x20 0x21 0x08
+
+# CHECK: mov.ne %r0, 0
+0xca 0x20 0x22 0x00
+
 # CHECK: st.aw %fp, [%sp,-4]
 0xfc 0x1c 0xc8 0xb6
 
 # CHECK: ld.ab %fp, [%sp,4]
 0x04 0x14 0x1b 0x34
 
 # CHECK: bl -2028
 0x16 0x08 0xcf 0xff