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Differential D106210

[MS] Preserve base register %esi around movs[bwl]
ClosedPublic

Authored by namazso on Jul 16 2021, 9:14 PM.

Details

Reviewers
echristo
rnk
craig.topper
Commits
rG91bc85b1ebaa: [MS] Preserve base register %esi around movs[bwl]
Summary

fix for behavior reported in https://bugs.llvm.org/show_bug.cgi?id=51100 workaround for root cause https://bugs.llvm.org/show_bug.cgi?id=16830

similar to https://reviews.llvm.org/D101338

Diff Detail

Event Timeline

namazso requested review of this revision.Jul 16 2021, 9:14 PM
namazso created this revision.
Herald added a subscriber: cfe-commits. · View Herald TranscriptJul 16 2021, 9:14 PM
namazso edited the summary of this revision. (Show Details)Jul 16 2021, 9:16 PM
Harbormaster completed remote builds in B114660: Diff 359526.Jul 16 2021, 9:53 PM
namazso updated this revision to Diff 359550.Jul 17 2021, 1:45 AM

fix linter warnings, update tests

Harbormaster completed remote builds in B114674: Diff 359550.Jul 17 2021, 2:22 AM
namazso added reviewers: echristo, rnk.Jul 17 2021, 2:32 AM
craig.topper accepted this revision.Jul 17 2021, 11:32 AM
craig.topper added a subscriber: craig.topper.

LGTM

This revision is now accepted and ready to land.Jul 17 2021, 11:32 AM
namazso added a comment.Jul 17 2021, 12:08 PM

I don't have commit access, could someone commit this for me? Thanks in advance.

craig.topper added a comment.Jul 18 2021, 1:35 PM
In D106210#2885538, @namazso wrote:

I don't have commit access, could someone commit this for me? Thanks in advance.

I can commit it. How would you like your name to appear in the author line of the git log?

namazso added a comment.Jul 18 2021, 2:48 PM

i'd prefer it as just namazso with email admin@namazso.eu

This revision was landed with ongoing or failed builds.Jul 23 2021, 1:28 AM
Closed by commit rG91bc85b1ebaa: [MS] Preserve base register %esi around movs[bwl] (authored by namazso, committed by Wang, Pengfei <pengfei.wang@intel.com>). · Explain Why
This revision was automatically updated to reflect the committed changes.
pengfei added a commit: rG91bc85b1ebaa: [MS] Preserve base register %esi around movs[bwl].
pengfei added a subscriber: pengfei.Jul 23 2021, 1:30 AM

Happened to see it. I thought Craig might miss it.

craig.topper added a comment.Jul 23 2021, 10:16 AM
In D106210#2899361, @pengfei wrote:

Happened to see it. I thought Craig might miss it.

Thanks @pengfei

Revision Contents

PathSize
clang/
lib/
Headers/
27 lines
test/
CodeGen/
6 lines

Diff 361122

clang/lib/Headers/intrin.h

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/*----------------------------------------------------------------------------*\ /*----------------------------------------------------------------------------*\
|* movs, stos |* movs, stos
\*----------------------------------------------------------------------------*/ \*----------------------------------------------------------------------------*/
#if defined(__i386__) || defined(__x86_64__) #if defined(__i386__) || defined(__x86_64__)
static __inline__ void __DEFAULT_FN_ATTRS __movsb(unsigned char *__dst, static __inline__ void __DEFAULT_FN_ATTRS __movsb(unsigned char *__dst,
unsigned char const *__src, unsigned char const *__src,
size_t __n) { size_t __n) {
__asm__ __volatile__("rep movsb" : "+D"(__dst), "+S"(__src), "+c"(__n) #if defined(__x86_64__)
: : "memory"); __asm__ __volatile__("rep movsb"
: "+D"(__dst), "+S"(__src), "+c"(__n)
:
: "memory");
#else
__asm__ __volatile__("xchg %%esi, %1\nrep movsb\nxchg %%esi, %1"
: "+D"(__dst), "+r"(__src), "+c"(__n)
:
: "memory");
#endif
} }
static __inline__ void __DEFAULT_FN_ATTRS __movsd(unsigned long *__dst, static __inline__ void __DEFAULT_FN_ATTRS __movsd(unsigned long *__dst,
unsigned long const *__src, unsigned long const *__src,
size_t __n) { size_t __n) {
#if defined(__x86_64__)
__asm__ __volatile__("rep movsl" __asm__ __volatile__("rep movsl"
: "+D"(__dst), "+S"(__src), "+c"(__n) : "+D"(__dst), "+S"(__src), "+c"(__n)
: :
: "memory"); : "memory");
#else
__asm__ __volatile__("xchg %%esi, %1\nrep movsl\nxchg %%esi, %1"
: "+D"(__dst), "+r"(__src), "+c"(__n)
:
: "memory");
#endif
} }
static __inline__ void __DEFAULT_FN_ATTRS __movsw(unsigned short *__dst, static __inline__ void __DEFAULT_FN_ATTRS __movsw(unsigned short *__dst,
unsigned short const *__src, unsigned short const *__src,
size_t __n) { size_t __n) {
#if defined(__x86_64__)
__asm__ __volatile__("rep movsw" __asm__ __volatile__("rep movsw"
: "+D"(__dst), "+S"(__src), "+c"(__n) : "+D"(__dst), "+S"(__src), "+c"(__n)
: :
: "memory"); : "memory");
#else
__asm__ __volatile__("xchg %%esi, %1\nrep movsw\nxchg %%esi, %1"
: "+D"(__dst), "+r"(__src), "+c"(__n)
:
: "memory");
#endif
} }
static __inline__ void __DEFAULT_FN_ATTRS __stosd(unsigned long *__dst, static __inline__ void __DEFAULT_FN_ATTRS __stosd(unsigned long *__dst,
unsigned long __x, unsigned long __x,
size_t __n) { size_t __n) {
__asm__ __volatile__("rep stosl" __asm__ __volatile__("rep stosl"
: "+D"(__dst), "+c"(__n) : "+D"(__dst), "+c"(__n)
: "a"(__x) : "a"(__x)
: "memory"); : "memory");
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clang/test/CodeGen/ms-intrinsics.c

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// CHECK-X64: tail call void @llvm.memset.p0i8.i64(i8* align 1 %Dest, i8 %Data, i64 %Count, i1 true) // CHECK-X64: tail call void @llvm.memset.p0i8.i64(i8* align 1 %Dest, i8 %Data, i64 %Count, i1 true)
// CHECK-X64: ret void // CHECK-X64: ret void
// CHECK-X64: } // CHECK-X64: }
void test__movsb(unsigned char *Dest, unsigned char *Src, size_t Count) { void test__movsb(unsigned char *Dest, unsigned char *Src, size_t Count) {
return __movsb(Dest, Src, Count); return __movsb(Dest, Src, Count);
} }
// CHECK-I386-LABEL: define{{.*}} void @test__movsb // CHECK-I386-LABEL: define{{.*}} void @test__movsb
// CHECK-I386: call { i8*, i8*, i32 } asm sideeffect "rep movsb", "={di},={si},={cx},0,1,2,~{memory},~{dirflag},~{fpsr},~{flags}"(i8* %Dest, i8* %Src, i32 %Count) // CHECK-I386: tail call { i8*, i8*, i32 } asm sideeffect "xchg %esi, $1\0Arep movsb\0Axchg %esi, $1", "={di},=r,={cx},0,1,2,~{memory},~{dirflag},~{fpsr},~{flags}"(i8* %Dest, i8* %Src, i32 %Count)
// CHECK-I386: ret void // CHECK-I386: ret void
// CHECK-I386: } // CHECK-I386: }
// CHECK-X64-LABEL: define{{.*}} void @test__movsb // CHECK-X64-LABEL: define{{.*}} void @test__movsb
// CHECK-X64: call { i8*, i8*, i64 } asm sideeffect "rep movsb", "={di},={si},={cx},0,1,2,~{memory},~{dirflag},~{fpsr},~{flags}"(i8* %Dest, i8* %Src, i64 %Count) // CHECK-X64: call { i8*, i8*, i64 } asm sideeffect "rep movsb", "={di},={si},={cx},0,1,2,~{memory},~{dirflag},~{fpsr},~{flags}"(i8* %Dest, i8* %Src, i64 %Count)
// CHECK-X64: ret void // CHECK-X64: ret void
// CHECK-X64: } // CHECK-X64: }
Show All 9 Lines
// CHECK-X64: call { i16*, i64 } asm sideeffect "rep stosw", "={di},={cx},{ax},0,1,~{memory},~{dirflag},~{fpsr},~{flags}"(i16 %Data, i16* %Dest, i64 %Count) // CHECK-X64: call { i16*, i64 } asm sideeffect "rep stosw", "={di},={cx},{ax},0,1,~{memory},~{dirflag},~{fpsr},~{flags}"(i16 %Data, i16* %Dest, i64 %Count)
// CHECK-X64: ret void // CHECK-X64: ret void
// CHECK-X64: } // CHECK-X64: }
void test__movsw(unsigned short *Dest, unsigned short *Src, size_t Count) { void test__movsw(unsigned short *Dest, unsigned short *Src, size_t Count) {
return __movsw(Dest, Src, Count); return __movsw(Dest, Src, Count);
} }
// CHECK-I386-LABEL: define{{.*}} void @test__movsw // CHECK-I386-LABEL: define{{.*}} void @test__movsw
// CHECK-I386: call { i16*, i16*, i32 } asm sideeffect "rep movsw", "={di},={si},={cx},0,1,2,~{memory},~{dirflag},~{fpsr},~{flags}"(i16* %Dest, i16* %Src, i32 %Count) // CHECK-I386: tail call { i16*, i16*, i32 } asm sideeffect "xchg %esi, $1\0Arep movsw\0Axchg %esi, $1", "={di},=r,={cx},0,1,2,~{memory},~{dirflag},~{fpsr},~{flags}"(i16* %Dest, i16* %Src, i32 %Count)
// CHECK-I386: ret void // CHECK-I386: ret void
// CHECK-I386: } // CHECK-I386: }
// CHECK-X64-LABEL: define{{.*}} void @test__movsw // CHECK-X64-LABEL: define{{.*}} void @test__movsw
// CHECK-X64: call { i16*, i16*, i64 } asm sideeffect "rep movsw", "={di},={si},={cx},0,1,2,~{memory},~{dirflag},~{fpsr},~{flags}"(i16* %Dest, i16* %Src, i64 %Count) // CHECK-X64: call { i16*, i16*, i64 } asm sideeffect "rep movsw", "={di},={si},={cx},0,1,2,~{memory},~{dirflag},~{fpsr},~{flags}"(i16* %Dest, i16* %Src, i64 %Count)
// CHECK-X64: ret void // CHECK-X64: ret void
// CHECK-X64: } // CHECK-X64: }
Show All 9 Lines
// CHECK-X64: call { i32*, i64 } asm sideeffect "rep stosl", "={di},={cx},{ax},0,1,~{memory},~{dirflag},~{fpsr},~{flags}"(i32 %Data, i32* %Dest, i64 %Count) // CHECK-X64: call { i32*, i64 } asm sideeffect "rep stosl", "={di},={cx},{ax},0,1,~{memory},~{dirflag},~{fpsr},~{flags}"(i32 %Data, i32* %Dest, i64 %Count)
// CHECK-X64: ret void // CHECK-X64: ret void
// CHECK-X64: } // CHECK-X64: }
void test__movsd(unsigned long *Dest, unsigned long *Src, size_t Count) { void test__movsd(unsigned long *Dest, unsigned long *Src, size_t Count) {
return __movsd(Dest, Src, Count); return __movsd(Dest, Src, Count);
} }
// CHECK-I386-LABEL: define{{.*}} void @test__movsd // CHECK-I386-LABEL: define{{.*}} void @test__movsd
// CHECK-I386: call { i32*, i32*, i32 } asm sideeffect "rep movsl", "={di},={si},={cx},0,1,2,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %Dest, i32* %Src, i32 %Count) // CHECK-I386: tail call { i32*, i32*, i32 } asm sideeffect "xchg %esi, $1\0Arep movsl\0Axchg %esi, $1", "={di},=r,={cx},0,1,2,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %Dest, i32* %Src, i32 %Count)
// CHECK-I386: ret void // CHECK-I386: ret void
// CHECK-I386: } // CHECK-I386: }
// CHECK-X64-LABEL: define{{.*}} void @test__movsd // CHECK-X64-LABEL: define{{.*}} void @test__movsd
// CHECK-X64: call { i32*, i32*, i64 } asm sideeffect "rep movsl", "={di},={si},={cx},0,1,2,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %Dest, i32* %Src, i64 %Count) // CHECK-X64: call { i32*, i32*, i64 } asm sideeffect "rep movsl", "={di},={si},={cx},0,1,2,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %Dest, i32* %Src, i64 %Count)
// CHECK-X64: ret void // CHECK-X64: ret void
// CHECK-X64: } // CHECK-X64: }
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